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merged changes in eth

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This commit is contained in:
Alex Forencich 2022-03-16 21:09:16 -07:00
commit cb44b2ee60
35 changed files with 236 additions and 221 deletions
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26
fpga/lib/eth/rtl/ptp_clock.v
View File

@ -184,15 +184,7 @@ always @(posedge clk) begin
end
// 96 bit timestamp
if (input_ts_96_valid) begin
// load timestamp
{ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= (FNS_WIDTH > 16 ? input_ts_96[45:0] << (FNS_WIDTH-16) : input_ts_96[45:0] >> (16-FNS_WIDTH)) + {ts_inc_ns_reg, ts_inc_fns_reg};
{ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} <= (FNS_WIDTH > 16 ? input_ts_96[45:0] << (FNS_WIDTH-16) : input_ts_96[45:0] >> (16-FNS_WIDTH)) + {ts_inc_ns_reg, ts_inc_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}};
ts_96_s_reg <= input_ts_96[95:48];
ts_96_ns_reg <= input_ts_96[45:16];
ts_96_fns_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
ts_step_reg <= 1;
end else if (!ts_96_ns_ovf_reg[30]) begin
if (!ts_96_ns_ovf_reg[30]) begin
// if the overflow lookahead did not borrow, one second has elapsed
// increment seconds field, pre-compute both normal increment and overflow values
{ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
@ -207,13 +199,25 @@ always @(posedge clk) begin
ts_96_s_reg <= ts_96_s_reg;
end
if (input_ts_96_valid) begin
// load timestamp
ts_96_s_reg <= input_ts_96[95:48];
ts_96_ns_reg <= input_ts_96[45:16];
ts_96_ns_inc_reg <= input_ts_96[45:16];
ts_96_ns_ovf_reg <= 31'h7fffffff;
ts_96_fns_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
ts_96_fns_inc_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
ts_96_fns_ovf_reg <= {FNS_WIDTH{1'b1}};
ts_step_reg <= 1;
end
// 64 bit timestamp
{ts_64_ns_reg, ts_64_fns_reg} <= {ts_64_ns_reg, ts_64_fns_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
if (input_ts_64_valid) begin
// load timestamp
{ts_64_ns_reg, ts_64_fns_reg} <= input_ts_64;
ts_step_reg <= 1;
end else begin
{ts_64_ns_reg, ts_64_fns_reg} <= {ts_64_ns_reg, ts_64_fns_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
end
pps_reg <= !ts_96_ns_ovf_reg[30];

30
fpga/lib/eth/rtl/ptp_clock_cdc.v
View File

@ -431,7 +431,8 @@ reg sec_mismatch_reg = 1'b0, sec_mismatch_next;
reg diff_valid_reg = 1'b0, diff_valid_next;
reg diff_corr_valid_reg = 1'b0, diff_corr_valid_next;
reg [47:0] ts_s_diff_reg = 0, ts_s_diff_next;
reg ts_s_msb_diff_reg = 1'b0, ts_s_msb_diff_next;
reg [7:0] ts_s_diff_reg = 0, ts_s_diff_next;
reg [TS_NS_WIDTH+1-1:0] ts_ns_diff_reg = 0, ts_ns_diff_next;
reg [FNS_WIDTH-1:0] ts_fns_diff_reg = 0, ts_fns_diff_next;
@ -467,14 +468,15 @@ always @* begin
sec_mismatch_next = sec_mismatch_reg;
diff_valid_next = 1'b0;
diff_corr_valid_next = 1'b0;
ts_s_msb_diff_next = ts_s_msb_diff_reg;
ts_s_diff_next = ts_s_diff_reg;
ts_ns_diff_next = ts_ns_diff_reg;
ts_fns_diff_next = ts_fns_diff_reg;
ts_ns_diff_corr_next = ts_ns_diff_corr_reg;
ts_fns_diff_corr_next = ts_fns_diff_corr_reg;
time_err_int_next = time_err_int_reg;
ptp_lock_count_next = ptp_lock_count_reg;
@ -509,19 +511,23 @@ always @* begin
// input stepped
sec_mismatch_next = 1'b0;
{ts_ns_inc_next, ts_fns_inc_next} = {ts_ns_sync_reg, ts_fns_sync_reg} + {period_ns_reg, period_fns_reg};
{ts_ns_ovf_next, ts_fns_ovf_next} = {ts_ns_sync_reg, ts_fns_sync_reg} + {period_ns_reg, period_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}};
ts_s_next = ts_s_sync_reg;
ts_ns_next = ts_ns_sync_reg;
ts_ns_inc_next = ts_ns_sync_reg;
ts_ns_ovf_next = {TS_NS_WIDTH+1{1'b1}};
ts_fns_next = ts_fns_sync_reg;
ts_fns_inc_next = ts_fns_sync_reg;
ts_fns_ovf_next = {FNS_WIDTH{1'b1}};
ts_step_next = 1;
end else begin
// compute difference
// input did not step
sec_mismatch_next = 1'b0;
diff_valid_next = 1'b1;
ts_s_diff_next = ts_s_sync_reg - dest_ts_s_capt_reg;
{ts_ns_diff_next, ts_fns_diff_next} = {ts_ns_sync_reg, ts_fns_sync_reg} - {dest_ts_ns_capt_reg, dest_ts_fns_capt_reg};
end
// compute difference
ts_s_msb_diff_next = ts_s_sync_reg[47:8] != dest_ts_s_capt_reg[47:8];
ts_s_diff_next = ts_s_sync_reg[7:0] - dest_ts_s_capt_reg[7:0];
{ts_ns_diff_next, ts_fns_diff_next} = {ts_ns_sync_reg, ts_fns_sync_reg} - {dest_ts_ns_capt_reg, dest_ts_fns_capt_reg};
end else if (TS_WIDTH == 64) begin
if (ts_step_sync_reg || sec_mismatch_reg) begin
// input stepped
@ -531,18 +537,19 @@ always @* begin
ts_fns_next = ts_fns_sync_reg;
ts_step_next = 1;
end else begin
// compute difference
// input did not step
sec_mismatch_next = 1'b0;
diff_valid_next = 1'b1;
{ts_ns_diff_next, ts_fns_diff_next} = {ts_ns_sync_reg, ts_fns_sync_reg} - {dest_ts_ns_capt_reg, dest_ts_fns_capt_reg};
end
// compute difference
{ts_ns_diff_next, ts_fns_diff_next} = {ts_ns_sync_reg, ts_fns_sync_reg} - {dest_ts_ns_capt_reg, dest_ts_fns_capt_reg};
end
end
if (diff_valid_reg) begin
// seconds field correction
if (TS_WIDTH == 96) begin
if ($signed(ts_s_diff_reg) == 0 && ($signed(ts_ns_diff_reg[30:16]) == 0 || $signed(ts_ns_diff_reg[30:16]) == -1)) begin
if ($signed(ts_s_diff_reg) == 0 && ts_s_msb_diff_reg == 0 && ($signed(ts_ns_diff_reg[30:16]) == 0 || $signed(ts_ns_diff_reg[30:16]) == -1)) begin
// difference is small and no seconds difference; slew
ts_ns_diff_corr_next = ts_ns_diff_reg[16:0];
ts_fns_diff_corr_next = ts_fns_diff_reg;
@ -641,6 +648,7 @@ always @(posedge output_clk) begin
diff_valid_reg <= diff_valid_next;
diff_corr_valid_reg <= diff_corr_valid_next;
ts_s_msb_diff_reg <= ts_s_msb_diff_next;
ts_s_diff_reg <= ts_s_diff_next;
ts_ns_diff_reg <= ts_ns_diff_next;
ts_fns_diff_reg <= ts_fns_diff_next;

12
fpga/lib/eth/tb/arp/test_arp.py
View File

@ -93,10 +93,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -138,10 +138,10 @@ async def run_test(dut, idle_inserter=None, backpressure_inserter=None):
gateway_ip = '192.168.1.1'
subnet_mask = '255.255.255.0'
dut.local_mac <= int.from_bytes(mac2str(local_mac), 'big')
dut.local_ip <= atol(local_ip)
dut.gateway_ip <= atol(gateway_ip)
dut.subnet_mask <= atol(subnet_mask)
dut.local_mac.value = int.from_bytes(mac2str(local_mac), 'big')
dut.local_ip.value = atol(local_ip)
dut.gateway_ip.value = atol(gateway_ip)
dut.subnet_mask.value = atol(subnet_mask)
for k in range(10):
await RisingEdge(dut.clk)

8
fpga/lib/eth/tb/arp_cache/test_arp_cache.py
View File

@ -62,10 +62,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -195,9 +195,9 @@ async def run_test(dut):
tb.log.info("Clear cache")
await RisingEdge(dut.clk)
dut.clear_cache <= 1
dut.clear_cache.value = 1
await RisingEdge(dut.clk)
dut.clear_cache <= 0
dut.clear_cache.value = 0
await tb.query_request_source.send(CacheOpTransaction(ip=0xc0a80111))

4
fpga/lib/eth/tb/arp_eth_rx/test_arp_eth_rx.py
View File

@ -79,10 +79,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
fpga/lib/eth/tb/arp_eth_tx/test_arp_eth_tx.py
View File

@ -79,10 +79,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
fpga/lib/eth/tb/axis_baser_rx_64/test_axis_baser_rx_64.py
View File

@ -67,10 +67,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

8
fpga/lib/eth/tb/axis_baser_tx_64/test_axis_baser_tx_64.py
View File

@ -68,10 +68,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -80,7 +80,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -109,7 +109,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
for length in range(60, 92):

8
fpga/lib/eth/tb/axis_gmii_rx/test_axis_gmii_rx.py
View File

@ -62,10 +62,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -84,7 +84,7 @@ class TB:
async def _run_enable(self):
for val in self._enable_generator:
self.dut.clk_enable <= val
self.dut.clk_enable.value = val
await RisingEdge(self.dut.clk)
@ -93,7 +93,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
tb = TB(dut)
tb.source.ifg = ifg
tb.dut.mii_select <= mii_sel
tb.dut.mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator(enable_gen())

10
fpga/lib/eth/tb/axis_gmii_tx/test_axis_gmii_tx.py
View File

@ -63,10 +63,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -85,7 +85,7 @@ class TB:
async def _run_enable(self):
for val in self._enable_generator:
self.dut.clk_enable <= val
self.dut.clk_enable.value = val
await RisingEdge(self.dut.clk)
@ -93,8 +93,8 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
tb = TB(dut)
tb.dut.ifg_delay <= ifg
tb.dut.mii_select <= mii_sel
tb.dut.ifg_delay.value = ifg
tb.dut.mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator(enable_gen())

4
fpga/lib/eth/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py
View File

@ -56,10 +56,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
fpga/lib/eth/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py
View File

@ -56,10 +56,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

8
fpga/lib/eth/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py
View File

@ -58,10 +58,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -70,7 +70,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -99,7 +99,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
for length in range(60, 92):

8
fpga/lib/eth/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py
View File

@ -58,10 +58,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -70,7 +70,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -99,7 +99,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
for length in range(60, 92):

4
fpga/lib/eth/tb/baser.py
View File

@ -358,8 +358,8 @@ class BaseRSerdesSource():
data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1)
self.data <= data
self.header <= header
self.data.value = data
self.header.value = header
class BaseRSerdesSink:

4
fpga/lib/eth/tb/eth_axis_rx/test_eth_axis_rx.py
View File

@ -73,10 +73,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
fpga/lib/eth/tb/eth_axis_tx/test_eth_axis_tx.py
View File

@ -74,10 +74,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

14
fpga/lib/eth/tb/eth_mac_10g/test_eth_mac_10g.py
View File

@ -67,12 +67,12 @@ class TB:
self.dut.tx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.rx_clk)
await RisingEdge(self.dut.rx_clk)
self.dut.rx_rst <= 1
self.dut.tx_rst <= 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
await RisingEdge(self.dut.rx_clk)
await RisingEdge(self.dut.rx_clk)
self.dut.rx_rst <= 0
self.dut.tx_rst <= 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
await RisingEdge(self.dut.rx_clk)
await RisingEdge(self.dut.rx_clk)
@ -82,7 +82,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -109,7 +109,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -139,7 +139,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
for length in range(60, 92):

18
fpga/lib/eth/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py
View File

@ -71,14 +71,14 @@ class TB:
self.dut.tx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst <= 1
self.dut.rx_rst <= 1
self.dut.tx_rst <= 1
self.dut.logic_rst.value = 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst <= 0
self.dut.rx_rst <= 0
self.dut.tx_rst <= 0
self.dut.logic_rst.value = 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
@ -88,7 +88,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -115,7 +115,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -145,7 +145,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
for length in range(60, 92):

24
fpga/lib/eth/tb/eth_mac_1g/test_eth_mac_1g.py
View File

@ -74,12 +74,12 @@ class TB:
self.dut.tx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.rx_rst <= 1
self.dut.tx_rst <= 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.rx_rst <= 0
self.dut.tx_rst <= 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
@ -111,12 +111,12 @@ class TB:
async def _run_enable_rx(self):
for val in self._enable_generator_rx:
self.dut.rx_clk_enable <= val
self.dut.rx_clk_enable.value = val
await RisingEdge(self.dut.rx_clk)
async def _run_enable_tx(self):
for val in self._enable_generator_tx:
self.dut.tx_clk_enable <= val
self.dut.tx_clk_enable.value = val
await RisingEdge(self.dut.tx_clk)
@ -125,9 +125,9 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.rx_mii_select <= mii_sel
tb.dut.tx_mii_select <= mii_sel
tb.dut.ifg_delay.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator_rx(enable_gen())
@ -158,9 +158,9 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.rx_mii_select <= mii_sel
tb.dut.tx_mii_select <= mii_sel
tb.dut.ifg_delay.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator_rx(enable_gen())

28
fpga/lib/eth/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py
View File

@ -74,14 +74,14 @@ class TB:
self.dut.tx_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst <= 1
self.dut.rx_rst <= 1
self.dut.tx_rst <= 1
self.dut.logic_rst.value = 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst <= 0
self.dut.rx_rst <= 0
self.dut.tx_rst <= 0
self.dut.logic_rst.value = 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.logic_clk)
@ -113,12 +113,12 @@ class TB:
async def _run_enable_rx(self):
for val in self._enable_generator_rx:
self.dut.rx_clk_enable <= val
self.dut.rx_clk_enable.value = val
await RisingEdge(self.dut.rx_clk)
async def _run_enable_tx(self):
for val in self._enable_generator_tx:
self.dut.tx_clk_enable <= val
self.dut.tx_clk_enable.value = val
await RisingEdge(self.dut.tx_clk)
@ -127,9 +127,9 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.rx_mii_select <= mii_sel
tb.dut.tx_mii_select <= mii_sel
tb.dut.ifg_delay.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator_rx(enable_gen())
@ -160,9 +160,9 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.rx_mii_select <= mii_sel
tb.dut.tx_mii_select <= mii_sel
tb.dut.ifg_delay.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator_rx(enable_gen())

8
fpga/lib/eth/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py
View File

@ -59,10 +59,10 @@ class TB:
self.dut.gtx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.gtx_rst <= 1
self.dut.gtx_rst.value = 1
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.gtx_rst <= 0
self.dut.gtx_rst.value = 0
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
@ -75,7 +75,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
tb.set_speed(speed)
@ -114,7 +114,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
tb.set_speed(speed)

12
fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py
View File

@ -61,12 +61,12 @@ class TB:
self.dut.logic_rst.setimmediatevalue(0)
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.gtx_rst <= 1
self.dut.logic_rst <= 1
self.dut.gtx_rst.value = 1
self.dut.logic_rst.value = 1
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.gtx_rst <= 0
self.dut.logic_rst <= 0
self.dut.gtx_rst.value = 0
self.dut.logic_rst.value = 0
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
@ -79,7 +79,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
tb.set_speed(speed)
@ -118,7 +118,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
tb.set_speed(speed)

16
fpga/lib/eth/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py
View File

@ -61,23 +61,23 @@ class TB:
self.dut.gtx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst <= 1
self.dut.gtx_rst.value = 1
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst <= 0
self.dut.gtx_rst.value = 0
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
async def _run_gtx_clk(self):
t = Timer(2, 'ns')
while True:
self.dut.gtx_clk <= 1
self.dut.gtx_clk.value = 1
await t
self.dut.gtx_clk90 <= 1
self.dut.gtx_clk90.value = 1
await t
self.dut.gtx_clk <= 0
self.dut.gtx_clk.value = 0
await t
self.dut.gtx_clk90 <= 0
self.dut.gtx_clk90.value = 0
await t
@ -86,7 +86,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -123,7 +123,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()

20
fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py
View File

@ -65,25 +65,25 @@ class TB:
self.dut.logic_rst.setimmediatevalue(0)
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst <= 1
self.dut.logic_rst <= 1
self.dut.gtx_rst.value = 1
self.dut.logic_rst.value = 1
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst <= 0
self.dut.logic_rst <= 0
self.dut.gtx_rst.value = 0
self.dut.logic_rst.value = 0
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
async def _run_gtx_clk(self):
t = Timer(2, 'ns')
while True:
self.dut.gtx_clk <= 1
self.dut.gtx_clk.value = 1
await t
self.dut.gtx_clk90 <= 1
self.dut.gtx_clk90.value = 1
await t
self.dut.gtx_clk <= 0
self.dut.gtx_clk.value = 0
await t
self.dut.gtx_clk90 <= 0
self.dut.gtx_clk90.value = 0
await t
@ -92,7 +92,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -129,7 +129,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()

8
fpga/lib/eth/tb/eth_mac_mii/test_eth_mac_mii.py
View File

@ -56,10 +56,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
@ -69,7 +69,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -96,7 +96,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()

8
fpga/lib/eth/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py
View File

@ -59,10 +59,10 @@ class TB:
self.dut.logic_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst <= 1
self.dut.logic_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst <= 0
self.dut.logic_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.logic_clk)
@ -72,7 +72,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -99,7 +99,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()

14
fpga/lib/eth/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py
View File

@ -81,12 +81,12 @@ class TB:
self.dut.tx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.rx_clk)
await RisingEdge(self.dut.rx_clk)
self.dut.rx_rst <= 1
self.dut.tx_rst <= 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
await RisingEdge(self.dut.rx_clk)
await RisingEdge(self.dut.rx_clk)
self.dut.rx_rst <= 0
self.dut.tx_rst <= 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
await RisingEdge(self.dut.rx_clk)
await RisingEdge(self.dut.rx_clk)
@ -96,7 +96,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -130,7 +130,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -160,7 +160,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
for length in range(60, 92):

18
fpga/lib/eth/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py
View File

@ -85,14 +85,14 @@ class TB:
self.dut.tx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst <= 1
self.dut.rx_rst <= 1
self.dut.tx_rst <= 1
self.dut.logic_rst.value = 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst <= 0
self.dut.rx_rst <= 0
self.dut.tx_rst <= 0
self.dut.logic_rst.value = 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
@ -102,7 +102,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -136,7 +136,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
@ -166,7 +166,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay <= ifg
tb.dut.ifg_delay.value = ifg
for length in range(60, 92):

8
fpga/lib/eth/tb/eth_phy_10g/test_eth_phy_10g.py
View File

@ -72,12 +72,12 @@ class TB:
self.dut.rx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.tx_rst <= 1
self.dut.rx_rst <= 1
self.dut.tx_rst.value = 1
self.dut.rx_rst.value = 1
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.tx_rst <= 0
self.dut.rx_rst <= 0
self.dut.tx_rst.value = 0
self.dut.rx_rst.value = 0
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)

49
fpga/lib/eth/tb/ptp_clock/test_ptp_clock.py
View File

@ -66,10 +66,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -122,15 +122,15 @@ async def run_load_timestamps(dut):
await RisingEdge(dut.clk)
dut.input_ts_96 <= 12345678
dut.input_ts_96_valid <= 1
dut.input_ts_64 <= 12345678
dut.input_ts_64_valid <= 1
dut.input_ts_96.value = 12345678
dut.input_ts_96_valid.value = 1
dut.input_ts_64.value = 12345678
dut.input_ts_64_valid.value = 1
await RisingEdge(dut.clk)
dut.input_ts_96_valid <= 0
dut.input_ts_64_valid <= 0
dut.input_ts_96_valid.value = 0
dut.input_ts_64_valid.value = 0
await RisingEdge(dut.clk)
@ -138,6 +138,8 @@ async def run_load_timestamps(dut):
assert dut.output_ts_64.value.integer == 12345678
assert dut.output_ts_step.value.integer == 1
await RisingEdge(dut.clk)
start_time = get_sim_time('sec')
start_ts_96 = (dut.output_ts_96.value.integer >> 48) + ((dut.output_ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_64 = dut.output_ts_64.value.integer/2**16*1e-9
@ -178,16 +180,17 @@ async def run_seconds_increment(dut):
await RisingEdge(dut.clk)
dut.input_ts_96 <= 999990000*2**16
dut.input_ts_96_valid <= 1
dut.input_ts_64 <= 999990000*2**16
dut.input_ts_64_valid <= 1
dut.input_ts_96.value = 999990000*2**16
dut.input_ts_96_valid.value = 1
dut.input_ts_64.value = 999990000*2**16
dut.input_ts_64_valid.value = 1
await RisingEdge(dut.clk)
dut.input_ts_96_valid <= 0
dut.input_ts_64_valid <= 0
dut.input_ts_96_valid.value = 0
dut.input_ts_64_valid.value = 0
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
start_time = get_sim_time('sec')
@ -239,13 +242,13 @@ async def run_frequency_adjustment(dut):
await RisingEdge(dut.clk)
dut.input_period_ns <= 0x6
dut.input_period_fns <= 0x6624
dut.input_period_valid <= 1
dut.input_period_ns.value = 0x6
dut.input_period_fns.value = 0x6624
dut.input_period_valid.value = 1
await RisingEdge(dut.clk)
dut.input_period_valid <= 0
dut.input_period_valid.value = 0
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
@ -290,14 +293,14 @@ async def run_drift_adjustment(dut):
await tb.reset()
dut.input_drift_ns <= 0
dut.input_drift_fns <= 20
dut.input_drift_rate <= 5
dut.input_drift_valid <= 1
dut.input_drift_ns.value = 0
dut.input_drift_fns.value = 20
dut.input_drift_rate.value = 5
dut.input_drift_valid.value = 1
await RisingEdge(dut.clk)
dut.input_drift_valid <= 0
dut.input_drift_valid.value = 0
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

12
fpga/lib/eth/tb/ptp_clock_cdc/test_ptp_clock_cdc.py
View File

@ -73,12 +73,12 @@ class TB:
self.dut.output_rst.setimmediatevalue(0)
await RisingEdge(self.dut.input_clk)
await RisingEdge(self.dut.input_clk)
self.dut.input_rst <= 1
self.dut.output_rst <= 1
self.dut.input_rst.value = 1
self.dut.output_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.input_clk)
self.dut.input_rst <= 0
self.dut.output_rst <= 0
self.dut.input_rst.value = 0
self.dut.output_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.input_clk)
@ -94,9 +94,9 @@ class TB:
while True:
await t
self.dut.output_clk <= 1
self.dut.output_clk.value = 1
await t
self.dut.output_clk <= 0
self.dut.output_clk.value = 0
def get_input_ts_ns(self):
ts = self.dut.input_ts.value.integer

42
fpga/lib/eth/tb/ptp_perout/test_ptp_perout.py
View File

@ -64,10 +64,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -79,39 +79,39 @@ async def run_test(dut):
await tb.reset()
dut.enable <= 1
dut.enable.value = 1
await RisingEdge(dut.clk)
dut.input_start <= 100 << 16
dut.input_start_valid <= 1
dut.input_period <= 100 << 16
dut.input_period_valid <= 1
dut.input_width <= 50 << 16
dut.input_width_valid <= 1
dut.input_start.value = 100 << 16
dut.input_start_valid.value = 1
dut.input_period.value = 100 << 16
dut.input_period_valid.value = 1
dut.input_width.value = 50 << 16
dut.input_width_valid.value = 1
await RisingEdge(dut.clk)
dut.input_start_valid <= 0
dut.input_period_valid <= 0
dut.input_width_valid <= 0
dut.input_start_valid.value = 0
dut.input_period_valid.value = 0
dut.input_width_valid.value = 0
await Timer(10000, 'ns')
await RisingEdge(dut.clk)
dut.input_start <= 0 << 16
dut.input_start_valid <= 1
dut.input_period <= 100 << 16
dut.input_period_valid <= 1
dut.input_width <= 50 << 16
dut.input_width_valid <= 1
dut.input_start.value = 0 << 16
dut.input_start_valid.value = 1
dut.input_period.value = 100 << 16
dut.input_period_valid.value = 1
dut.input_width.value = 50 << 16
dut.input_width_valid.value = 1
await RisingEdge(dut.clk)
dut.input_start_valid <= 0
dut.input_period_valid <= 0
dut.input_width_valid <= 0
dut.input_start_valid.value = 0
dut.input_period_valid.value = 0
dut.input_width_valid.value = 0
await Timer(10000, 'ns')

4
fpga/lib/eth/tb/xgmii_baser_dec_64/test_xgmii_baser_dec_64.py
View File

@ -64,10 +64,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
fpga/lib/eth/tb/xgmii_baser_enc_64/test_xgmii_baser_enc_64.py
View File

@ -64,10 +64,10 @@ class TB:
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)