FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-02-06 08:38:23 +08:00
Code Issues Projects Releases Wiki Activity

Update parameter ordering

Browse Source
This commit is contained in:
Alex Forencich 2018-10-25 10:20:17 -07:00
parent 09a8fa51b6
commit cb9f2132a4
3 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rtl/axis_frame_join.v
View File

@ -31,8 +31,8 @@ THE SOFTWARE.
*/ */
module axis_frame_join # module axis_frame_join #
( (
parameter DATA_WIDTH = 8,
parameter S_COUNT = 4, parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter TAG_ENABLE = 1, parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16 parameter TAG_WIDTH = 16
) )

2
tb/test_axis_frame_join_4.py
View File

@ -44,8 +44,8 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench(): def bench():
# Parameters # Parameters
DATA_WIDTH = 8
S_COUNT = 4 S_COUNT = 4
DATA_WIDTH = 8
TAG_ENABLE = 1 TAG_ENABLE = 1
TAG_WIDTH = 16 TAG_WIDTH = 16

4
tb/test_axis_frame_join_4.v
View File

@ -32,8 +32,8 @@ THE SOFTWARE.
module test_axis_frame_join_4; module test_axis_frame_join_4;
// Parameters // Parameters
parameter DATA_WIDTH = 8;
parameter S_COUNT = 4; parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter TAG_ENABLE = 1; parameter TAG_ENABLE = 1;
parameter TAG_WIDTH = 16; parameter TAG_WIDTH = 16;
@ -85,8 +85,8 @@ initial begin
end end
axis_frame_join #( axis_frame_join #(
.DATA_WIDTH(DATA_WIDTH),
.S_COUNT(S_COUNT), .S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.TAG_ENABLE(TAG_ENABLE), .TAG_ENABLE(TAG_ENABLE),
.TAG_WIDTH(TAG_WIDTH) .TAG_WIDTH(TAG_WIDTH)
) )