fpga/mqnic/DK_DEV_AGF014EA: Merge 25G into 100G for DK-DEV-AGF014EA

Signed-off-by: Alex Forencich <alex@alexforencich.com>

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/config.tcl

@@ -53,6 +53,9 @@ dict set params BUILD_DATE  "32'd${build_date}"
 dict set params GIT_HASH  "32'h${git_hash}"
 dict set params RELEASE_INFO  [format "32'h%08x" $release_info]
 
+# Board configuration
+dict set params MAC_100G "1"
+
 # Structural configuration
 dict set params IF_COUNT "2"
 dict set params PORTS_PER_IF "1"

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/config.tcl

@@ -53,6 +53,9 @@ dict set params BUILD_DATE  "32'd${build_date}"
 dict set params GIT_HASH  "32'h${git_hash}"
 dict set params RELEASE_INFO  [format "32'h%08x" $release_info]
 
+# Board configuration
+dict set params MAC_100G "1"
+
 # Structural configuration
 dict set params IF_COUNT "2"
 dict set params PORTS_PER_IF "1"

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/config.tcl

@@ -53,6 +53,9 @@ dict set params BUILD_DATE  "32'd${build_date}"
 dict set params GIT_HASH  "32'h${git_hash}"
 dict set params RELEASE_INFO  [format "32'h%08x" $release_info]
 
+# Board configuration
+dict set params MAC_100G "1"
+
 # Structural configuration
 dict set params IF_COUNT "2"
 dict set params PORTS_PER_IF "1"

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/config.tcl

@@ -53,6 +53,9 @@ dict set params BUILD_DATE  "32'd${build_date}"
 dict set params GIT_HASH  "32'h${git_hash}"
 dict set params RELEASE_INFO  [format "32'h%08x" $release_info]
 
+# Board configuration
+dict set params MAC_100G "1"
+
 # Structural configuration
 dict set params IF_COUNT "2"
 dict set params PORTS_PER_IF "1"

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/config.tcl

@@ -53,6 +53,10 @@ dict set params BUILD_DATE  "32'd${build_date}"
 dict set params GIT_HASH  "32'h${git_hash}"
 dict set params RELEASE_INFO  [format "32'h%08x" $release_info]
 
+# Board configuration
+dict set params MAC_100G "0"
+dict set params MAC_RSFEC "0"
+
 # Structural configuration
 dict set params IF_COUNT "2"
 dict set params PORTS_PER_IF "1"
@@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
 dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
-dict set params MAC_RSFEC "0"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/config.tcl

@@ -53,6 +53,10 @@ dict set params BUILD_DATE  "32'd${build_date}"
 dict set params GIT_HASH  "32'h${git_hash}"
 dict set params RELEASE_INFO  [format "32'h%08x" $release_info]
 
+# Board configuration
+dict set params MAC_100G "0"
+dict set params MAC_RSFEC "0"
+
 # Structural configuration
 dict set params IF_COUNT "2"
 dict set params PORTS_PER_IF "1"
@@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
 dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
-dict set params MAC_RSFEC "0"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/config.tcl

@@ -53,6 +53,10 @@ dict set params BUILD_DATE  "32'd${build_date}"
 dict set params GIT_HASH  "32'h${git_hash}"
 dict set params RELEASE_INFO  [format "32'h%08x" $release_info]
 
+# Board configuration
+dict set params MAC_100G "0"
+dict set params MAC_RSFEC "1"
+
 # Structural configuration
 dict set params IF_COUNT "2"
 dict set params PORTS_PER_IF "1"
@@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
 dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
-dict set params MAC_RSFEC "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/config.tcl

@@ -53,6 +53,10 @@ dict set params BUILD_DATE  "32'd${build_date}"
 dict set params GIT_HASH  "32'h${git_hash}"
 dict set params RELEASE_INFO  [format "32'h%08x" $release_info]
 
+# Board configuration
+dict set params MAC_100G "0"
+dict set params MAC_RSFEC "1"
+
 # Structural configuration
 dict set params IF_COUNT "2"
 dict set params PORTS_PER_IF "1"
@@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
 dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
-dict set params MAC_RSFEC "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/eth_mac_dual_quad_wrapper.v

@@ -33,6 +33,7 @@ THE SOFTWARE.
  */
 module eth_mac_dual_quad_wrapper #
 (
+    parameter N_CH = 8,
     parameter PTP_TS_WIDTH = 96,
     parameter PTP_TAG_WIDTH = 8,
     parameter DATA_WIDTH = 64,
@@ -42,331 +43,56 @@ module eth_mac_dual_quad_wrapper #
     parameter MAC_RSFEC = 0
 )
 (
-    input  wire                      ctrl_clk,
+    input  wire                           ctrl_clk,
-    input  wire                      ctrl_rst,
+    input  wire                           ctrl_rst,
-
+
-    output wire [7:0]                tx_serial_data_p,
+    output wire [7:0]                     tx_serial_data_p,
-    output wire [7:0]                tx_serial_data_n,
+    output wire [7:0]                     tx_serial_data_n,
-    input  wire [7:0]                rx_serial_data_p,
+    input  wire [7:0]                     rx_serial_data_p,
-    input  wire [7:0]                rx_serial_data_n,
+    input  wire [7:0]                     rx_serial_data_n,
-    input  wire                      ref_clk,
+    input  wire                           ref_clk,
-    input  wire                      ptp_sample_clk,
+    input  wire                           ptp_sample_clk,
-
+
-    output wire                      mac_1_tx_clk,
+    output wire [N_CH-1:0]                mac_tx_clk,
-    output wire                      mac_1_tx_rst,
+    output wire [N_CH-1:0]                mac_tx_rst,
-
+
-    output wire                      mac_1_tx_ptp_clk,
+    output wire [N_CH-1:0]                mac_tx_ptp_clk,
-    output wire                      mac_1_tx_ptp_rst,
+    output wire [N_CH-1:0]                mac_tx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_1_tx_ptp_time,
+    input  wire [N_CH*PTP_TS_WIDTH-1:0]   mac_tx_ptp_time,
-
+
-    output wire [PTP_TS_WIDTH-1:0]   mac_1_tx_ptp_ts,
+    output wire [N_CH*PTP_TS_WIDTH-1:0]   mac_tx_ptp_ts,
-    output wire [PTP_TAG_WIDTH-1:0]  mac_1_tx_ptp_ts_tag,
+    output wire [N_CH*PTP_TAG_WIDTH-1:0]  mac_tx_ptp_ts_tag,
-    output wire                      mac_1_tx_ptp_ts_valid,
+    output wire [N_CH-1:0]                mac_tx_ptp_ts_valid,
-
+
-    input  wire [DATA_WIDTH-1:0]     mac_1_tx_axis_tdata,
+    input  wire [N_CH*DATA_WIDTH-1:0]     mac_tx_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]     mac_1_tx_axis_tkeep,
+    input  wire [N_CH*KEEP_WIDTH-1:0]     mac_tx_axis_tkeep,
-    input  wire                      mac_1_tx_axis_tvalid,
+    input  wire [N_CH-1:0]                mac_tx_axis_tvalid,
-    output wire                      mac_1_tx_axis_tready,
+    output wire [N_CH-1:0]                mac_tx_axis_tready,
-    input  wire                      mac_1_tx_axis_tlast,
+    input  wire [N_CH-1:0]                mac_tx_axis_tlast,
-    input  wire [TX_USER_WIDTH-1:0]  mac_1_tx_axis_tuser,
+    input  wire [N_CH*TX_USER_WIDTH-1:0]  mac_tx_axis_tuser,
-
+
-    output wire                      mac_1_tx_status,
+    output wire [N_CH*1-1:0]              mac_tx_status,
-    input  wire                      mac_1_tx_lfc_req,
+    input  wire [N_CH*1-1:0]              mac_tx_lfc_req,
-    input  wire [7:0]                mac_1_tx_pfc_req,
+    input  wire [N_CH*8-1:0]              mac_tx_pfc_req,
-
+
-    output wire                      mac_1_rx_clk,
+    output wire [N_CH-1:0]                mac_rx_clk,
-    output wire                      mac_1_rx_rst,
+    output wire [N_CH-1:0]                mac_rx_rst,
-
+
-    output wire                      mac_1_rx_ptp_clk,
+    output wire [N_CH-1:0]                mac_rx_ptp_clk,
-    output wire                      mac_1_rx_ptp_rst,
+    output wire [N_CH-1:0]                mac_rx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_1_rx_ptp_time,
+    input  wire [N_CH*PTP_TS_WIDTH-1:0]   mac_rx_ptp_time,
-
+
-    output wire [DATA_WIDTH-1:0]     mac_1_rx_axis_tdata,
+    output wire [N_CH*DATA_WIDTH-1:0]     mac_rx_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]     mac_1_rx_axis_tkeep,
+    output wire [N_CH*KEEP_WIDTH-1:0]     mac_rx_axis_tkeep,
-    output wire                      mac_1_rx_axis_tvalid,
+    output wire [N_CH-1:0]                mac_rx_axis_tvalid,
-    output wire                      mac_1_rx_axis_tlast,
+    output wire [N_CH-1:0]                mac_rx_axis_tlast,
-    output wire [RX_USER_WIDTH-1:0]  mac_1_rx_axis_tuser,
+    output wire [N_CH*RX_USER_WIDTH-1:0]  mac_rx_axis_tuser,
-
+
-    output wire                      mac_1_rx_status,
+    output wire [N_CH*1-1:0]              mac_rx_status,
-    output wire                      mac_1_rx_lfc_req,
+    output wire [N_CH*1-1:0]              mac_rx_lfc_req,
-    output wire [7:0]                mac_1_rx_pfc_req,
+    output wire [N_CH*8-1:0]              mac_rx_pfc_req
-
-    output wire                      mac_2_tx_clk,
-    output wire                      mac_2_tx_rst,
-
-    output wire                      mac_2_tx_ptp_clk,
-    output wire                      mac_2_tx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_2_tx_ptp_time,
-
-    output wire [PTP_TS_WIDTH-1:0]   mac_2_tx_ptp_ts,
-    output wire [PTP_TAG_WIDTH-1:0]  mac_2_tx_ptp_ts_tag,
-    output wire                      mac_2_tx_ptp_ts_valid,
-
-    input  wire [DATA_WIDTH-1:0]     mac_2_tx_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]     mac_2_tx_axis_tkeep,
-    input  wire                      mac_2_tx_axis_tvalid,
-    output wire                      mac_2_tx_axis_tready,
-    input  wire                      mac_2_tx_axis_tlast,
-    input  wire [TX_USER_WIDTH-1:0]  mac_2_tx_axis_tuser,
-
-    output wire                      mac_2_tx_status,
-    input  wire                      mac_2_tx_lfc_req,
-    input  wire [7:0]                mac_2_tx_pfc_req,
-
-    output wire                      mac_2_rx_clk,
-    output wire                      mac_2_rx_rst,
-
-    output wire                      mac_2_rx_ptp_clk,
-    output wire                      mac_2_rx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_2_rx_ptp_time,
-
-    output wire [DATA_WIDTH-1:0]     mac_2_rx_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]     mac_2_rx_axis_tkeep,
-    output wire                      mac_2_rx_axis_tvalid,
-    output wire                      mac_2_rx_axis_tlast,
-    output wire [RX_USER_WIDTH-1:0]  mac_2_rx_axis_tuser,
-
-    output wire                      mac_2_rx_status,
-    output wire                      mac_2_rx_lfc_req,
-    output wire [7:0]                mac_2_rx_pfc_req,
-
-    output wire                      mac_3_tx_clk,
-    output wire                      mac_3_tx_rst,
-
-    output wire                      mac_3_tx_ptp_clk,
-    output wire                      mac_3_tx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_3_tx_ptp_time,
-
-    output wire [PTP_TS_WIDTH-1:0]   mac_3_tx_ptp_ts,
-    output wire [PTP_TAG_WIDTH-1:0]  mac_3_tx_ptp_ts_tag,
-    output wire                      mac_3_tx_ptp_ts_valid,
-
-    input  wire [DATA_WIDTH-1:0]     mac_3_tx_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]     mac_3_tx_axis_tkeep,
-    input  wire                      mac_3_tx_axis_tvalid,
-    output wire                      mac_3_tx_axis_tready,
-    input  wire                      mac_3_tx_axis_tlast,
-    input  wire [TX_USER_WIDTH-1:0]  mac_3_tx_axis_tuser,
-
-    output wire                      mac_3_tx_status,
-    input  wire                      mac_3_tx_lfc_req,
-    input  wire [7:0]                mac_3_tx_pfc_req,
-
-    output wire                      mac_3_rx_clk,
-    output wire                      mac_3_rx_rst,
-
-    output wire                      mac_3_rx_ptp_clk,
-    output wire                      mac_3_rx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_3_rx_ptp_time,
-
-    output wire [DATA_WIDTH-1:0]     mac_3_rx_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]     mac_3_rx_axis_tkeep,
-    output wire                      mac_3_rx_axis_tvalid,
-    output wire                      mac_3_rx_axis_tlast,
-    output wire [RX_USER_WIDTH-1:0]  mac_3_rx_axis_tuser,
-
-    output wire                      mac_3_rx_status,
-    output wire                      mac_3_rx_lfc_req,
-    output wire [7:0]                mac_3_rx_pfc_req,
-
-    output wire                      mac_4_tx_clk,
-    output wire                      mac_4_tx_rst,
-
-    output wire                      mac_4_tx_ptp_clk,
-    output wire                      mac_4_tx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_4_tx_ptp_time,
-
-    output wire [PTP_TS_WIDTH-1:0]   mac_4_tx_ptp_ts,
-    output wire [PTP_TAG_WIDTH-1:0]  mac_4_tx_ptp_ts_tag,
-    output wire                      mac_4_tx_ptp_ts_valid,
-
-    input  wire [DATA_WIDTH-1:0]     mac_4_tx_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]     mac_4_tx_axis_tkeep,
-    input  wire                      mac_4_tx_axis_tvalid,
-    output wire                      mac_4_tx_axis_tready,
-    input  wire                      mac_4_tx_axis_tlast,
-    input  wire [TX_USER_WIDTH-1:0]  mac_4_tx_axis_tuser,
-
-    output wire                      mac_4_tx_status,
-    input  wire                      mac_4_tx_lfc_req,
-    input  wire [7:0]                mac_4_tx_pfc_req,
-
-    output wire                      mac_4_rx_clk,
-    output wire                      mac_4_rx_rst,
-
-    output wire                      mac_4_rx_ptp_clk,
-    output wire                      mac_4_rx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_4_rx_ptp_time,
-
-    output wire [DATA_WIDTH-1:0]     mac_4_rx_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]     mac_4_rx_axis_tkeep,
-    output wire                      mac_4_rx_axis_tvalid,
-    output wire                      mac_4_rx_axis_tlast,
-    output wire [RX_USER_WIDTH-1:0]  mac_4_rx_axis_tuser,
-
-    output wire                      mac_4_rx_status,
-    output wire                      mac_4_rx_lfc_req,
-    output wire [7:0]                mac_4_rx_pfc_req,
-
-    output wire                      mac_5_tx_clk,
-    output wire                      mac_5_tx_rst,
-
-    output wire                      mac_5_tx_ptp_clk,
-    output wire                      mac_5_tx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_5_tx_ptp_time,
-
-    output wire [PTP_TS_WIDTH-1:0]   mac_5_tx_ptp_ts,
-    output wire [PTP_TAG_WIDTH-1:0]  mac_5_tx_ptp_ts_tag,
-    output wire                      mac_5_tx_ptp_ts_valid,
-
-    input  wire [DATA_WIDTH-1:0]     mac_5_tx_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]     mac_5_tx_axis_tkeep,
-    input  wire                      mac_5_tx_axis_tvalid,
-    output wire                      mac_5_tx_axis_tready,
-    input  wire                      mac_5_tx_axis_tlast,
-    input  wire [TX_USER_WIDTH-1:0]  mac_5_tx_axis_tuser,
-
-    output wire                      mac_5_tx_status,
-    input  wire                      mac_5_tx_lfc_req,
-    input  wire [7:0]                mac_5_tx_pfc_req,
-
-    output wire                      mac_5_rx_clk,
-    output wire                      mac_5_rx_rst,
-
-    output wire                      mac_5_rx_ptp_clk,
-    output wire                      mac_5_rx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_5_rx_ptp_time,
-
-    output wire [DATA_WIDTH-1:0]     mac_5_rx_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]     mac_5_rx_axis_tkeep,
-    output wire                      mac_5_rx_axis_tvalid,
-    output wire                      mac_5_rx_axis_tlast,
-    output wire [RX_USER_WIDTH-1:0]  mac_5_rx_axis_tuser,
-
-    output wire                      mac_5_rx_status,
-    output wire                      mac_5_rx_lfc_req,
-    output wire [7:0]                mac_5_rx_pfc_req,
-
-    output wire                      mac_6_tx_clk,
-    output wire                      mac_6_tx_rst,
-
-    output wire                      mac_6_tx_ptp_clk,
-    output wire                      mac_6_tx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_6_tx_ptp_time,
-
-    output wire [PTP_TS_WIDTH-1:0]   mac_6_tx_ptp_ts,
-    output wire [PTP_TAG_WIDTH-1:0]  mac_6_tx_ptp_ts_tag,
-    output wire                      mac_6_tx_ptp_ts_valid,
-
-    input  wire [DATA_WIDTH-1:0]     mac_6_tx_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]     mac_6_tx_axis_tkeep,
-    input  wire                      mac_6_tx_axis_tvalid,
-    output wire                      mac_6_tx_axis_tready,
-    input  wire                      mac_6_tx_axis_tlast,
-    input  wire [TX_USER_WIDTH-1:0]  mac_6_tx_axis_tuser,
-
-    output wire                      mac_6_tx_status,
-    input  wire                      mac_6_tx_lfc_req,
-    input  wire [7:0]                mac_6_tx_pfc_req,
-
-    output wire                      mac_6_rx_clk,
-    output wire                      mac_6_rx_rst,
-
-    output wire                      mac_6_rx_ptp_clk,
-    output wire                      mac_6_rx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_6_rx_ptp_time,
-
-    output wire [DATA_WIDTH-1:0]     mac_6_rx_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]     mac_6_rx_axis_tkeep,
-    output wire                      mac_6_rx_axis_tvalid,
-    output wire                      mac_6_rx_axis_tlast,
-    output wire [RX_USER_WIDTH-1:0]  mac_6_rx_axis_tuser,
-
-    output wire                      mac_6_rx_status,
-    output wire                      mac_6_rx_lfc_req,
-    output wire [7:0]                mac_6_rx_pfc_req,
-
-    output wire                      mac_7_tx_clk,
-    output wire                      mac_7_tx_rst,
-
-    output wire                      mac_7_tx_ptp_clk,
-    output wire                      mac_7_tx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_7_tx_ptp_time,
-
-    output wire [PTP_TS_WIDTH-1:0]   mac_7_tx_ptp_ts,
-    output wire [PTP_TAG_WIDTH-1:0]  mac_7_tx_ptp_ts_tag,
-    output wire                      mac_7_tx_ptp_ts_valid,
-
-    input  wire [DATA_WIDTH-1:0]     mac_7_tx_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]     mac_7_tx_axis_tkeep,
-    input  wire                      mac_7_tx_axis_tvalid,
-    output wire                      mac_7_tx_axis_tready,
-    input  wire                      mac_7_tx_axis_tlast,
-    input  wire [TX_USER_WIDTH-1:0]  mac_7_tx_axis_tuser,
-
-    output wire                      mac_7_tx_status,
-    input  wire                      mac_7_tx_lfc_req,
-    input  wire [7:0]                mac_7_tx_pfc_req,
-
-    output wire                      mac_7_rx_clk,
-    output wire                      mac_7_rx_rst,
-
-    output wire                      mac_7_rx_ptp_clk,
-    output wire                      mac_7_rx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_7_rx_ptp_time,
-
-    output wire [DATA_WIDTH-1:0]     mac_7_rx_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]     mac_7_rx_axis_tkeep,
-    output wire                      mac_7_rx_axis_tvalid,
-    output wire                      mac_7_rx_axis_tlast,
-    output wire [RX_USER_WIDTH-1:0]  mac_7_rx_axis_tuser,
-
-    output wire                      mac_7_rx_status,
-    output wire                      mac_7_rx_lfc_req,
-    output wire [7:0]                mac_7_rx_pfc_req,
-
-    output wire                      mac_8_tx_clk,
-    output wire                      mac_8_tx_rst,
-
-    output wire                      mac_8_tx_ptp_clk,
-    output wire                      mac_8_tx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_8_tx_ptp_time,
-
-    output wire [PTP_TS_WIDTH-1:0]   mac_8_tx_ptp_ts,
-    output wire [PTP_TAG_WIDTH-1:0]  mac_8_tx_ptp_ts_tag,
-    output wire                      mac_8_tx_ptp_ts_valid,
-
-    input  wire [DATA_WIDTH-1:0]     mac_8_tx_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]     mac_8_tx_axis_tkeep,
-    input  wire                      mac_8_tx_axis_tvalid,
-    output wire                      mac_8_tx_axis_tready,
-    input  wire                      mac_8_tx_axis_tlast,
-    input  wire [TX_USER_WIDTH-1:0]  mac_8_tx_axis_tuser,
-
-    output wire                      mac_8_tx_status,
-    input  wire                      mac_8_tx_lfc_req,
-    input  wire [7:0]                mac_8_tx_pfc_req,
-
-    output wire                      mac_8_rx_clk,
-    output wire                      mac_8_rx_rst,
-
-    output wire                      mac_8_rx_ptp_clk,
-    output wire                      mac_8_rx_ptp_rst,
-    input  wire [PTP_TS_WIDTH-1:0]   mac_8_rx_ptp_time,
-
-    output wire [DATA_WIDTH-1:0]     mac_8_rx_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]     mac_8_rx_axis_tkeep,
-    output wire                      mac_8_rx_axis_tvalid,
-    output wire                      mac_8_rx_axis_tlast,
-    output wire [RX_USER_WIDTH-1:0]  mac_8_rx_axis_tuser,
-
-    output wire                      mac_8_rx_status,
-    output wire                      mac_8_rx_lfc_req,
-    output wire [7:0]                mac_8_rx_pfc_req
 );
 
-parameter N_CH = 8;
-
 wire [11:0]  mac_pll_clk_d64;
 wire [11:0]  mac_pll_clk_d66;
 wire [11:0]  mac_rec_clk_d64;
@@ -374,16 +100,6 @@ wire [11:0]  mac_rec_clk_d66;
 
 wire [N_CH-1:0]  mac_tx_pll_locked;
 
-wire [N_CH-1:0]  mac_rx_clk;
-wire [N_CH-1:0]  mac_rx_rst;
-wire [N_CH-1:0]  mac_tx_clk;
-wire [N_CH-1:0]  mac_tx_rst;
-
-wire [N_CH-1:0]  mac_rx_ptp_clk;
-wire [N_CH-1:0]  mac_rx_ptp_rst;
-wire [N_CH-1:0]  mac_tx_ptp_clk;
-wire [N_CH-1:0]  mac_tx_ptp_rst;
-
 wire [N_CH*19-1:0]  xcvr_reconfig_address;
 wire [N_CH-1:0]     xcvr_reconfig_read;
 wire [N_CH-1:0]     xcvr_reconfig_write;
@@ -857,19 +573,6 @@ end
 
 endgenerate
 
-wire [N_CH*DATA_WIDTH-1:0]     mac_rx_axis_tdata;
-wire [N_CH*KEEP_WIDTH-1:0]     mac_rx_axis_tkeep;
-wire [N_CH-1:0]                mac_rx_axis_tvalid;
-wire [N_CH-1:0]                mac_rx_axis_tlast;
-wire [N_CH*RX_USER_WIDTH-1:0]  mac_rx_axis_tuser;
-
-wire [N_CH*DATA_WIDTH-1:0]     mac_tx_axis_tdata;
-wire [N_CH*KEEP_WIDTH-1:0]     mac_tx_axis_tkeep;
-wire [N_CH-1:0]                mac_tx_axis_tvalid;
-wire [N_CH-1:0]                mac_tx_axis_tready;
-wire [N_CH-1:0]                mac_tx_axis_tlast;
-wire [N_CH*TX_USER_WIDTH-1:0]  mac_tx_axis_tuser;
-
 assign mac_tx_clk[3:0] = {4{mac_pll_clk_d64[4]}};
 assign mac_rx_clk[3:0] = mac_tx_clk[3:0];
 
@@ -882,317 +585,20 @@ assign mac_rx_clk[7:4] = mac_tx_clk[7:4];
 assign mac_tx_ptp_clk[7:4] = mac_pll_clk_d66[9:6];
 assign mac_rx_ptp_clk[7:4] = mac_rec_clk_d66[9:6];
 
-assign mac_1_tx_clk = mac_tx_clk[0];
+assign mac_ptp_tx_tod = mac_tx_ptp_time;
-assign mac_1_tx_rst = mac_tx_rst[0];
+assign mac_ptp_rx_tod = mac_rx_ptp_time;
 
-assign mac_1_tx_ptp_clk = mac_tx_ptp_clk[0];
+assign mac_tx_ptp_ts = mac_ptp_ets;
-assign mac_1_tx_ptp_rst = mac_tx_ptp_rst[0];
+assign mac_tx_ptp_ts_tag = mac_ptp_ets_fp;
-assign mac_ptp_tx_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_tx_ptp_time;
+assign mac_tx_ptp_ts_valid = mac_ptp_ets_valid;
 
-assign mac_1_tx_ptp_ts = mac_ptp_ets[0*PTP_TS_WIDTH +: PTP_TS_WIDTH];
+assign mac_tx_status = mac_tx_lanes_stable;
-assign mac_1_tx_ptp_ts_tag = mac_ptp_ets_fp[0*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
+assign mac_tx_pause = mac_tx_lfc_req;
-assign mac_1_tx_ptp_ts_valid = mac_ptp_ets_valid[0];
+assign mac_tx_pfc = mac_tx_pfc_req;
 
-assign mac_tx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH] = mac_1_tx_axis_tdata;
+assign mac_rx_status = mac_rx_pcs_ready;
-assign mac_tx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH] = mac_1_tx_axis_tkeep;
+assign mac_rx_lfc_req = mac_rx_pause;
-assign mac_tx_axis_tvalid[0] = mac_1_tx_axis_tvalid;
+assign mac_rx_pfc_req = mac_rx_pfc;
-assign mac_1_tx_axis_tready = mac_tx_axis_tready[0];
-assign mac_tx_axis_tlast[0] = mac_1_tx_axis_tlast;
-assign mac_tx_axis_tuser[0*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_1_tx_axis_tuser;
-
-assign mac_1_tx_status = mac_tx_lanes_stable[0*1 +: 1];
-assign mac_tx_pause[0*1 +: 1] = mac_1_tx_lfc_req;
-assign mac_tx_pfc[0*8 +: 8] = mac_1_tx_pfc_req;
-
-assign mac_1_rx_clk = mac_rx_clk[0];
-assign mac_1_rx_rst = mac_rx_rst[0];
-
-assign mac_1_rx_ptp_clk = mac_rx_ptp_clk[0];
-assign mac_1_rx_ptp_rst = mac_rx_ptp_rst[0];
-assign mac_ptp_rx_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_rx_ptp_time;
-
-assign mac_1_rx_axis_tdata = mac_rx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH];
-assign mac_1_rx_axis_tkeep = mac_rx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH];
-assign mac_1_rx_axis_tvalid = mac_rx_axis_tvalid[0];
-assign mac_1_rx_axis_tlast = mac_rx_axis_tlast[0];
-assign mac_1_rx_axis_tuser = mac_rx_axis_tuser[0*RX_USER_WIDTH +: RX_USER_WIDTH];
-
-assign mac_1_rx_status = mac_rx_pcs_ready[0*1 +: 1];
-assign mac_1_rx_lfc_req = mac_rx_pause[0*1 +: 1];
-assign mac_1_rx_pfc_req = mac_rx_pfc[0*8 +: 8];
-
-assign mac_2_tx_clk = mac_tx_clk[1];
-assign mac_2_tx_rst = mac_tx_rst[1];
-
-assign mac_2_tx_ptp_clk = mac_tx_ptp_clk[1];
-assign mac_2_tx_ptp_rst = mac_tx_ptp_rst[1];
-assign mac_ptp_tx_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_tx_ptp_time;
-
-assign mac_2_tx_ptp_ts = mac_ptp_ets[1*PTP_TS_WIDTH +: PTP_TS_WIDTH];
-assign mac_2_tx_ptp_ts_tag = mac_ptp_ets_fp[1*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
-assign mac_2_tx_ptp_ts_valid = mac_ptp_ets_valid[1];
-
-assign mac_tx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH] = mac_2_tx_axis_tdata;
-assign mac_tx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH] = mac_2_tx_axis_tkeep;
-assign mac_tx_axis_tvalid[1] = mac_2_tx_axis_tvalid;
-assign mac_2_tx_axis_tready = mac_tx_axis_tready[1];
-assign mac_tx_axis_tlast[1] = mac_2_tx_axis_tlast;
-assign mac_tx_axis_tuser[1*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_2_tx_axis_tuser;
-
-assign mac_2_tx_status = mac_tx_lanes_stable[1*1 +: 1];
-assign mac_tx_pause[1*1 +: 1] = mac_2_tx_lfc_req;
-assign mac_tx_pfc[1*8 +: 8] = mac_2_tx_pfc_req;
-
-assign mac_2_rx_clk = mac_rx_clk[1];
-assign mac_2_rx_rst = mac_rx_rst[1];
-
-assign mac_2_rx_ptp_clk = mac_rx_ptp_clk[1];
-assign mac_2_rx_ptp_rst = mac_rx_ptp_rst[1];
-assign mac_ptp_rx_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_rx_ptp_time;
-
-assign mac_2_rx_axis_tdata = mac_rx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH];
-assign mac_2_rx_axis_tkeep = mac_rx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH];
-assign mac_2_rx_axis_tvalid = mac_rx_axis_tvalid[1];
-assign mac_2_rx_axis_tlast = mac_rx_axis_tlast[1];
-assign mac_2_rx_axis_tuser = mac_rx_axis_tuser[1*RX_USER_WIDTH +: RX_USER_WIDTH];
-
-assign mac_2_rx_status = mac_rx_pcs_ready[1*1 +: 1];
-assign mac_2_rx_lfc_req = mac_rx_pause[1*1 +: 1];
-assign mac_2_rx_pfc_req = mac_rx_pfc[1*8 +: 8];
-
-assign mac_3_tx_clk = mac_tx_clk[2];
-assign mac_3_tx_rst = mac_tx_rst[2];
-
-assign mac_3_tx_ptp_clk = mac_tx_ptp_clk[2];
-assign mac_3_tx_ptp_rst = mac_tx_ptp_rst[2];
-assign mac_ptp_tx_tod[2*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_3_tx_ptp_time;
-
-assign mac_3_tx_ptp_ts = mac_ptp_ets[2*PTP_TS_WIDTH +: PTP_TS_WIDTH];
-assign mac_3_tx_ptp_ts_tag = mac_ptp_ets_fp[2*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
-assign mac_3_tx_ptp_ts_valid = mac_ptp_ets_valid[2];
-
-assign mac_tx_axis_tdata[2*DATA_WIDTH +: DATA_WIDTH] = mac_3_tx_axis_tdata;
-assign mac_tx_axis_tkeep[2*KEEP_WIDTH +: KEEP_WIDTH] = mac_3_tx_axis_tkeep;
-assign mac_tx_axis_tvalid[2] = mac_3_tx_axis_tvalid;
-assign mac_3_tx_axis_tready = mac_tx_axis_tready[2];
-assign mac_tx_axis_tlast[2] = mac_3_tx_axis_tlast;
-assign mac_tx_axis_tuser[2*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_3_tx_axis_tuser;
-
-assign mac_3_tx_status = mac_tx_lanes_stable[2*1 +: 1];
-assign mac_tx_pause[2*1 +: 1] = mac_3_tx_lfc_req;
-assign mac_tx_pfc[2*8 +: 8] = mac_3_tx_pfc_req;
-
-assign mac_3_rx_clk = mac_rx_clk[2];
-assign mac_3_rx_rst = mac_rx_rst[2];
-
-assign mac_3_rx_ptp_clk = mac_rx_ptp_clk[2];
-assign mac_3_rx_ptp_rst = mac_rx_ptp_rst[2];
-assign mac_ptp_rx_tod[2*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_3_rx_ptp_time;
-
-assign mac_3_rx_axis_tdata = mac_rx_axis_tdata[2*DATA_WIDTH +: DATA_WIDTH];
-assign mac_3_rx_axis_tkeep = mac_rx_axis_tkeep[2*KEEP_WIDTH +: KEEP_WIDTH];
-assign mac_3_rx_axis_tvalid = mac_rx_axis_tvalid[2];
-assign mac_3_rx_axis_tlast = mac_rx_axis_tlast[2];
-assign mac_3_rx_axis_tuser = mac_rx_axis_tuser[2*RX_USER_WIDTH +: RX_USER_WIDTH];
-
-assign mac_3_rx_status = mac_rx_pcs_ready[2*1 +: 1];
-assign mac_3_rx_lfc_req = mac_rx_pause[2*1 +: 1];
-assign mac_3_rx_pfc_req = mac_rx_pfc[2*8 +: 8];
-
-assign mac_4_tx_clk = mac_tx_clk[3];
-assign mac_4_tx_rst = mac_tx_rst[3];
-
-assign mac_4_tx_ptp_clk = mac_tx_ptp_clk[3];
-assign mac_4_tx_ptp_rst = mac_tx_ptp_rst[3];
-assign mac_ptp_tx_tod[3*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_4_tx_ptp_time;
-
-assign mac_4_tx_ptp_ts = mac_ptp_ets[3*PTP_TS_WIDTH +: PTP_TS_WIDTH];
-assign mac_4_tx_ptp_ts_tag = mac_ptp_ets_fp[3*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
-assign mac_4_tx_ptp_ts_valid = mac_ptp_ets_valid[3];
-
-assign mac_tx_axis_tdata[3*DATA_WIDTH +: DATA_WIDTH] = mac_4_tx_axis_tdata;
-assign mac_tx_axis_tkeep[3*KEEP_WIDTH +: KEEP_WIDTH] = mac_4_tx_axis_tkeep;
-assign mac_tx_axis_tvalid[3] = mac_4_tx_axis_tvalid;
-assign mac_4_tx_axis_tready = mac_tx_axis_tready[3];
-assign mac_tx_axis_tlast[3] = mac_4_tx_axis_tlast;
-assign mac_tx_axis_tuser[3*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_4_tx_axis_tuser;
-
-assign mac_4_tx_status = mac_tx_lanes_stable[3*1 +: 1];
-assign mac_tx_pause[3*1 +: 1] = mac_4_tx_lfc_req;
-assign mac_tx_pfc[3*8 +: 8] = mac_4_tx_pfc_req;
-
-assign mac_4_rx_clk = mac_rx_clk[3];
-assign mac_4_rx_rst = mac_rx_rst[3];
-
-assign mac_4_rx_ptp_clk = mac_rx_ptp_clk[3];
-assign mac_4_rx_ptp_rst = mac_rx_ptp_rst[3];
-assign mac_ptp_rx_tod[3*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_4_rx_ptp_time;
-
-assign mac_4_rx_axis_tdata = mac_rx_axis_tdata[3*DATA_WIDTH +: DATA_WIDTH];
-assign mac_4_rx_axis_tkeep = mac_rx_axis_tkeep[3*KEEP_WIDTH +: KEEP_WIDTH];
-assign mac_4_rx_axis_tvalid = mac_rx_axis_tvalid[3];
-assign mac_4_rx_axis_tlast = mac_rx_axis_tlast[3];
-assign mac_4_rx_axis_tuser = mac_rx_axis_tuser[3*RX_USER_WIDTH +: RX_USER_WIDTH];
-
-assign mac_4_rx_status = mac_rx_pcs_ready[3*1 +: 1];
-assign mac_4_rx_lfc_req = mac_rx_pause[3*1 +: 1];
-assign mac_4_rx_pfc_req = mac_rx_pfc[3*8 +: 8];
-
-assign mac_5_tx_clk = mac_tx_clk[4];
-assign mac_5_tx_rst = mac_tx_rst[4];
-
-assign mac_5_tx_ptp_clk = mac_tx_ptp_clk[4];
-assign mac_5_tx_ptp_rst = mac_tx_ptp_rst[4];
-assign mac_ptp_tx_tod[4*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_5_tx_ptp_time;
-
-assign mac_5_tx_ptp_ts = mac_ptp_ets[4*PTP_TS_WIDTH +: PTP_TS_WIDTH];
-assign mac_5_tx_ptp_ts_tag = mac_ptp_ets_fp[4*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
-assign mac_5_tx_ptp_ts_valid = mac_ptp_ets_valid[4];
-
-assign mac_tx_axis_tdata[4*DATA_WIDTH +: DATA_WIDTH] = mac_5_tx_axis_tdata;
-assign mac_tx_axis_tkeep[4*KEEP_WIDTH +: KEEP_WIDTH] = mac_5_tx_axis_tkeep;
-assign mac_tx_axis_tvalid[4] = mac_5_tx_axis_tvalid;
-assign mac_5_tx_axis_tready = mac_tx_axis_tready[4];
-assign mac_tx_axis_tlast[4] = mac_5_tx_axis_tlast;
-assign mac_tx_axis_tuser[4*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_5_tx_axis_tuser;
-
-assign mac_5_tx_status = mac_tx_lanes_stable[4*1 +: 1];
-assign mac_tx_pause[4*1 +: 1] = mac_5_tx_lfc_req;
-assign mac_tx_pfc[4*8 +: 8] = mac_5_tx_pfc_req;
-
-assign mac_5_rx_clk = mac_rx_clk[4];
-assign mac_5_rx_rst = mac_rx_rst[4];
-
-assign mac_5_rx_ptp_clk = mac_rx_ptp_clk[4];
-assign mac_5_rx_ptp_rst = mac_rx_ptp_rst[4];
-assign mac_ptp_rx_tod[4*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_5_rx_ptp_time;
-
-assign mac_5_rx_axis_tdata = mac_rx_axis_tdata[4*DATA_WIDTH +: DATA_WIDTH];
-assign mac_5_rx_axis_tkeep = mac_rx_axis_tkeep[4*KEEP_WIDTH +: KEEP_WIDTH];
-assign mac_5_rx_axis_tvalid = mac_rx_axis_tvalid[4];
-assign mac_5_rx_axis_tlast = mac_rx_axis_tlast[4];
-assign mac_5_rx_axis_tuser = mac_rx_axis_tuser[4*RX_USER_WIDTH +: RX_USER_WIDTH];
-
-assign mac_5_rx_status = mac_rx_pcs_ready[4*1 +: 1];
-assign mac_5_rx_lfc_req = mac_rx_pause[4*1 +: 1];
-assign mac_5_rx_pfc_req = mac_rx_pfc[4*8 +: 8];
-
-assign mac_6_tx_clk = mac_tx_clk[5];
-assign mac_6_tx_rst = mac_tx_rst[5];
-
-assign mac_6_tx_ptp_clk = mac_tx_ptp_clk[5];
-assign mac_6_tx_ptp_rst = mac_tx_ptp_rst[5];
-assign mac_ptp_tx_tod[5*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_6_tx_ptp_time;
-
-assign mac_6_tx_ptp_ts = mac_ptp_ets[5*PTP_TS_WIDTH +: PTP_TS_WIDTH];
-assign mac_6_tx_ptp_ts_tag = mac_ptp_ets_fp[5*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
-assign mac_6_tx_ptp_ts_valid = mac_ptp_ets_valid[5];
-
-assign mac_tx_axis_tdata[5*DATA_WIDTH +: DATA_WIDTH] = mac_6_tx_axis_tdata;
-assign mac_tx_axis_tkeep[5*KEEP_WIDTH +: KEEP_WIDTH] = mac_6_tx_axis_tkeep;
-assign mac_tx_axis_tvalid[5] = mac_6_tx_axis_tvalid;
-assign mac_6_tx_axis_tready = mac_tx_axis_tready[5];
-assign mac_tx_axis_tlast[5] = mac_6_tx_axis_tlast;
-assign mac_tx_axis_tuser[5*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_6_tx_axis_tuser;
-
-assign mac_6_tx_status = mac_tx_lanes_stable[5*1 +: 1];
-assign mac_tx_pause[5*1 +: 1] = mac_6_tx_lfc_req;
-assign mac_tx_pfc[5*8 +: 8] = mac_6_tx_pfc_req;
-
-assign mac_6_rx_clk = mac_rx_clk[5];
-assign mac_6_rx_rst = mac_rx_rst[5];
-
-assign mac_6_rx_ptp_clk = mac_rx_ptp_clk[5];
-assign mac_6_rx_ptp_rst = mac_rx_ptp_rst[5];
-assign mac_ptp_rx_tod[5*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_6_rx_ptp_time;
-
-assign mac_6_rx_axis_tdata = mac_rx_axis_tdata[5*DATA_WIDTH +: DATA_WIDTH];
-assign mac_6_rx_axis_tkeep = mac_rx_axis_tkeep[5*KEEP_WIDTH +: KEEP_WIDTH];
-assign mac_6_rx_axis_tvalid = mac_rx_axis_tvalid[5];
-assign mac_6_rx_axis_tlast = mac_rx_axis_tlast[5];
-assign mac_6_rx_axis_tuser = mac_rx_axis_tuser[5*RX_USER_WIDTH +: RX_USER_WIDTH];
-
-assign mac_6_rx_status = mac_rx_pcs_ready[5*1 +: 1];
-assign mac_6_rx_lfc_req = mac_rx_pause[5*1 +: 1];
-assign mac_6_rx_pfc_req = mac_rx_pfc[5*8 +: 8];
-
-assign mac_7_tx_clk = mac_tx_clk[6];
-assign mac_7_tx_rst = mac_tx_rst[6];
-
-assign mac_7_tx_ptp_clk = mac_tx_ptp_clk[6];
-assign mac_7_tx_ptp_rst = mac_tx_ptp_rst[6];
-assign mac_ptp_tx_tod[6*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_7_tx_ptp_time;
-
-assign mac_7_tx_ptp_ts = mac_ptp_ets[6*PTP_TS_WIDTH +: PTP_TS_WIDTH];
-assign mac_7_tx_ptp_ts_tag = mac_ptp_ets_fp[6*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
-assign mac_7_tx_ptp_ts_valid = mac_ptp_ets_valid[6];
-
-assign mac_tx_axis_tdata[6*DATA_WIDTH +: DATA_WIDTH] = mac_7_tx_axis_tdata;
-assign mac_tx_axis_tkeep[6*KEEP_WIDTH +: KEEP_WIDTH] = mac_7_tx_axis_tkeep;
-assign mac_tx_axis_tvalid[6] = mac_7_tx_axis_tvalid;
-assign mac_7_tx_axis_tready = mac_tx_axis_tready[6];
-assign mac_tx_axis_tlast[6] = mac_7_tx_axis_tlast;
-assign mac_tx_axis_tuser[6*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_7_tx_axis_tuser;
-
-assign mac_7_tx_status = mac_tx_lanes_stable[6*1 +: 1];
-assign mac_tx_pause[6*1 +: 1] = mac_7_tx_lfc_req;
-assign mac_tx_pfc[6*8 +: 8] = mac_7_tx_pfc_req;
-
-assign mac_7_rx_clk = mac_rx_clk[6];
-assign mac_7_rx_rst = mac_rx_rst[6];
-
-assign mac_7_rx_ptp_clk = mac_rx_ptp_clk[6];
-assign mac_7_rx_ptp_rst = mac_rx_ptp_rst[6];
-assign mac_ptp_rx_tod[6*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_7_rx_ptp_time;
-
-assign mac_7_rx_axis_tdata = mac_rx_axis_tdata[6*DATA_WIDTH +: DATA_WIDTH];
-assign mac_7_rx_axis_tkeep = mac_rx_axis_tkeep[6*KEEP_WIDTH +: KEEP_WIDTH];
-assign mac_7_rx_axis_tvalid = mac_rx_axis_tvalid[6];
-assign mac_7_rx_axis_tlast = mac_rx_axis_tlast[6];
-assign mac_7_rx_axis_tuser = mac_rx_axis_tuser[6*RX_USER_WIDTH +: RX_USER_WIDTH];
-
-assign mac_7_rx_status = mac_rx_pcs_ready[6*1 +: 1];
-assign mac_7_rx_lfc_req = mac_rx_pause[6*1 +: 1];
-assign mac_7_rx_pfc_req = mac_rx_pfc[6*8 +: 8];
-
-assign mac_8_tx_clk = mac_tx_clk[7];
-assign mac_8_tx_rst = mac_tx_rst[7];
-
-assign mac_8_tx_ptp_clk = mac_tx_ptp_clk[7];
-assign mac_8_tx_ptp_rst = mac_tx_ptp_rst[7];
-assign mac_ptp_tx_tod[7*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_8_tx_ptp_time;
-
-assign mac_8_tx_ptp_ts = mac_ptp_ets[7*PTP_TS_WIDTH +: PTP_TS_WIDTH];
-assign mac_8_tx_ptp_ts_tag = mac_ptp_ets_fp[7*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
-assign mac_8_tx_ptp_ts_valid = mac_ptp_ets_valid[7];
-
-assign mac_tx_axis_tdata[7*DATA_WIDTH +: DATA_WIDTH] = mac_8_tx_axis_tdata;
-assign mac_tx_axis_tkeep[7*KEEP_WIDTH +: KEEP_WIDTH] = mac_8_tx_axis_tkeep;
-assign mac_tx_axis_tvalid[7] = mac_8_tx_axis_tvalid;
-assign mac_8_tx_axis_tready = mac_tx_axis_tready[7];
-assign mac_tx_axis_tlast[7] = mac_8_tx_axis_tlast;
-assign mac_tx_axis_tuser[7*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_8_tx_axis_tuser;
-
-assign mac_8_tx_status = mac_tx_lanes_stable[7*1 +: 1];
-assign mac_tx_pause[7*1 +: 1] = mac_8_tx_lfc_req;
-assign mac_tx_pfc[7*8 +: 8] = mac_8_tx_pfc_req;
-
-assign mac_8_rx_clk = mac_rx_clk[7];
-assign mac_8_rx_rst = mac_rx_rst[7];
-
-assign mac_8_rx_ptp_clk = mac_rx_ptp_clk[7];
-assign mac_8_rx_ptp_rst = mac_rx_ptp_rst[7];
-assign mac_ptp_rx_tod[7*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_8_rx_ptp_time;
-
-assign mac_8_rx_axis_tdata = mac_rx_axis_tdata[7*DATA_WIDTH +: DATA_WIDTH];
-assign mac_8_rx_axis_tkeep = mac_rx_axis_tkeep[7*KEEP_WIDTH +: KEEP_WIDTH];
-assign mac_8_rx_axis_tvalid = mac_rx_axis_tvalid[7];
-assign mac_8_rx_axis_tlast = mac_rx_axis_tlast[7];
-assign mac_8_rx_axis_tuser = mac_rx_axis_tuser[7*RX_USER_WIDTH +: RX_USER_WIDTH];
-
-assign mac_8_rx_status = mac_rx_pcs_ready[7*1 +: 1];
-assign mac_8_rx_lfc_req = mac_rx_pause[7*1 +: 1];
-assign mac_8_rx_pfc_req = mac_rx_pfc[7*8 +: 8];
 
 generate
 

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v

@@ -24,6 +24,10 @@ module fpga #
     parameter GIT_HASH = 32'hdce357bf,
     parameter RELEASE_INFO = 32'h00000000,
 
+    // Board configuration
+    parameter MAC_100G = 1,
+    parameter MAC_RSFEC = 1,
+
     // Structural configuration
     parameter IF_COUNT = 2,
     parameter PORTS_PER_IF = 1,
@@ -445,7 +449,7 @@ pcie pcie_hip_inst (
 
 // QSFP-DD interfaces
 localparam QSFPDD_CNT = 2;
-localparam CH_CNT = QSFPDD_CNT*2;
+localparam CH_CNT = MAC_100G ? QSFPDD_CNT*2 : QSFPDD_CNT*8;
 
 wire [CH_CNT-1:0]                         qsfpdd_mac_tx_clk;
 wire [CH_CNT-1:0]                         qsfpdd_mac_tx_rst;
@@ -457,7 +461,10 @@ wire [CH_CNT-1:0]                         qsfpdd_mac_tx_axis_tready;
 wire [CH_CNT-1:0]                         qsfpdd_mac_tx_axis_tlast;
 wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0]  qsfpdd_mac_tx_axis_tuser;
 
+wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_clk;
+wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_rst;
 wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_tx_ptp_time;
+
 wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_tx_ptp_ts;
 wire [CH_CNT*TX_TAG_WIDTH-1:0]            qsfpdd_mac_tx_ptp_ts_tag;
 wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_ts_valid;
@@ -475,117 +482,269 @@ wire [CH_CNT-1:0]                         qsfpdd_mac_rx_axis_tvalid;
 wire [CH_CNT-1:0]                         qsfpdd_mac_rx_axis_tlast;
 wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0]  qsfpdd_mac_rx_axis_tuser;
 
+wire [CH_CNT-1:0]                         qsfpdd_mac_rx_ptp_clk;
+wire [CH_CNT-1:0]                         qsfpdd_mac_rx_ptp_rst;
 wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_rx_ptp_time;
 
 wire [CH_CNT-1:0]                         qsfpdd_mac_rx_status;
 wire [CH_CNT-1:0]                         qsfpdd_mac_rx_lfc_req;
 wire [CH_CNT*8-1:0]                       qsfpdd_mac_rx_pfc_req;
 
-// QSFP-DD 0
+generate
-assign qsfpdd_mac_rx_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2];
-assign qsfpdd_mac_rx_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2];
 
-eth_mac_dual_wrapper #(
+if (MAC_100G) begin
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
-    .PTP_TAG_WIDTH(PTP_TAG_WIDTH),
-    .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
-    .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
-    .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
-    .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH)
-)
-qsfpdd0_mac_inst (
-    .ctrl_clk(clk_100mhz),
-    .ctrl_rst(rst_100mhz),
 
-    .tx_serial_data_p({qsfpdd0_tx_p[7], qsfpdd0_tx_p[5], qsfpdd0_tx_p[6], qsfpdd0_tx_p[4], qsfpdd0_tx_p[3], qsfpdd0_tx_p[1], qsfpdd0_tx_p[2], qsfpdd0_tx_p[0]}),
+    // QSFP-DD 0
-    // .tx_serial_data_n({qsfpdd0_tx_n[7], qsfpdd0_tx_n[5], qsfpdd0_tx_n[6], qsfpdd0_tx_n[4], qsfpdd0_tx_n[3], qsfpdd0_tx_n[1], qsfpdd0_tx_n[2], qsfpdd0_tx_n[0]}),
+    assign qsfpdd_mac_tx_ptp_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2];
-    .rx_serial_data_p({qsfpdd0_rx_p[7], qsfpdd0_rx_p[5], qsfpdd0_rx_p[6], qsfpdd0_rx_p[4], qsfpdd0_rx_p[3], qsfpdd0_rx_p[1], qsfpdd0_rx_p[2], qsfpdd0_rx_p[0]}),
+    assign qsfpdd_mac_tx_ptp_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2];
-    // .rx_serial_data_n({qsfpdd0_rx_n[7], qsfpdd0_rx_n[5], qsfpdd0_rx_n[6], qsfpdd0_rx_n[4], qsfpdd0_rx_n[3], qsfpdd0_rx_n[1], qsfpdd0_rx_n[2], qsfpdd0_rx_n[0]}),
+    assign qsfpdd_mac_rx_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2];
-    .ref_clk(refclk_156m_qsfpdd_p),
+    assign qsfpdd_mac_rx_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2];
+    assign qsfpdd_mac_rx_ptp_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2];
+    assign qsfpdd_mac_rx_ptp_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2];
 
-    .mac_clk(qsfpdd_mac_tx_clk[0*2 +: 2*1]),
+    eth_mac_dual_wrapper #(
-    .mac_rst(qsfpdd_mac_tx_rst[0*2 +: 2*1]),
+        .PTP_TS_WIDTH(PTP_TS_WIDTH),
+        .PTP_TAG_WIDTH(PTP_TAG_WIDTH),
+        .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
+        .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
+        .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
+        .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH)
+    )
+    qsfpdd0_mac_inst (
+        .ctrl_clk(clk_100mhz),
+        .ctrl_rst(rst_100mhz),
 
-    .mac_ptp_time(qsfpdd_mac_tx_ptp_time[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
+        .tx_serial_data_p({qsfpdd0_tx_p[7], qsfpdd0_tx_p[5], qsfpdd0_tx_p[6], qsfpdd0_tx_p[4], qsfpdd0_tx_p[3], qsfpdd0_tx_p[1], qsfpdd0_tx_p[2], qsfpdd0_tx_p[0]}),
+        // .tx_serial_data_n({qsfpdd0_tx_n[7], qsfpdd0_tx_n[5], qsfpdd0_tx_n[6], qsfpdd0_tx_n[4], qsfpdd0_tx_n[3], qsfpdd0_tx_n[1], qsfpdd0_tx_n[2], qsfpdd0_tx_n[0]}),
+        .rx_serial_data_p({qsfpdd0_rx_p[7], qsfpdd0_rx_p[5], qsfpdd0_rx_p[6], qsfpdd0_rx_p[4], qsfpdd0_rx_p[3], qsfpdd0_rx_p[1], qsfpdd0_rx_p[2], qsfpdd0_rx_p[0]}),
+        // .rx_serial_data_n({qsfpdd0_rx_n[7], qsfpdd0_rx_n[5], qsfpdd0_rx_n[6], qsfpdd0_rx_n[4], qsfpdd0_rx_n[3], qsfpdd0_rx_n[1], qsfpdd0_rx_n[2], qsfpdd0_rx_n[0]}),
+        .ref_clk(refclk_156m_qsfpdd_p),
 
-    .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
+        .mac_clk(qsfpdd_mac_tx_clk[0*2 +: 2*1]),
-    .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[0*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]),
+        .mac_rst(qsfpdd_mac_tx_rst[0*2 +: 2*1]),
-    .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[0*2 +: 2*1]),
 
-    .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
+        .mac_ptp_time(qsfpdd_mac_tx_ptp_time[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
-    .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
-    .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[0*2 +: 2*1]),
-    .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[0*2 +: 2*1]),
-    .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[0*2 +: 2*1]),
-    .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[0*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]),
 
-    .mac_tx_status(qsfpdd_mac_tx_status[0*2 +: 2*1]),
+        .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
-    .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[0*2 +: 2*1]),
+        .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[0*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]),
-    .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[0*2*8 +: 2*8]),
+        .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[0*2 +: 2*1]),
 
-    .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
+        .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
-    .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
+        .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
-    .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[0*2 +: 2*1]),
+        .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[0*2 +: 2*1]),
-    .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[0*2 +: 2*1]),
+        .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[0*2 +: 2*1]),
-    .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[0*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]),
+        .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[0*2 +: 2*1]),
+        .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[0*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]),
 
-    .mac_rx_status(qsfpdd_mac_rx_status[0*2 +: 2*1]),
+        .mac_tx_status(qsfpdd_mac_tx_status[0*2 +: 2*1]),
-    .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[0*2 +: 2*1]),
+        .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[0*2 +: 2*1]),
-    .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[0*2*8 +: 2*8])
+        .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[0*2*8 +: 2*8]),
-);
 
-// QSFP-DD 1
+        .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
-assign qsfpdd_mac_rx_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2];
+        .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
-assign qsfpdd_mac_rx_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2];
+        .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[0*2 +: 2*1]),
+        .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[0*2 +: 2*1]),
+        .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[0*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]),
 
-eth_mac_dual_wrapper #(
+        .mac_rx_status(qsfpdd_mac_rx_status[0*2 +: 2*1]),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
+        .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[0*2 +: 2*1]),
-    .PTP_TAG_WIDTH(PTP_TAG_WIDTH),
+        .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[0*2*8 +: 2*8])
-    .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
+    );
-    .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
-    .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
-    .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH)
-)
-qsfpdd1_mac_inst (
-    .ctrl_clk(clk_100mhz),
-    .ctrl_rst(rst_100mhz),
 
-    .tx_serial_data_p({qsfpdd1_tx_p[7], qsfpdd1_tx_p[5], qsfpdd1_tx_p[6], qsfpdd1_tx_p[4], qsfpdd1_tx_p[3], qsfpdd1_tx_p[1], qsfpdd1_tx_p[2], qsfpdd1_tx_p[0]}),
+    // QSFP-DD 1
-    // .tx_serial_data_n({qsfpdd1_tx_n[7], qsfpdd1_tx_n[5], qsfpdd1_tx_n[6], qsfpdd1_tx_n[4], qsfpdd1_tx_n[3], qsfpdd1_tx_n[1], qsfpdd1_tx_n[2], qsfpdd1_tx_n[0]}),
+    assign qsfpdd_mac_tx_ptp_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2];
-    .rx_serial_data_p({qsfpdd1_rx_p[7], qsfpdd1_rx_p[5], qsfpdd1_rx_p[6], qsfpdd1_rx_p[4], qsfpdd1_rx_p[3], qsfpdd1_rx_p[1], qsfpdd1_rx_p[2], qsfpdd1_rx_p[0]}),
+    assign qsfpdd_mac_tx_ptp_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2];
-    // .rx_serial_data_n({qsfpdd1_rx_n[7], qsfpdd1_rx_n[5], qsfpdd1_rx_n[6], qsfpdd1_rx_n[4], qsfpdd1_rx_n[3], qsfpdd1_rx_n[1], qsfpdd1_rx_n[2], qsfpdd1_rx_n[0]}),
+    assign qsfpdd_mac_rx_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2];
-    .ref_clk(refclk_156m_qsfpdd_p),
+    assign qsfpdd_mac_rx_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2];
+    assign qsfpdd_mac_rx_ptp_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2];
+    assign qsfpdd_mac_rx_ptp_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2];
 
-    .mac_clk(qsfpdd_mac_tx_clk[1*2 +: 2*1]),
+    eth_mac_dual_wrapper #(
-    .mac_rst(qsfpdd_mac_tx_rst[1*2 +: 2*1]),
+        .PTP_TS_WIDTH(PTP_TS_WIDTH),
+        .PTP_TAG_WIDTH(PTP_TAG_WIDTH),
+        .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
+        .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
+        .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
+        .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH)
+    )
+    qsfpdd1_mac_inst (
+        .ctrl_clk(clk_100mhz),
+        .ctrl_rst(rst_100mhz),
 
-    .mac_ptp_time(qsfpdd_mac_tx_ptp_time[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
+        .tx_serial_data_p({qsfpdd1_tx_p[7], qsfpdd1_tx_p[5], qsfpdd1_tx_p[6], qsfpdd1_tx_p[4], qsfpdd1_tx_p[3], qsfpdd1_tx_p[1], qsfpdd1_tx_p[2], qsfpdd1_tx_p[0]}),
+        // .tx_serial_data_n({qsfpdd1_tx_n[7], qsfpdd1_tx_n[5], qsfpdd1_tx_n[6], qsfpdd1_tx_n[4], qsfpdd1_tx_n[3], qsfpdd1_tx_n[1], qsfpdd1_tx_n[2], qsfpdd1_tx_n[0]}),
+        .rx_serial_data_p({qsfpdd1_rx_p[7], qsfpdd1_rx_p[5], qsfpdd1_rx_p[6], qsfpdd1_rx_p[4], qsfpdd1_rx_p[3], qsfpdd1_rx_p[1], qsfpdd1_rx_p[2], qsfpdd1_rx_p[0]}),
+        // .rx_serial_data_n({qsfpdd1_rx_n[7], qsfpdd1_rx_n[5], qsfpdd1_rx_n[6], qsfpdd1_rx_n[4], qsfpdd1_rx_n[3], qsfpdd1_rx_n[1], qsfpdd1_rx_n[2], qsfpdd1_rx_n[0]}),
+        .ref_clk(refclk_156m_qsfpdd_p),
 
-    .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
+        .mac_clk(qsfpdd_mac_tx_clk[1*2 +: 2*1]),
-    .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[1*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]),
+        .mac_rst(qsfpdd_mac_tx_rst[1*2 +: 2*1]),
-    .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[1*2 +: 2*1]),
 
-    .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
+        .mac_ptp_time(qsfpdd_mac_tx_ptp_time[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
-    .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
-    .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[1*2 +: 2*1]),
-    .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[1*2 +: 2*1]),
-    .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[1*2 +: 2*1]),
-    .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[1*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]),
 
-    .mac_tx_status(qsfpdd_mac_tx_status[1*2 +: 2*1]),
+        .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
-    .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[1*2 +: 2*1]),
+        .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[1*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]),
-    .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[1*2*8 +: 2*8]),
+        .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[1*2 +: 2*1]),
 
-    .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
+        .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
-    .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
+        .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
-    .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[1*2 +: 2*1]),
+        .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[1*2 +: 2*1]),
-    .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[1*2 +: 2*1]),
+        .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[1*2 +: 2*1]),
-    .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[1*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]),
+        .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[1*2 +: 2*1]),
+        .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[1*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]),
 
-    .mac_rx_status(qsfpdd_mac_rx_status[1*2 +: 2*1]),
+        .mac_tx_status(qsfpdd_mac_tx_status[1*2 +: 2*1]),
-    .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[1*2 +: 2*1]),
+        .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[1*2 +: 2*1]),
-    .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[1*2*8 +: 2*8])
+        .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[1*2*8 +: 2*8]),
-);
+
+        .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
+        .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
+        .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[1*2 +: 2*1]),
+        .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[1*2 +: 2*1]),
+        .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[1*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]),
+
+        .mac_rx_status(qsfpdd_mac_rx_status[1*2 +: 2*1]),
+        .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[1*2 +: 2*1]),
+        .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[1*2*8 +: 2*8])
+    );
+
+end else begin
+
+    wire etile_iopll_locked;
+    wire etile_ptp_sample_clk;
+
+    iopll_etile_ptp iopll_etile_ptp_inst (
+        .rst      (rst_100mhz),
+        .refclk   (clk_100mhz),
+        .locked   (etile_iopll_locked),
+        .outclk_0 (etile_ptp_sample_clk)
+    );
+
+    // QSFP-DD 0
+    eth_mac_dual_quad_wrapper #(
+        .PTP_TS_WIDTH(PTP_TS_WIDTH),
+        .PTP_TAG_WIDTH(PTP_TAG_WIDTH),
+        .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
+        .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
+        .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
+        .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
+        .MAC_RSFEC(MAC_RSFEC)
+    )
+    qsfpdd0_mac_inst (
+        .ctrl_clk(clk_100mhz),
+        .ctrl_rst(rst_100mhz),
+
+        .tx_serial_data_p({qsfpdd0_tx_p[7], qsfpdd0_tx_p[5], qsfpdd0_tx_p[6], qsfpdd0_tx_p[4], qsfpdd0_tx_p[3], qsfpdd0_tx_p[1], qsfpdd0_tx_p[2], qsfpdd0_tx_p[0]}),
+        // .tx_serial_data_n({qsfpdd0_tx_n[7], qsfpdd0_tx_n[5], qsfpdd0_tx_n[6], qsfpdd0_tx_n[4], qsfpdd0_tx_n[3], qsfpdd0_tx_n[1], qsfpdd0_tx_n[2], qsfpdd0_tx_n[0]}),
+        .rx_serial_data_p({qsfpdd0_rx_p[7], qsfpdd0_rx_p[5], qsfpdd0_rx_p[6], qsfpdd0_rx_p[4], qsfpdd0_rx_p[3], qsfpdd0_rx_p[1], qsfpdd0_rx_p[2], qsfpdd0_rx_p[0]}),
+        // .rx_serial_data_n({qsfpdd0_rx_n[7], qsfpdd0_rx_n[5], qsfpdd0_rx_n[6], qsfpdd0_rx_n[4], qsfpdd0_rx_n[3], qsfpdd0_rx_n[1], qsfpdd0_rx_n[2], qsfpdd0_rx_n[0]}),
+        .ref_clk(refclk_156m_qsfpdd_p),
+        .ptp_sample_clk(etile_ptp_sample_clk),
+
+        .mac_tx_clk(qsfpdd_mac_tx_clk[0*8 +: 8*1]),
+        .mac_tx_rst(qsfpdd_mac_tx_rst[0*8 +: 8*1]),
+
+        .mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk[0*8 +: 8*1]),
+        .mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst[0*8 +: 8*1]),
+        .mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time[0*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]),
+
+        .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[0*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]),
+        .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[0*8*TX_TAG_WIDTH +: 8*TX_TAG_WIDTH]),
+        .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[0*8 +: 8*1]),
+
+        .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[0*8*AXIS_ETH_DATA_WIDTH +: 8*AXIS_ETH_DATA_WIDTH]),
+        .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[0*8*AXIS_ETH_KEEP_WIDTH +: 8*AXIS_ETH_KEEP_WIDTH]),
+        .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[0*8 +: 8*1]),
+        .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[0*8 +: 8*1]),
+        .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[0*8 +: 8*1]),
+        .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[0*8*AXIS_ETH_TX_USER_WIDTH +: 8*AXIS_ETH_TX_USER_WIDTH]),
+
+        .mac_tx_status(qsfpdd_mac_tx_status[0*8 +: 8*1]),
+        .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[0*8 +: 8*1]),
+        .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[0*8*8 +: 8*8]),
+
+        .mac_rx_clk(qsfpdd_mac_rx_clk[0*8 +: 8*1]),
+        .mac_rx_rst(qsfpdd_mac_rx_rst[0*8 +: 8*1]),
+
+        .mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk[0*8 +: 8*1]),
+        .mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst[0*8 +: 8*1]),
+        .mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time[0*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]),
+
+        .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[0*8*AXIS_ETH_DATA_WIDTH +: 8*AXIS_ETH_DATA_WIDTH]),
+        .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[0*8*AXIS_ETH_KEEP_WIDTH +: 8*AXIS_ETH_KEEP_WIDTH]),
+        .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[0*8 +: 8*1]),
+        .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[0*8 +: 8*1]),
+        .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[0*8*AXIS_ETH_RX_USER_WIDTH +: 8*AXIS_ETH_RX_USER_WIDTH]),
+
+        .mac_rx_status(qsfpdd_mac_rx_status[0*8 +: 8*1]),
+        .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[0*8 +: 8*1]),
+        .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[0*8*8 +: 8*8])
+    );
+
+    // QSFP-DD 1
+    eth_mac_dual_quad_wrapper #(
+        .PTP_TS_WIDTH(PTP_TS_WIDTH),
+        .PTP_TAG_WIDTH(PTP_TAG_WIDTH),
+        .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
+        .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
+        .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
+        .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
+        .MAC_RSFEC(MAC_RSFEC)
+    )
+    qsfpdd1_mac_inst (
+        .ctrl_clk(clk_100mhz),
+        .ctrl_rst(rst_100mhz),
+
+        .tx_serial_data_p({qsfpdd1_tx_p[7], qsfpdd1_tx_p[5], qsfpdd1_tx_p[6], qsfpdd1_tx_p[4], qsfpdd1_tx_p[3], qsfpdd1_tx_p[1], qsfpdd1_tx_p[2], qsfpdd1_tx_p[0]}),
+        // .tx_serial_data_n({qsfpdd1_tx_n[7], qsfpdd1_tx_n[5], qsfpdd1_tx_n[6], qsfpdd1_tx_n[4], qsfpdd1_tx_n[3], qsfpdd1_tx_n[1], qsfpdd1_tx_n[2], qsfpdd1_tx_n[0]}),
+        .rx_serial_data_p({qsfpdd1_rx_p[7], qsfpdd1_rx_p[5], qsfpdd1_rx_p[6], qsfpdd1_rx_p[4], qsfpdd1_rx_p[3], qsfpdd1_rx_p[1], qsfpdd1_rx_p[2], qsfpdd1_rx_p[0]}),
+        // .rx_serial_data_n({qsfpdd1_rx_n[7], qsfpdd1_rx_n[5], qsfpdd1_rx_n[6], qsfpdd1_rx_n[4], qsfpdd1_rx_n[3], qsfpdd1_rx_n[1], qsfpdd1_rx_n[2], qsfpdd1_rx_n[0]}),
+        .ref_clk(refclk_156m_qsfpdd_p),
+        .ptp_sample_clk(etile_ptp_sample_clk),
+
+        .mac_tx_clk(qsfpdd_mac_tx_clk[1*8 +: 8*1]),
+        .mac_tx_rst(qsfpdd_mac_tx_rst[1*8 +: 8*1]),
+
+        .mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk[1*8 +: 8*1]),
+        .mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst[1*8 +: 8*1]),
+        .mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time[1*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]),
+
+        .mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[1*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]),
+        .mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[1*8*TX_TAG_WIDTH +: 8*TX_TAG_WIDTH]),
+        .mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[1*8 +: 8*1]),
+
+        .mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[1*8*AXIS_ETH_DATA_WIDTH +: 8*AXIS_ETH_DATA_WIDTH]),
+        .mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[1*8*AXIS_ETH_KEEP_WIDTH +: 8*AXIS_ETH_KEEP_WIDTH]),
+        .mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[1*8 +: 8*1]),
+        .mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[1*8 +: 8*1]),
+        .mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[1*8 +: 8*1]),
+        .mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[1*8*AXIS_ETH_TX_USER_WIDTH +: 8*AXIS_ETH_TX_USER_WIDTH]),
+
+        .mac_tx_status(qsfpdd_mac_tx_status[1*8 +: 8*1]),
+        .mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[1*8 +: 8*1]),
+        .mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[1*8*8 +: 8*8]),
+
+        .mac_rx_clk(qsfpdd_mac_rx_clk[1*8 +: 8*1]),
+        .mac_rx_rst(qsfpdd_mac_rx_rst[1*8 +: 8*1]),
+
+        .mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk[1*8 +: 8*1]),
+        .mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst[1*8 +: 8*1]),
+        .mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time[1*8*PTP_TS_WIDTH +: 8*PTP_TS_WIDTH]),
+
+        .mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[1*8*AXIS_ETH_DATA_WIDTH +: 8*AXIS_ETH_DATA_WIDTH]),
+        .mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[1*8*AXIS_ETH_KEEP_WIDTH +: 8*AXIS_ETH_KEEP_WIDTH]),
+        .mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[1*8 +: 8*1]),
+        .mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[1*8 +: 8*1]),
+        .mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[1*8*AXIS_ETH_RX_USER_WIDTH +: 8*AXIS_ETH_RX_USER_WIDTH]),
+
+        .mac_rx_status(qsfpdd_mac_rx_status[1*8 +: 8*1]),
+        .mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[1*8 +: 8*1]),
+        .mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[1*8*8 +: 8*8])
+    );
+
+end
+
+endgenerate
 
 wire ptp_clk;
 wire ptp_rst;
@@ -627,6 +786,8 @@ fpga_core #(
     .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
+    .PTP_SEPARATE_TX_CLOCK(MAC_100G ? 0 : 1),
+    .PTP_SEPARATE_RX_CLOCK(MAC_100G ? 0 : 1),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v

@@ -27,6 +27,7 @@ module fpga_core #
     // Board configuration
     parameter QSFPDD_CNT = 2,
     parameter CH_CNT = QSFPDD_CNT*2,
+    parameter PORT_GROUP_SIZE = 2,
 
     // Structural configuration
     parameter IF_COUNT = 2,
@@ -44,6 +45,8 @@ module fpga_core #
     parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
+    parameter PTP_SEPARATE_TX_CLOCK = 0,
+    parameter PTP_SEPARATE_RX_CLOCK = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 1,
     parameter PTP_PEROUT_COUNT = 1,
@@ -232,7 +235,10 @@ module fpga_core #
     output wire [CH_CNT-1:0]                         qsfpdd_mac_tx_axis_tlast,
     output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0]  qsfpdd_mac_tx_axis_tuser,
 
+    input  wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_clk,
+    input  wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_rst,
     output wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_tx_ptp_time,
+
     input  wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_tx_ptp_ts,
     input  wire [CH_CNT*TX_TAG_WIDTH-1:0]            qsfpdd_mac_tx_ptp_ts_tag,
     input  wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_ts_valid,
@@ -250,6 +256,8 @@ module fpga_core #
     input  wire [CH_CNT-1:0]                         qsfpdd_mac_rx_axis_tlast,
     input  wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0]  qsfpdd_mac_rx_axis_tuser,
 
+    input  wire [CH_CNT-1:0]                         qsfpdd_mac_rx_ptp_clk,
+    input  wire [CH_CNT-1:0]                         qsfpdd_mac_rx_ptp_rst,
     output wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_rx_ptp_time,
 
     input  wire [CH_CNT-1:0]                         qsfpdd_mac_rx_status,
@@ -590,7 +598,7 @@ wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_ack;
 mqnic_port_map_mac_axis #(
     .MAC_COUNT(CH_CNT),
     .PORT_MASK(PORT_MASK),
-    .PORT_GROUP_SIZE(2),
+    .PORT_GROUP_SIZE(PORT_GROUP_SIZE),
 
     .IF_COUNT(IF_COUNT),
     .PORTS_PER_IF(PORTS_PER_IF),
@@ -609,8 +617,8 @@ mqnic_port_map_mac_axis_inst (
     .mac_tx_clk(qsfpdd_mac_tx_clk),
     .mac_tx_rst(qsfpdd_mac_tx_rst),
 
-    .mac_tx_ptp_clk(qsfpdd_mac_tx_clk),
+    .mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk),
-    .mac_tx_ptp_rst(qsfpdd_mac_tx_rst),
+    .mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst),
     .mac_tx_ptp_ts_96(qsfpdd_mac_tx_ptp_time),
     .mac_tx_ptp_ts_step(),
 
@@ -636,8 +644,8 @@ mqnic_port_map_mac_axis_inst (
     .mac_rx_clk(qsfpdd_mac_rx_clk),
     .mac_rx_rst(qsfpdd_mac_rx_rst),
 
-    .mac_rx_ptp_clk(qsfpdd_mac_rx_clk),
+    .mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk),
-    .mac_rx_ptp_rst(qsfpdd_mac_rx_rst),
+    .mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst),
     .mac_rx_ptp_ts_96(qsfpdd_mac_rx_ptp_time),
     .mac_rx_ptp_ts_step(),
 
@@ -738,8 +746,8 @@ mqnic_core_pcie_ptile #(
     .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
-    .PTP_SEPARATE_TX_CLOCK(0),
+    .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
-    .PTP_SEPARATE_RX_CLOCK(0),
+    .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.v

@@ -46,6 +46,7 @@ module test_fpga_core #
     // Board configuration
     parameter QSFPDD_CNT = 2,
     parameter CH_CNT = QSFPDD_CNT*2,
+    parameter PORT_GROUP_SIZE = 2,
 
     // Structural configuration
     parameter IF_COUNT = 2,
@@ -63,6 +64,8 @@ module test_fpga_core #
     parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
+    parameter PTP_SEPARATE_TX_CLOCK = 0,
+    parameter PTP_SEPARATE_RX_CLOCK = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 1,
     parameter PTP_PEROUT_COUNT = 1,
@@ -251,7 +254,10 @@ module test_fpga_core #
     // output wire [CH_CNT-1:0]                         qsfpdd_mac_tx_axis_tlast,
     // output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0]  qsfpdd_mac_tx_axis_tuser,
 
+    // input  wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_clk,
+    // input  wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_rst,
     // output wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_tx_ptp_time,
+
     // input  wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_tx_ptp_ts,
     // input  wire [CH_CNT*TX_TAG_WIDTH-1:0]            qsfpdd_mac_tx_ptp_ts_tag,
     // input  wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_ts_valid,
@@ -269,6 +275,8 @@ module test_fpga_core #
     // input  wire [CH_CNT-1:0]                         qsfpdd_mac_rx_axis_tlast,
     // input  wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0]  qsfpdd_mac_rx_axis_tuser,
 
+    // input  wire [CH_CNT-1:0]                         qsfpdd_mac_rx_ptp_clk,
+    // input  wire [CH_CNT-1:0]                         qsfpdd_mac_rx_ptp_rst,
     // output wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_rx_ptp_time,
 
     // input  wire [CH_CNT-1:0]                         qsfpdd_mac_rx_status,
@@ -310,7 +318,10 @@ wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_tx_ptp_ts;
 wire [CH_CNT*TX_TAG_WIDTH-1:0]            qsfpdd_mac_tx_ptp_ts_tag;
 wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_ts_valid;
 
+wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_clk;
+wire [CH_CNT-1:0]                         qsfpdd_mac_tx_ptp_rst;
 wire [CH_CNT-1:0]                         qsfpdd_mac_tx_status;
+
 wire [CH_CNT-1:0]                         qsfpdd_mac_tx_lfc_req;
 wire [CH_CNT*8-1:0]                       qsfpdd_mac_tx_pfc_req;
 
@@ -323,6 +334,8 @@ wire [CH_CNT-1:0]                         qsfpdd_mac_rx_axis_tvalid;
 wire [CH_CNT-1:0]                         qsfpdd_mac_rx_axis_tlast;
 wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0]  qsfpdd_mac_rx_axis_tuser;
 
+wire [CH_CNT-1:0]                         qsfpdd_mac_rx_ptp_clk;
+wire [CH_CNT-1:0]                         qsfpdd_mac_rx_ptp_rst;
 wire [CH_CNT*PTP_TS_WIDTH-1:0]            qsfpdd_mac_rx_ptp_time;
 
 wire [CH_CNT-1:0]                         qsfpdd_mac_rx_status;
@@ -343,9 +356,12 @@ for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch
     wire                               ch_mac_tx_axis_tlast;
     wire [AXIS_ETH_TX_USER_WIDTH-1:0]  ch_mac_tx_axis_tuser;
 
+    wire                               ch_mac_tx_ptp_clk;
+    wire                               ch_mac_tx_ptp_rst;
     wire [PTP_TS_WIDTH-1:0]            ch_mac_tx_ptp_time;
+
     wire [PTP_TS_WIDTH-1:0]            ch_mac_tx_ptp_ts;
-    wire [TX_TAG_WIDTH-1:0]            ch_mac_tx_ptp_ts_tag;
+    wire [15:0]                        ch_mac_tx_ptp_ts_tag;
     wire                               ch_mac_tx_ptp_ts_valid;
 
     wire                               ch_mac_tx_status;
@@ -361,6 +377,8 @@ for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch
     wire                               ch_mac_rx_axis_tlast;
     wire [AXIS_ETH_RX_USER_WIDTH-1:0]  ch_mac_rx_axis_tuser;
 
+    wire                               ch_mac_rx_ptp_clk;
+    wire                               ch_mac_rx_ptp_rst;
     wire [PTP_TS_WIDTH-1:0]            ch_mac_rx_ptp_time;
 
     wire                               ch_mac_rx_status;
@@ -377,7 +395,10 @@ for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch
     assign ch_mac_tx_axis_tlast = qsfpdd_mac_tx_axis_tlast[n +: 1];
     assign ch_mac_tx_axis_tuser = qsfpdd_mac_tx_axis_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH];
 
+    assign qsfpdd_mac_tx_ptp_clk[n +: 1] = ch_mac_tx_ptp_clk;
+    assign qsfpdd_mac_tx_ptp_rst[n +: 1] = ch_mac_tx_ptp_rst;
     assign ch_mac_tx_ptp_time = qsfpdd_mac_tx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
+
     assign qsfpdd_mac_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = ch_mac_tx_ptp_ts;
     assign qsfpdd_mac_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH] = ch_mac_tx_ptp_ts_tag;
     assign qsfpdd_mac_tx_ptp_ts_valid[n +: 1] = ch_mac_tx_ptp_ts_valid;
@@ -395,6 +416,8 @@ for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch
     assign qsfpdd_mac_rx_axis_tlast[n +: 1] = ch_mac_rx_axis_tlast;
     assign qsfpdd_mac_rx_axis_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = ch_mac_rx_axis_tuser;
 
+    assign qsfpdd_mac_rx_ptp_clk[n +: 1] = ch_mac_rx_ptp_clk;
+    assign qsfpdd_mac_rx_ptp_rst[n +: 1] = ch_mac_rx_ptp_rst;
     assign ch_mac_rx_ptp_time = qsfpdd_mac_rx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
 
     assign qsfpdd_mac_rx_status[n +: 1] = ch_mac_rx_status;
@@ -419,6 +442,7 @@ fpga_core #(
     // Board configuration
     .QSFPDD_CNT(QSFPDD_CNT),
     .CH_CNT(CH_CNT),
+    .PORT_GROUP_SIZE(PORT_GROUP_SIZE),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
@@ -436,6 +460,8 @@ fpga_core #(
     .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
+    .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
+    .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
@@ -624,7 +650,10 @@ uut (
     .qsfpdd_mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast),
     .qsfpdd_mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser),
 
+    .qsfpdd_mac_tx_ptp_clk(qsfpdd_mac_tx_ptp_clk),
+    .qsfpdd_mac_tx_ptp_rst(qsfpdd_mac_tx_ptp_rst),
     .qsfpdd_mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time),
+
     .qsfpdd_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts),
     .qsfpdd_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag),
     .qsfpdd_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid),
@@ -642,6 +671,8 @@ uut (
     .qsfpdd_mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast),
     .qsfpdd_mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser),
 
+    .qsfpdd_mac_rx_ptp_clk(qsfpdd_mac_rx_ptp_clk),
+    .qsfpdd_mac_rx_ptp_rst(qsfpdd_mac_rx_ptp_rst),
     .qsfpdd_mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time),
 
     .qsfpdd_mac_rx_status(qsfpdd_mac_rx_status),

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/README.md

@@ -1,31 +0,0 @@
-# Corundum mqnic for DK-DEV-AGF014EA
-
-## Introduction
-
-This design targets the Intel DK-DEV-AGF014EA FPGA development board.
-
-* FPGA: AGFB014R24B2E2V
-* PHY: E-Tile
-
-## Quick start
-
-### Build FPGA bitstream
-
-Run `make` in the `fpga` subdirectory to build the bitstream.  Ensure that the Intel Quartus Pro toolchain components are in PATH.
-
-### Build driver and userspace tools
-
-On the host system, run `make` in `modules/mqnic` to build the driver.  Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.  Then, run `make` in `utils` to build the userspace tools.
-
-### Testing
-
-Configure DIP switches:
-
-* SW1: off, on, on, off (AS_NORMAL)
-* SW2: all off (UART, Si52202, Si5341 all enable, select USB JTAG)
-* SW3: all off (enable all I2C interfaces)
-* SW4: off, on, on, off (select USB JTAG, bypass MAX10 JTAG, bypass MICTOR JTAG, enable FPGA JTAG)
-* SW6: 1 on, rest off (select x16)
-* SW7: off (PCIe reference clock from edge connector)
-
-Run `make program` to program the board with Quartus.  Then, reboot the machine to re-enumerate the PCIe bus.  Finally, load the driver on the host system with `insmod mqnic.ko`.  Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/app

@@ -1 +0,0 @@
-../../../app/

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/common/quartus_pro.mk

@@ -1,188 +0,0 @@
-###################################################################
-#
-# Makefile for Intel Quartus Prime Pro
-#
-# Alex Forencich
-#
-###################################################################
-#
-# Parameters:
-# FPGA_TOP - Top module name
-# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX)
-# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG)
-# SYN_FILES - space-separated list of source files
-# IP_FILES - space-separated list of IP files
-# IP_TCL_FILES - space-separated list of TCL files for qsys-script
-# QSF_FILES - space-separated list of settings files
-# SDC_FILES - space-separated list of timing constraint files
-#
-# Example:
-#
-# FPGA_TOP = fpga
-# FPGA_FAMILY = "Stratix 10 DX"
-# FPGA_DEVICE = 1SD280PT2F55E1VG
-# SYN_FILES = rtl/fpga.v
-# QSF_FILES = fpga.qsf
-# SDC_FILES = fpga.sdc
-# include ../common/quartus_pro.mk
-#
-###################################################################
-
-# phony targets
-.PHONY: clean fpga
-
-# output files to hang on to
-.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt
-.SECONDARY:
-
-# any project specific settings
-CONFIG ?= config.mk
--include ../$(CONFIG)
-
-SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
-
-IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES))
-IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES)))
-
-IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
-IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES)))
-IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES)))
-
-CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
-
-ifdef QSF_FILES
-  QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p))
-else
-  QSF_FILES_REL = ../$(FPGA_TOP).qsf
-endif
-
-SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
-
-ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf
-
-###################################################################
-# Main Targets
-#
-# all: build everything
-# clean: remove output files and database
-###################################################################
-
-all: fpga
-
-fpga: $(FPGA_TOP).sof
-
-quartus: $(FPGA_TOP).qpf
-	quartus $(FPGA_TOP).qpf
-
-tmpclean::
-	-rm -rf defines.v
-	-rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp
-	-rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit
-	-rm -rf create_project.tcl update_config.tcl update_ip_*.tcl
-
-clean:: tmpclean
-	-rm -rf *.sof *.pof *.jdi *.jic *.map
-
-distclean:: clean
-	-rm -rf rev
-
-syn: smart.log output_files/$(PROJECT).syn.rpt
-fit: smart.log output_files/$(PROJECT).fit.rpt
-asm: smart.log output_files/$(PROJECT).asm.rpt
-sta: smart.log output_files/$(PROJECT).sta.rpt
-smart: smart.log
-
-###################################################################
-# Executable Configuration
-###################################################################
-
-IP_ARGS  = --run_default_mode_op
-SYN_ARGS = --read_settings_files=on --write_settings_files=off
-FIT_ARGS = --read_settings_files=on --write_settings_files=off
-ASM_ARGS = --read_settings_files=on --write_settings_files=off
-STA_ARGS =
-
-###################################################################
-# Target implementations
-###################################################################
-
-STAMP = echo done >
-
-define COPY_IP_RULE
-$(patsubst %, ip/%, $(notdir $(1))): $(1)
-	@mkdir -p ip
-	@cp -pv $(1) ip/
-endef
-$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l))))
-
-define TCL_IP_GEN_RULE
-$(patsubst %.tcl,%.ip,$(1)): $(1)
-	cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf}
-	cd ip && qsys-script --script=$(notdir $(1))
-endef
-$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l))))
-
-%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
-	quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP)
-
-%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL)
-	quartus_syn $(SYN_ARGS) $(FPGA_TOP)
-
-%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL)
-	quartus_fit $(FIT_ARGS) $(FPGA_TOP)
-
-%.sta.rpt: sta.chg %.fit.rpt
-	quartus_sta $(STA_ARGS) $(FPGA_TOP)
-
-%.asm.rpt: asm.chg %.sta.rpt
-	quartus_asm $(ASM_ARGS) $(FPGA_TOP)
-	mkdir -p rev
-	EXT=sof; COUNT=100; \
-	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
-	do let COUNT=COUNT+1; done; \
-	cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \
-	echo "Output: rev/$*_rev$$COUNT.$$EXT";
-
-%.sof: smart.log %.asm.rpt
-	
-
-smart.log: $(ASSIGNMENT_FILES)
-	quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log
-
-###################################################################
-# Project initialization
-###################################################################
-
-create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
-	rm -f update_config.tcl
-	echo "project_new $(FPGA_TOP) -overwrite" > $@
-	echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@
-	echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@
-	for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \
-		case $${x##*.} in \
-			v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\
-			vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\
-			qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\
-			ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\
-			*) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\
-		esac; \
-	done
-	for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done
-	for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done
-
-update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL)
-	echo "project_open $(FPGA_TOP)" > $@
-	for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done
-
-$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl
-	for x in $?; do quartus_sh -t "$$x"; done
-	touch -c $(ASSIGNMENT_FILES)
-
-syn.chg:
-	$(STAMP) syn.chg
-fit.chg:
-	$(STAMP) fit.chg
-sta.chg:
-	$(STAMP) sta.chg
-asm.chg:
-	$(STAMP) asm.chg

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga.qsf

@@ -1,349 +0,0 @@
-# I/O constraints for the Intel DK-DEV-AGF014EA FPGA development board
-# part: AGFB014R24B2E2V
-
-set_global_assignment -name USE_CONF_DONE SDM_IO16
-set_global_assignment -name USE_CVP_CONFDONE SDM_IO10
-set_global_assignment -name USE_INIT_DONE SDM_IO0
-set_global_assignment -name USE_HPS_COLD_RESET SDM_IO13
-
-set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
-set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401
-set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 47
-set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
-set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
-set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF
-set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
-set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
-set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"
-set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
-set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
-
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
-set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
-set_global_assignment -name GENERATE_COMPRESSED_SOF ON
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-set_global_assignment -name GENERATE_PR_RBF_FILE ON
-set_global_assignment -name ENABLE_ED_CRC_CHECK ON
-
-set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
-
-set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on
-
-# Clock and reset
-set_location_assignment PIN_CU24 -to clk_sys_100m_p
-set_location_assignment PIN_G26  -to clk_sys_bak_50m_p
-
-set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to clk_sys_100m_p
-set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to clk_sys_bak_50m_p
-
-set_location_assignment PIN_AD11 -to hps_osc_clk
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_osc_clk
-
-# Switches, buttons, LEDs
-set_location_assignment PIN_A24  -to cpu_resetn
-
-set_location_assignment PIN_C30  -to fpga_led[0]
-set_location_assignment PIN_A30  -to fpga_led[1]
-set_location_assignment PIN_D31  -to fpga_led[2]
-set_location_assignment PIN_B31  -to fpga_led[3]
-set_location_assignment PIN_H19  -to qsfpdd0_led0
-set_location_assignment PIN_F19  -to qsfpdd0_led1_g
-set_location_assignment PIN_J20  -to qsfpdd0_led1_y
-set_location_assignment PIN_G20  -to qsfpdd1_led0
-set_location_assignment PIN_H21  -to qsfpdd1_led1_g
-set_location_assignment PIN_F21  -to qsfpdd1_led1_y
-
-set_instance_assignment -name IO_STANDARD "1.2 V" -to cpu_resetn
-
-set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_led[0]
-set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_led[1]
-set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_led[2]
-set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_led[3]
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd0_led0
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd0_led1_g
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd0_led1_y
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd1_led0
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd1_led1_g
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd1_led1_y
-
-# I2C
-set_location_assignment PIN_F23  -to fpga_i2c_scl
-set_location_assignment PIN_D19  -to fpga_i2c_sda
-
-set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_i2c_scl
-set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_i2c_sda
-
-# PCIe
-set_location_assignment PIN_BP55 -to pcie_tx_p[0]      ;# GXPL10A_TX_CH0P
-set_location_assignment PIN_BN52 -to pcie_tx_p[1]      ;# GXPL10A_TX_CH1P
-set_location_assignment PIN_BK55 -to pcie_tx_p[2]      ;# GXPL10A_TX_CH2P
-set_location_assignment PIN_BJ52 -to pcie_tx_p[3]      ;# GXPL10A_TX_CH3P
-set_location_assignment PIN_BF55 -to pcie_tx_p[4]      ;# GXPL10A_TX_CH4P
-set_location_assignment PIN_BE52 -to pcie_tx_p[5]      ;# GXPL10A_TX_CH5P
-set_location_assignment PIN_BB55 -to pcie_tx_p[6]      ;# GXPL10A_TX_CH6P
-set_location_assignment PIN_BA52 -to pcie_tx_p[7]      ;# GXPL10A_TX_CH7P
-set_location_assignment PIN_AV55 -to pcie_tx_p[8]      ;# GXPL10A_TX_CH8P
-set_location_assignment PIN_AU52 -to pcie_tx_p[9]      ;# GXPL10A_TX_CH9P
-set_location_assignment PIN_AP55 -to pcie_tx_p[10]     ;# GXPL10A_TX_CH10P
-set_location_assignment PIN_AN52 -to pcie_tx_p[11]     ;# GXPL10A_TX_CH11P
-set_location_assignment PIN_AK55 -to pcie_tx_p[12]     ;# GXPL10A_TX_CH12P
-set_location_assignment PIN_AJ52 -to pcie_tx_p[13]     ;# GXPL10A_TX_CH13P
-set_location_assignment PIN_AF55 -to pcie_tx_p[14]     ;# GXPL10A_TX_CH14P
-set_location_assignment PIN_AE52 -to pcie_tx_p[15]     ;# GXPL10A_TX_CH15P
-set_location_assignment PIN_BR56 -to pcie_tx_n[0]      ;# GXPL10A_TX_CH0N
-set_location_assignment PIN_BM53 -to pcie_tx_n[1]      ;# GXPL10A_TX_CH1N
-set_location_assignment PIN_BL56 -to pcie_tx_n[2]      ;# GXPL10A_TX_CH2N
-set_location_assignment PIN_BH53 -to pcie_tx_n[3]      ;# GXPL10A_TX_CH3N
-set_location_assignment PIN_BG56 -to pcie_tx_n[4]      ;# GXPL10A_TX_CH4N
-set_location_assignment PIN_BD53 -to pcie_tx_n[5]      ;# GXPL10A_TX_CH5N
-set_location_assignment PIN_BC56 -to pcie_tx_n[6]      ;# GXPL10A_TX_CH6N
-set_location_assignment PIN_AY53 -to pcie_tx_n[7]      ;# GXPL10A_TX_CH7N
-set_location_assignment PIN_AW56 -to pcie_tx_n[8]      ;# GXPL10A_TX_CH8N
-set_location_assignment PIN_AT53 -to pcie_tx_n[9]      ;# GXPL10A_TX_CH9N
-set_location_assignment PIN_AR56 -to pcie_tx_n[10]     ;# GXPL10A_TX_CH10N
-set_location_assignment PIN_AM53 -to pcie_tx_n[11]     ;# GXPL10A_TX_CH11N
-set_location_assignment PIN_AL56 -to pcie_tx_n[12]     ;# GXPL10A_TX_CH12N
-set_location_assignment PIN_AH53 -to pcie_tx_n[13]     ;# GXPL10A_TX_CH13N
-set_location_assignment PIN_AG56 -to pcie_tx_n[14]     ;# GXPL10A_TX_CH14N
-set_location_assignment PIN_AD53 -to pcie_tx_n[15]     ;# GXPL10A_TX_CH15N
-set_location_assignment PIN_BP61 -to pcie_rx_p[0]      ;# GXPL10A_RX_CH0P
-set_location_assignment PIN_BN58 -to pcie_rx_p[1]      ;# GXPL10A_RX_CH1P
-set_location_assignment PIN_BK61 -to pcie_rx_p[2]      ;# GXPL10A_RX_CH2P
-set_location_assignment PIN_BJ58 -to pcie_rx_p[3]      ;# GXPL10A_RX_CH3P
-set_location_assignment PIN_BF61 -to pcie_rx_p[4]      ;# GXPL10A_RX_CH4P
-set_location_assignment PIN_BE58 -to pcie_rx_p[5]      ;# GXPL10A_RX_CH5P
-set_location_assignment PIN_BB61 -to pcie_rx_p[6]      ;# GXPL10A_RX_CH6P
-set_location_assignment PIN_BA58 -to pcie_rx_p[7]      ;# GXPL10A_RX_CH7P
-set_location_assignment PIN_AV61 -to pcie_rx_p[8]      ;# GXPL10A_RX_CH8P
-set_location_assignment PIN_AU58 -to pcie_rx_p[9]      ;# GXPL10A_RX_CH9P
-set_location_assignment PIN_AP61 -to pcie_rx_p[10]     ;# GXPL10A_RX_CH10P
-set_location_assignment PIN_AN58 -to pcie_rx_p[11]     ;# GXPL10A_RX_CH11P
-set_location_assignment PIN_AK61 -to pcie_rx_p[12]     ;# GXPL10A_RX_CH12P
-set_location_assignment PIN_AJ58 -to pcie_rx_p[13]     ;# GXPL10A_RX_CH13P
-set_location_assignment PIN_AF61 -to pcie_rx_p[14]     ;# GXPL10A_RX_CH14P
-set_location_assignment PIN_AE58 -to pcie_rx_p[15]     ;# GXPL10A_RX_CH15P
-set_location_assignment PIN_BR62 -to pcie_rx_n[0]      ;# GXPL10A_RX_CH0N
-set_location_assignment PIN_BM59 -to pcie_rx_n[1]      ;# GXPL10A_RX_CH1N
-set_location_assignment PIN_BL62 -to pcie_rx_n[2]      ;# GXPL10A_RX_CH2N
-set_location_assignment PIN_BH59 -to pcie_rx_n[3]      ;# GXPL10A_RX_CH3N
-set_location_assignment PIN_BG62 -to pcie_rx_n[4]      ;# GXPL10A_RX_CH4N
-set_location_assignment PIN_BD59 -to pcie_rx_n[5]      ;# GXPL10A_RX_CH5N
-set_location_assignment PIN_BC62 -to pcie_rx_n[6]      ;# GXPL10A_RX_CH6N
-set_location_assignment PIN_AY59 -to pcie_rx_n[7]      ;# GXPL10A_RX_CH7N
-set_location_assignment PIN_AW62 -to pcie_rx_n[8]      ;# GXPL10A_RX_CH8N
-set_location_assignment PIN_AT59 -to pcie_rx_n[9]      ;# GXPL10A_RX_CH9N
-set_location_assignment PIN_AR62 -to pcie_rx_n[10]     ;# GXPL10A_RX_CH10N
-set_location_assignment PIN_AM59 -to pcie_rx_n[11]     ;# GXPL10A_RX_CH11N
-set_location_assignment PIN_AL62 -to pcie_rx_n[12]     ;# GXPL10A_RX_CH12N
-set_location_assignment PIN_AH59 -to pcie_rx_n[13]     ;# GXPL10A_RX_CH13N
-set_location_assignment PIN_AG62 -to pcie_rx_n[14]     ;# GXPL10A_RX_CH14N
-set_location_assignment PIN_AD59 -to pcie_rx_n[15]     ;# GXPL10A_RX_CH15N
-set_location_assignment PIN_AJ48 -to pcie_refclk_p[0]  ;# REFCLK_GXPL10A_CH0P
-set_location_assignment PIN_AE48 -to pcie_refclk_p[1]  ;# REFCLK_GXPL10A_CH2P
-set_location_assignment PIN_BU58 -to pcie_perst_n      ;# I_PIN_PERST_N_U10_P
-
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[12]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[13]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[14]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_p[15]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[12]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[13]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[14]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_tx_n[15]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[12]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[13]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[14]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_p[15]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[12]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[13]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[14]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_rx_n[15]
-set_instance_assignment -name IO_STANDARD "HCSL" -to pcie_refclk_p[0]
-set_instance_assignment -name IO_STANDARD "HCSL" -to pcie_refclk_p[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_perst_n
-
-# QSFP-DD
-set_location_assignment PIN_AK1  -to qsfpdd0_tx_p[0]       ;# GXER9A_TX_CH0P
-set_location_assignment PIN_AP1  -to qsfpdd0_tx_p[1]       ;# GXER9A_TX_CH2P
-set_location_assignment PIN_AL4  -to qsfpdd0_tx_p[2]       ;# GXER9A_TX_CH1P
-set_location_assignment PIN_AR4  -to qsfpdd0_tx_p[3]       ;# GXER9A_TX_CH3P
-set_location_assignment PIN_AV1  -to qsfpdd0_tx_p[4]       ;# GXER9A_TX_CH8P
-set_location_assignment PIN_BB1  -to qsfpdd0_tx_p[5]       ;# GXER9A_TX_CH10P
-set_location_assignment PIN_AW4  -to qsfpdd0_tx_p[6]       ;# GXER9A_TX_CH9P
-set_location_assignment PIN_BC4  -to qsfpdd0_tx_p[7]       ;# GXER9A_TX_CH11P
-set_location_assignment PIN_AJ2  -to qsfpdd0_tx_n[0]       ;# GXER9A_TX_CH0N
-set_location_assignment PIN_AN2  -to qsfpdd0_tx_n[1]       ;# GXER9A_TX_CH2N
-set_location_assignment PIN_AM5  -to qsfpdd0_tx_n[2]       ;# GXER9A_TX_CH1N
-set_location_assignment PIN_AT5  -to qsfpdd0_tx_n[3]       ;# GXER9A_TX_CH3N
-set_location_assignment PIN_AU2  -to qsfpdd0_tx_n[4]       ;# GXER9A_TX_CH8N
-set_location_assignment PIN_BA2  -to qsfpdd0_tx_n[5]       ;# GXER9A_TX_CH10N
-set_location_assignment PIN_AY5  -to qsfpdd0_tx_n[6]       ;# GXER9A_TX_CH9N
-set_location_assignment PIN_BD5  -to qsfpdd0_tx_n[7]       ;# GXER9A_TX_CH11N
-set_location_assignment PIN_AK7  -to qsfpdd0_rx_p[0]       ;# GXER9A_RX_CH0P
-set_location_assignment PIN_AP7  -to qsfpdd0_rx_p[1]       ;# GXER9A_RX_CH2P
-set_location_assignment PIN_AL10 -to qsfpdd0_rx_p[2]       ;# GXER9A_RX_CH1P
-set_location_assignment PIN_AR10 -to qsfpdd0_rx_p[3]       ;# GXER9A_RX_CH3P
-set_location_assignment PIN_AV7  -to qsfpdd0_rx_p[4]       ;# GXER9A_RX_CH8P
-set_location_assignment PIN_BB7  -to qsfpdd0_rx_p[5]       ;# GXER9A_RX_CH10P
-set_location_assignment PIN_AW10 -to qsfpdd0_rx_p[6]       ;# GXER9A_RX_CH9P
-set_location_assignment PIN_BC10 -to qsfpdd0_rx_p[7]       ;# GXER9A_RX_CH11P
-set_location_assignment PIN_AJ8  -to qsfpdd0_rx_n[0]       ;# GXER9A_RX_CH0N
-set_location_assignment PIN_AN8  -to qsfpdd0_rx_n[1]       ;# GXER9A_RX_CH2N
-set_location_assignment PIN_AM11 -to qsfpdd0_rx_n[2]       ;# GXER9A_RX_CH1N
-set_location_assignment PIN_AT11 -to qsfpdd0_rx_n[3]       ;# GXER9A_RX_CH3N
-set_location_assignment PIN_AU8  -to qsfpdd0_rx_n[4]       ;# GXER9A_RX_CH8N
-set_location_assignment PIN_BA8  -to qsfpdd0_rx_n[5]       ;# GXER9A_RX_CH10N
-set_location_assignment PIN_AY11 -to qsfpdd0_rx_n[6]       ;# GXER9A_RX_CH9N
-set_location_assignment PIN_BD11 -to qsfpdd0_rx_n[7]       ;# GXER9A_RX_CH11N
-
-set_location_assignment PIN_BF1  -to qsfpdd1_tx_p[0]       ;# GXER9A_TX_CH12P
-set_location_assignment PIN_BK1  -to qsfpdd1_tx_p[1]       ;# GXER9A_TX_CH14P
-set_location_assignment PIN_BG4  -to qsfpdd1_tx_p[2]       ;# GXER9A_TX_CH13P
-set_location_assignment PIN_BL4  -to qsfpdd1_tx_p[3]       ;# GXER9A_TX_CH15P
-set_location_assignment PIN_BP1  -to qsfpdd1_tx_p[4]       ;# GXER9A_TX_CH20P
-set_location_assignment PIN_BV1  -to qsfpdd1_tx_p[5]       ;# GXER9A_TX_CH22P
-set_location_assignment PIN_BR4  -to qsfpdd1_tx_p[6]       ;# GXER9A_TX_CH21P
-set_location_assignment PIN_BW4  -to qsfpdd1_tx_p[7]       ;# GXER9A_TX_CH23P
-set_location_assignment PIN_BE2  -to qsfpdd1_tx_n[0]       ;# GXER9A_TX_CH12N
-set_location_assignment PIN_BJ2  -to qsfpdd1_tx_n[1]       ;# GXER9A_TX_CH14N
-set_location_assignment PIN_BH5  -to qsfpdd1_tx_n[2]       ;# GXER9A_TX_CH13N
-set_location_assignment PIN_BM5  -to qsfpdd1_tx_n[3]       ;# GXER9A_TX_CH15N
-set_location_assignment PIN_BN2  -to qsfpdd1_tx_n[4]       ;# GXER9A_TX_CH20N
-set_location_assignment PIN_BU2  -to qsfpdd1_tx_n[5]       ;# GXER9A_TX_CH22N
-set_location_assignment PIN_BT5  -to qsfpdd1_tx_n[6]       ;# GXER9A_TX_CH21N
-set_location_assignment PIN_BY5  -to qsfpdd1_tx_n[7]       ;# GXER9A_TX_CH23N
-set_location_assignment PIN_BF7  -to qsfpdd1_rx_p[0]       ;# GXER9A_RX_CH12P
-set_location_assignment PIN_BK7  -to qsfpdd1_rx_p[1]       ;# GXER9A_RX_CH14P
-set_location_assignment PIN_BG10 -to qsfpdd1_rx_p[2]       ;# GXER9A_RX_CH13P
-set_location_assignment PIN_BL10 -to qsfpdd1_rx_p[3]       ;# GXER9A_RX_CH15P
-set_location_assignment PIN_BP7  -to qsfpdd1_rx_p[4]       ;# GXER9A_RX_CH20P
-set_location_assignment PIN_BV7  -to qsfpdd1_rx_p[5]       ;# GXER9A_RX_CH22P
-set_location_assignment PIN_BR10 -to qsfpdd1_rx_p[6]       ;# GXER9A_RX_CH21P
-set_location_assignment PIN_BW10 -to qsfpdd1_rx_p[7]       ;# GXER9A_RX_CH23P
-set_location_assignment PIN_BE8  -to qsfpdd1_rx_n[0]       ;# GXER9A_RX_CH12N
-set_location_assignment PIN_BJ8  -to qsfpdd1_rx_n[1]       ;# GXER9A_RX_CH14N
-set_location_assignment PIN_BH11 -to qsfpdd1_rx_n[2]       ;# GXER9A_RX_CH13N
-set_location_assignment PIN_BM11 -to qsfpdd1_rx_n[3]       ;# GXER9A_RX_CH15N
-set_location_assignment PIN_BN8  -to qsfpdd1_rx_n[4]       ;# GXER9A_RX_CH20N
-set_location_assignment PIN_BU8  -to qsfpdd1_rx_n[5]       ;# GXER9A_RX_CH22N
-set_location_assignment PIN_BT11 -to qsfpdd1_rx_n[6]       ;# GXER9A_RX_CH21N
-set_location_assignment PIN_BY11 -to qsfpdd1_rx_n[7]       ;# GXER9A_RX_CH23N
-
-set_location_assignment PIN_AT13 -to refclk_322m_qsfpdd_p  ;# REFCLK_GXER9A_CH0P
-set_location_assignment PIN_AR14 -to refclk_156m_qsfpdd_p  ;# REFCLK_GXER9A_CH1P
-
-set_location_assignment PIN_C26  -to qsfpdd0_modsel_l
-set_location_assignment PIN_J30  -to qsfpdd0_reset_l
-set_location_assignment PIN_G30  -to qsfpdd0_modprs_l
-set_location_assignment PIN_H31  -to qsfpdd0_lpmode
-set_location_assignment PIN_F31  -to qsfpdd0_int_l
-set_location_assignment PIN_B27  -to qsfpdd1_modsel_l
-set_location_assignment PIN_A26  -to qsfpdd1_reset_l
-set_location_assignment PIN_D27  -to qsfpdd1_modprs_l
-set_location_assignment PIN_A28  -to qsfpdd1_lpmode
-set_location_assignment PIN_C28  -to qsfpdd1_int_l
-set_location_assignment PIN_D29  -to qsfpdd_i2c_scl
-set_location_assignment PIN_G28  -to qsfpdd_i2c_sda
-
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_tx_p[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_tx_p[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_tx_p[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_tx_p[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_tx_p[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_tx_p[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_tx_p[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_tx_p[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_rx_p[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_rx_p[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_rx_p[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_rx_p[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_rx_p[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_rx_p[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_rx_p[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd0_rx_p[7]
-
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_tx_p[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_tx_p[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_tx_p[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_tx_p[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_tx_p[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_tx_p[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_tx_p[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_tx_p[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_rx_p[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_rx_p[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_rx_p[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_rx_p[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_rx_p[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_rx_p[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_rx_p[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfpdd1_rx_p[7]
-
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to refclk_322m_qsfpdd_p
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to refclk_156m_qsfpdd_p
-
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd0_modsel_l
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd0_reset_l
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd0_modprs_l
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd0_lpmode
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd0_int_l
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd1_modsel_l
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd1_reset_l
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd1_modprs_l
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd1_lpmode
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd1_int_l
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd_i2c_scl
-set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd_i2c_sda
-
-set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_BTI_clock=TRUE" -to refclk_156m_qsfpdd_p
-set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=156250000" -to refclk_156m_qsfpdd_p

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga.sdc

@@ -1,101 +0,0 @@
-# Timing constraints for the Intel DK-DEV-AGF014EA FPGA development board
-
-set_time_format -unit ns -decimal_places 3
-
-# Clock constraints
-create_clock -period 10.000 -name "clk_sys_100m" [ get_ports "clk_sys_100m_p" ]
-create_clock -period 20.000 -name "clk_sys_bak_50m" [ get_ports "clk_sys_bak_50m_p" ]
-create_clock -period 40.000 -name "hps_osc_clk" [ get_ports "hps_osc_clk" ]
-
-create_clock -period 10.000 -name "pcie_refclk_0" [ get_ports "pcie_refclk_p[0]" ]
-create_clock -period 10.000 -name "pcie_refclk_1" [ get_ports "pcie_refclk_p[1]" ]
-
-create_clock -period 3.103 -name "refclk_322m_qsfpdd" [ get_ports "refclk_322m_qsfpdd_p" ]
-create_clock -period 6.400 -name "refclk_156m_qsfpdd" [ get_ports "refclk_156m_qsfpdd_p" ]
-
-create_clock -period 30.000 -name "clk_ddr4_ch0" [ get_ports "clk_ddr4_ch0_p" ]
-create_clock -period 30.000 -name "clk_ddr4_ch1" [ get_ports "clk_ddr4_ch1_p" ]
-create_clock -period 30.000 -name "clk_ddr4_ch2" [ get_ports "clk_ddr4_ch2_p" ]
-create_clock -period 30.000 -name "clk_ddr4_ch3" [ get_ports "clk_ddr4_ch3_p" ]
-
-derive_clock_uncertainty
-
-set_clock_groups -asynchronous -group [ get_clocks "clk_sys_100m" ]
-set_clock_groups -asynchronous -group [ get_clocks "clk_sys_bak_50m" ]
-set_clock_groups -asynchronous -group [ get_clocks "hps_osc_clk" ]
-
-set_clock_groups -asynchronous -group [ get_clocks "pcie_refclk_0" ]
-set_clock_groups -asynchronous -group [ get_clocks "pcie_refclk_1" ]
-
-set_clock_groups -asynchronous -group [ get_clocks "refclk_322m_qsfpdd" ]
-set_clock_groups -asynchronous -group [ get_clocks "refclk_156m_qsfpdd" ]
-
-set_clock_groups -asynchronous -group [ get_clocks "clk_ddr4_ch0" ]
-set_clock_groups -asynchronous -group [ get_clocks "clk_ddr4_ch1" ]
-set_clock_groups -asynchronous -group [ get_clocks "clk_ddr4_ch2" ]
-set_clock_groups -asynchronous -group [ get_clocks "clk_ddr4_ch3" ]
-
-# JTAG constraints
-create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }]
-
-set_clock_groups -asynchronous -group [get_clocks "altera_reserved_tck"]
-set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tdi]
-set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tms]
-set_output_delay -clock altera_reserved_tck -clock_fall -max 6 [get_ports altera_reserved_tdo]
-
-# IO constraints
-set_false_path -from "cpu_resetn"
-
-set_false_path -to   "fpga_led[*]"
-set_false_path -to   "qsfpdd0_led0"
-set_false_path -to   "qsfpdd0_led1_g"
-set_false_path -to   "qsfpdd0_led1_y"
-set_false_path -to   "qsfpdd1_led0"
-set_false_path -to   "qsfpdd1_led1_g"
-set_false_path -to   "qsfpdd1_led1_y"
-
-set_false_path -from "pcie_perst_n"
-
-
-source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
-
-# clocking infrastructure
-constrain_sync_reset_inst "sync_reset_100mhz_inst"
-constrain_sync_reset_inst "ptp_rst_reset_sync_inst"
-
-# PCIe clock
-set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|xcvr_hip_native|rx_ch15" ]
-
-# E-Tile MACs
-set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_refclk" ]
-set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_outclk0" ]
-
-proc constrain_etile_mac_dual_quad { inst } {
-    puts "Inserting timing constraints for MAC quad $inst"
-
-    foreach mac {mac_02_inst mac_13_inst} {
-        for {set i 0} {$i < 4} {incr i} {
-            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ]
-            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ]
-            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ]
-            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ]
-            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ]
-            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ]
-            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ]
-            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ]
-        }
-
-        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
-        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
-        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp_plloff|tx_transfer_clk|ch0" ]
-    }
-
-    for {set i 0} {$i < 8} {incr i} {
-        constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_reset_sync_inst"
-        constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_ptp_reset_sync_inst"
-        constrain_sync_reset_inst "$inst|mac_ch[$i].mac_rx_ptp_reset_sync_inst"
-    }
-}
-
-constrain_etile_mac_dual_quad "qsfpdd0_mac_inst"
-constrain_etile_mac_dual_quad "qsfpdd1_mac_inst"

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/ip/reset_release.tcl

@@ -1,52 +0,0 @@
-package require -exact qsys 21.3
-
-# create the system "reset_release"
-proc do_create_reset_release {} {
-	# create the system
-	create_system reset_release
-	set_project_property DEVICE {AGFB014R24B2E2V}
-	set_project_property DEVICE_FAMILY {Agilex}
-	set_project_property HIDE_FROM_IP_CATALOG {true}
-	set_use_testbench_naming_pattern 0 {}
-
-	# add HDL parameters
-
-	# add the components
-	add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate
-	set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface}
-	set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true
-
-	# add wirelevel expressions
-
-	# preserve ports for debug
-
-	# add the exports
-	set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done
-
-	# set values for exposed HDL parameters
-
-	# set the the module properties
-	set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
-<bonusData>
- <element __value="s10_user_rst_clkgate_0">
-  <datum __value="_sortIndex" value="0" type="int" />
- </element>
-</bonusData>
-}
-	set_module_property FILE {reset_release.ip}
-	set_module_property GENERATION_ID {0x00000000}
-	set_module_property NAME {reset_release}
-
-	# save the system
-	sync_sysinfo_parameters
-	save_system reset_release
-}
-
-proc do_set_exported_interface_sysinfo_parameters {} {
-}
-
-# create all the systems, from bottom up
-do_create_reset_release
-
-# set system info parameters on exported interface, from bottom up
-do_set_exported_interface_sysinfo_parameters

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/lib

@@ -1 +0,0 @@
-../../../lib/

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/axis_fifo.v

@@ -1,565 +0,0 @@
-/*
-
-Copyright (c) 2013-2023 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`resetall
-`timescale 1ns / 1ps
-`default_nettype none
-
-/*
- * AXI4-Stream FIFO
- */
-module axis_fifo #
-(
-    // FIFO depth in words
-    // KEEP_WIDTH words per cycle if KEEP_ENABLE set
-    // Rounded up to nearest power of 2 cycles
-    parameter DEPTH = 4096,
-    // Width of AXI stream interfaces in bits
-    parameter DATA_WIDTH = 8,
-    // Propagate tkeep signal
-    // If disabled, tkeep assumed to be 1'b1
-    parameter KEEP_ENABLE = (DATA_WIDTH>8),
-    // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
-    // Propagate tlast signal
-    parameter LAST_ENABLE = 1,
-    // Propagate tid signal
-    parameter ID_ENABLE = 0,
-    // tid signal width
-    parameter ID_WIDTH = 8,
-    // Propagate tdest signal
-    parameter DEST_ENABLE = 0,
-    // tdest signal width
-    parameter DEST_WIDTH = 8,
-    // Propagate tuser signal
-    parameter USER_ENABLE = 1,
-    // tuser signal width
-    parameter USER_WIDTH = 1,
-    // number of RAM pipeline registers
-    parameter RAM_PIPELINE = 1,
-    // use output FIFO
-    // When set, the RAM read enable and pipeline clock enables are removed
-    parameter OUTPUT_FIFO_ENABLE = 0,
-    // Frame FIFO mode - operate on frames instead of cycles
-    // When set, m_axis_tvalid will not be deasserted within a frame
-    // Requires LAST_ENABLE set
-    parameter FRAME_FIFO = 0,
-    // tuser value for bad frame marker
-    parameter USER_BAD_FRAME_VALUE = 1'b1,
-    // tuser mask for bad frame marker
-    parameter USER_BAD_FRAME_MASK = 1'b1,
-    // Drop frames larger than FIFO
-    // Requires FRAME_FIFO set
-    parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
-    // Drop frames marked bad
-    // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
-    parameter DROP_BAD_FRAME = 0,
-    // Drop incoming frames when full
-    // When set, s_axis_tready is always asserted
-    // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
-    parameter DROP_WHEN_FULL = 0,
-    // Mark incoming frames as bad frames when full
-    // When set, s_axis_tready is always asserted
-    // Requires FRAME_FIFO to be clear
-    parameter MARK_WHEN_FULL = 0,
-    // Enable pause request input
-    parameter PAUSE_ENABLE = 0,
-    // Pause between frames
-    parameter FRAME_PAUSE = FRAME_FIFO
-)
-(
-    input  wire                   clk,
-    input  wire                   rst,
-
-    /*
-     * AXI input
-     */
-    input  wire [DATA_WIDTH-1:0]  s_axis_tdata,
-    input  wire [KEEP_WIDTH-1:0]  s_axis_tkeep,
-    input  wire                   s_axis_tvalid,
-    output wire                   s_axis_tready,
-    input  wire                   s_axis_tlast,
-    input  wire [ID_WIDTH-1:0]    s_axis_tid,
-    input  wire [DEST_WIDTH-1:0]  s_axis_tdest,
-    input  wire [USER_WIDTH-1:0]  s_axis_tuser,
-
-    /*
-     * AXI output
-     */
-    output wire [DATA_WIDTH-1:0]  m_axis_tdata,
-    output wire [KEEP_WIDTH-1:0]  m_axis_tkeep,
-    output wire                   m_axis_tvalid,
-    input  wire                   m_axis_tready,
-    output wire                   m_axis_tlast,
-    output wire [ID_WIDTH-1:0]    m_axis_tid,
-    output wire [DEST_WIDTH-1:0]  m_axis_tdest,
-    output wire [USER_WIDTH-1:0]  m_axis_tuser,
-
-    /*
-     * Pause
-     */
-    input  wire                   pause_req,
-    output wire                   pause_ack,
-
-    /*
-     * Status
-     */
-    output wire [$clog2(DEPTH):0] status_depth,
-    output wire [$clog2(DEPTH):0] status_depth_commit,
-    output wire                   status_overflow,
-    output wire                   status_bad_frame,
-    output wire                   status_good_frame
-);
-
-parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
-
-parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
-
-// check configuration
-initial begin
-    if (FRAME_FIFO && !LAST_ENABLE) begin
-        $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
-        $finish;
-    end
-
-    if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin
-        $error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
-        $finish;
-    end
-
-    if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
-        $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
-        $finish;
-    end
-
-    if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
-        $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
-        $finish;
-    end
-
-    if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
-        $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
-        $finish;
-    end
-
-    if (MARK_WHEN_FULL && FRAME_FIFO) begin
-        $error("Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)");
-        $finish;
-    end
-
-    if (MARK_WHEN_FULL && !LAST_ENABLE) begin
-        $error("Error: MARK_WHEN_FULL set requires LAST_ENABLE set (instance %m)");
-        $finish;
-    end
-end
-
-localparam KEEP_OFFSET = DATA_WIDTH;
-localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
-localparam ID_OFFSET   = LAST_OFFSET + (LAST_ENABLE ? 1          : 0);
-localparam DEST_OFFSET = ID_OFFSET   + (ID_ENABLE   ? ID_WIDTH   : 0);
-localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
-localparam WIDTH       = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
-
-reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] wr_ptr_commit_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
-
-// (* ramstyle = "no_rw_check" *)
-// Workaround for Quartus MLAB RAM read enable bug
-// https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html
-(* ramstyle = "no_rw_check, m20k" *)
-reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
-reg mem_read_data_valid_reg = 1'b0;
-
-(* shreg_extract = "no" *)
-reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0];
-reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0;
-
-// full when first MSB different but rest same
-wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
-// empty when pointers match exactly
-wire empty = wr_ptr_commit_reg == rd_ptr_reg;
-// overflow within packet
-wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
-
-reg s_frame_reg = 1'b0;
-
-reg drop_frame_reg = 1'b0;
-reg mark_frame_reg = 1'b0;
-reg send_frame_reg = 1'b0;
-reg [ADDR_WIDTH:0] depth_reg = 0;
-reg [ADDR_WIDTH:0] depth_commit_reg = 0;
-reg overflow_reg = 1'b0;
-reg bad_frame_reg = 1'b0;
-reg good_frame_reg = 1'b0;
-
-assign s_axis_tready = FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL);
-
-wire [WIDTH-1:0] s_axis;
-
-generate
-    assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
-    if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
-    if (LAST_ENABLE) assign s_axis[LAST_OFFSET]               = s_axis_tlast | mark_frame_reg;
-    if (ID_ENABLE)   assign s_axis[ID_OFFSET   +: ID_WIDTH]   = s_axis_tid;
-    if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
-    if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis_tuser;
-endgenerate
-
-wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1];
-
-wire                   m_axis_tready_pipe;
-wire                   m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1];
-
-wire [DATA_WIDTH-1:0]  m_axis_tdata_pipe  = m_axis[DATA_WIDTH-1:0];
-wire [KEEP_WIDTH-1:0]  m_axis_tkeep_pipe  = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
-wire                   m_axis_tlast_pipe  = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1;
-wire [ID_WIDTH-1:0]    m_axis_tid_pipe    = ID_ENABLE   ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
-wire [DEST_WIDTH-1:0]  m_axis_tdest_pipe  = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
-wire [USER_WIDTH-1:0]  m_axis_tuser_pipe  = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
-
-wire                   m_axis_tready_out;
-wire                   m_axis_tvalid_out;
-
-wire [DATA_WIDTH-1:0]  m_axis_tdata_out;
-wire [KEEP_WIDTH-1:0]  m_axis_tkeep_out;
-wire                   m_axis_tlast_out;
-wire [ID_WIDTH-1:0]    m_axis_tid_out;
-wire [DEST_WIDTH-1:0]  m_axis_tdest_out;
-wire [USER_WIDTH-1:0]  m_axis_tuser_out;
-
-wire pipe_ready;
-
-assign status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_reg;
-assign status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_commit_reg;
-assign status_overflow = overflow_reg;
-assign status_bad_frame = bad_frame_reg;
-assign status_good_frame = good_frame_reg;
-
-// Write logic
-always @(posedge clk) begin
-    overflow_reg <= 1'b0;
-    bad_frame_reg <= 1'b0;
-    good_frame_reg <= 1'b0;
-
-    if (s_axis_tready && s_axis_tvalid && LAST_ENABLE) begin
-        // track input frame status
-        s_frame_reg <= !s_axis_tlast;
-    end
-
-    if (FRAME_FIFO) begin
-        // frame FIFO mode
-        if (s_axis_tready && s_axis_tvalid) begin
-            // transfer in
-            if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
-                // full, packet overflow, or currently dropping frame
-                // drop frame
-                drop_frame_reg <= 1'b1;
-                if (s_axis_tlast) begin
-                    // end of frame, reset write pointer
-                    wr_ptr_reg <= wr_ptr_commit_reg;
-                    drop_frame_reg <= 1'b0;
-                    overflow_reg <= 1'b1;
-                end
-            end else begin
-                // store it
-                mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
-                wr_ptr_reg <= wr_ptr_reg + 1;
-                if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
-                    // end of frame or send frame
-                    send_frame_reg <= !s_axis_tlast;
-                    if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
-                        // bad packet, reset write pointer
-                        wr_ptr_reg <= wr_ptr_commit_reg;
-                        bad_frame_reg <= 1'b1;
-                    end else begin
-                        // good packet or packet overflow, update write pointer
-                        wr_ptr_commit_reg <= wr_ptr_reg + 1;
-                        good_frame_reg <= s_axis_tlast;
-                    end
-                end
-            end
-        end else if (s_axis_tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin
-            // data valid with packet overflow
-            // update write pointer
-            send_frame_reg <= 1'b1;
-            wr_ptr_commit_reg <= wr_ptr_reg;
-        end
-    end else begin
-        // normal FIFO mode
-        if (s_axis_tready && s_axis_tvalid) begin
-            if (drop_frame_reg && MARK_WHEN_FULL) begin
-                // currently dropping frame
-                if (s_axis_tlast) begin
-                    // end of frame
-                    if (!full && mark_frame_reg) begin
-                        // terminate marked frame
-                        mark_frame_reg <= 1'b0;
-                        mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
-                        wr_ptr_reg <= wr_ptr_reg + 1;
-                        wr_ptr_commit_reg <= wr_ptr_reg + 1;
-                    end
-                    // end of frame, clear drop flag
-                    drop_frame_reg <= 1'b0;
-                    overflow_reg <= 1'b1;
-                end
-            end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin
-                // full or marking frame
-                // drop frame; mark if this isn't the first cycle
-                drop_frame_reg <= 1'b1;
-                mark_frame_reg <= mark_frame_reg || s_frame_reg;
-                if (s_axis_tlast) begin
-                    drop_frame_reg <= 1'b0;
-                    overflow_reg <= 1'b1;
-                end
-            end else begin
-                // transfer in
-                mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
-                wr_ptr_reg <= wr_ptr_reg + 1;
-                wr_ptr_commit_reg <= wr_ptr_reg + 1;
-            end
-        end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin
-            // terminate marked frame
-            mark_frame_reg <= 1'b0;
-            mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
-            wr_ptr_reg <= wr_ptr_reg + 1;
-            wr_ptr_commit_reg <= wr_ptr_reg + 1;
-        end
-    end
-
-    if (rst) begin
-        wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
-        wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}};
-
-        s_frame_reg <= 1'b0;
-
-        drop_frame_reg <= 1'b0;
-        mark_frame_reg <= 1'b0;
-        send_frame_reg <= 1'b0;
-        overflow_reg <= 1'b0;
-        bad_frame_reg <= 1'b0;
-        good_frame_reg <= 1'b0;
-    end
-end
-
-// Status
-always @(posedge clk) begin
-    depth_reg <= wr_ptr_reg - rd_ptr_reg;
-    depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_reg;
-end
-
-// Read logic
-integer j;
-
-always @(posedge clk) begin
-    if (m_axis_tready_pipe) begin
-        // output ready; invalidate stage
-        m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
-    end
-
-    for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
-        if (m_axis_tready_pipe || ((~m_axis_tvalid_pipe_reg) >> j)) begin
-            // output ready or bubble in pipeline; transfer down pipeline
-            m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
-            m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
-            m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
-        end
-    end
-
-    if (m_axis_tready_pipe || ~m_axis_tvalid_pipe_reg) begin
-        // output ready or bubble in pipeline; read new data from FIFO
-        m_axis_tvalid_pipe_reg[0] <= 1'b0;
-        m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
-        if (!empty && pipe_ready) begin
-            // not empty, increment pointer
-            m_axis_tvalid_pipe_reg[0] <= 1'b1;
-            rd_ptr_reg <= rd_ptr_reg + 1;
-        end
-    end
-
-    if (rst) begin
-        rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
-        m_axis_tvalid_pipe_reg <= 0;
-    end
-end
-
-generate
-
-if (!OUTPUT_FIFO_ENABLE) begin
-
-    assign pipe_ready = 1'b1;
-
-    assign m_axis_tready_pipe = m_axis_tready_out;
-    assign m_axis_tvalid_out = m_axis_tvalid_pipe;
-
-    assign m_axis_tdata_out = m_axis_tdata_pipe;
-    assign m_axis_tkeep_out = m_axis_tkeep_pipe;
-    assign m_axis_tlast_out = m_axis_tlast_pipe;
-    assign m_axis_tid_out   = m_axis_tid_pipe;
-    assign m_axis_tdest_out = m_axis_tdest_pipe;
-    assign m_axis_tuser_out = m_axis_tuser_pipe;
-
-end else begin : output_fifo
-
-    // output datapath logic
-    reg [DATA_WIDTH-1:0] m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
-    reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
-    reg                  m_axis_tvalid_reg = 1'b0;
-    reg                  m_axis_tlast_reg  = 1'b0;
-    reg [ID_WIDTH-1:0]   m_axis_tid_reg    = {ID_WIDTH{1'b0}};
-    reg [DEST_WIDTH-1:0] m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
-    reg [USER_WIDTH-1:0] m_axis_tuser_reg  = {USER_WIDTH{1'b0}};
-
-    reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
-    reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
-    reg out_fifo_half_full_reg = 1'b0;
-
-    wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
-    wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
-
-    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg                  out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [ID_WIDTH-1:0]   out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
-    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
-
-    assign pipe_ready = !out_fifo_half_full_reg;
-
-    assign m_axis_tready_pipe = 1'b1;
-
-    assign m_axis_tdata_out  = m_axis_tdata_reg;
-    assign m_axis_tkeep_out  = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
-    assign m_axis_tvalid_out = m_axis_tvalid_reg;
-    assign m_axis_tlast_out  = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
-    assign m_axis_tid_out    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
-    assign m_axis_tdest_out  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
-    assign m_axis_tuser_out  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
-
-    always @(posedge clk) begin
-        m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out;
-
-        out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
-
-        if (!out_fifo_full && m_axis_tvalid_pipe) begin
-            out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe;
-            out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe;
-            out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe;
-            out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe;
-            out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe;
-            out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe;
-            out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
-        end
-
-        if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin
-            m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
-            m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
-            m_axis_tvalid_reg <= 1'b1;
-            m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
-            m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
-            m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
-            m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
-            out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
-        end
-
-        if (rst) begin
-            out_fifo_wr_ptr_reg <= 0;
-            out_fifo_rd_ptr_reg <= 0;
-            m_axis_tvalid_reg <= 1'b0;
-        end
-    end
-
-end
-
-if (PAUSE_ENABLE) begin : pause
-
-    // Pause logic
-    reg pause_reg = 1'b0;
-    reg pause_frame_reg = 1'b0;
-
-    assign m_axis_tready_out = m_axis_tready && !pause_reg;
-    assign m_axis_tvalid = m_axis_tvalid_out && !pause_reg;
-
-    assign m_axis_tdata = m_axis_tdata_out;
-    assign m_axis_tkeep = m_axis_tkeep_out;
-    assign m_axis_tlast = m_axis_tlast_out;
-    assign m_axis_tid   = m_axis_tid_out;
-    assign m_axis_tdest = m_axis_tdest_out;
-    assign m_axis_tuser = m_axis_tuser_out;
-
-    assign pause_ack = pause_reg;
-
-    always @(posedge clk) begin
-        if (FRAME_PAUSE) begin
-            if (m_axis_tvalid && m_axis_tready) begin
-                if (m_axis_tlast) begin
-                    pause_frame_reg <= 1'b0;
-                    pause_reg <= pause_req;
-                end else begin
-                    pause_frame_reg <= 1'b1;
-                end
-            end else begin
-                if (!pause_frame_reg) begin
-                    pause_reg <= pause_req;
-                end
-            end
-        end else begin
-            pause_reg <= pause_req;
-        end
-
-        if (rst) begin
-            pause_frame_reg <= 1'b0;
-            pause_reg <= 1'b0;
-        end
-    end
-
-end else begin
-
-    assign m_axis_tready_out = m_axis_tready;
-    assign m_axis_tvalid = m_axis_tvalid_out;
-
-    assign m_axis_tdata = m_axis_tdata_out;
-    assign m_axis_tkeep = m_axis_tkeep_out;
-    assign m_axis_tlast = m_axis_tlast_out;
-    assign m_axis_tid   = m_axis_tid_out;
-    assign m_axis_tdest = m_axis_tdest_out;
-    assign m_axis_tuser = m_axis_tuser_out;
-
-    assign pause_ack = 1'b0;
-
-end
-
-endgenerate
-
-endmodule
-
-`resetall

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/common

@@ -1 +0,0 @@
-../../../../common/rtl/

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/sync_signal.v

@@ -1,62 +0,0 @@
-/*
-
-Copyright (c) 2014-2018 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog-2001
-
-`resetall
-`timescale 1 ns / 1 ps
-`default_nettype none
-
-/*
- * Synchronizes an asyncronous signal to a given clock by using a pipeline of
- * two registers.
- */
-module sync_signal #(
-    parameter WIDTH=1, // width of the input and output signals
-    parameter N=2 // depth of synchronizer
-)(
-    input wire clk,
-    input wire [WIDTH-1:0] in,
-    output wire [WIDTH-1:0] out
-);
-
-reg [WIDTH-1:0] sync_reg[N-1:0];
-
-/*
- * The synchronized output is the last register in the pipeline.
- */
-assign out = sync_reg[N-1];
-
-integer k;
-
-always @(posedge clk) begin
-    sync_reg[0] <= in;
-    for (k = 1; k < N; k = k + 1) begin
-        sync_reg[k] <= sync_reg[k-1];
-    end
-end
-
-endmodule
-
-`resetall

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/xcvr_ctrl.v

@@ -1,268 +0,0 @@
-/*
-
-Copyright (c) 2021 Alex Forencich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
-
-*/
-
-// Language: Verilog 2001
-
-`resetall
-`timescale 1ns / 1ps
-`default_nettype none
-
-/*
- * Transceiver control
- */
-module xcvr_ctrl (
-    input  wire        reconfig_clk,
-    input  wire        reconfig_rst,
-
-    input  wire        pll_locked_in,
-
-    output wire [18:0] xcvr_reconfig_address,
-    output wire        xcvr_reconfig_read,
-    output wire        xcvr_reconfig_write,
-    input  wire [7:0]  xcvr_reconfig_readdata,
-    output wire [7:0]  xcvr_reconfig_writedata,
-    input  wire        xcvr_reconfig_waitrequest
-);
-
-localparam [3:0]
-    STATE_IDLE = 4'd0,
-    STATE_LOAD_PMA_1 = 4'd1,
-    STATE_LOAD_PMA_2 = 4'd2,
-    STATE_INIT_ADAPT_1 = 4'd3,
-    STATE_INIT_ADAPT_2 = 4'd4,
-    STATE_INIT_ADAPT_3 = 4'd5,
-    STATE_INIT_ADAPT_4 = 4'd6,
-    STATE_CONT_ADAPT_1 = 4'd7,
-    STATE_CONT_ADAPT_2 = 4'd8,
-    STATE_CONT_ADAPT_3 = 4'd9,
-    STATE_CONT_ADAPT_4 = 4'd10,
-    STATE_DONE = 4'd11;
-
-reg [3:0] state_reg = STATE_IDLE, state_next;
-
-reg [18:0] xcvr_reconfig_address_reg = 19'd0, xcvr_reconfig_address_next;
-reg xcvr_reconfig_read_reg = 1'b0, xcvr_reconfig_read_next;
-reg xcvr_reconfig_write_reg = 1'b0, xcvr_reconfig_write_next;
-reg [7:0] xcvr_reconfig_writedata_reg = 8'd0, xcvr_reconfig_writedata_next;
-
-reg [7:0] read_data_reg = 8'd0, read_data_next;
-reg read_data_valid_reg = 1'b0, read_data_valid_next;
-
-reg [15:0] delay_count_reg = 0, delay_count_next;
-
-reg pll_locked_sync_1_reg = 0;
-reg pll_locked_sync_2_reg = 0;
-reg pll_locked_sync_3_reg = 0;
-
-assign xcvr_reconfig_address = xcvr_reconfig_address_reg;
-assign xcvr_reconfig_read = xcvr_reconfig_read_reg;
-assign xcvr_reconfig_write = xcvr_reconfig_write_reg;
-assign xcvr_reconfig_writedata = xcvr_reconfig_writedata_reg;
-
-always @(posedge reconfig_clk) begin
-    pll_locked_sync_1_reg <= pll_locked_in;
-    pll_locked_sync_2_reg <= pll_locked_sync_1_reg;
-    pll_locked_sync_3_reg <= pll_locked_sync_2_reg;
-end
-
-always @* begin
-    state_next = STATE_IDLE;
-
-    xcvr_reconfig_address_next = xcvr_reconfig_address_reg;
-    xcvr_reconfig_read_next = 1'b0;
-    xcvr_reconfig_write_next = 1'b0;
-    xcvr_reconfig_writedata_next = xcvr_reconfig_writedata_reg;
-
-    read_data_next = read_data_reg;
-    read_data_valid_next = read_data_valid_reg;
-
-    delay_count_next = delay_count_reg;
-
-    if (xcvr_reconfig_read_reg || xcvr_reconfig_write_reg) begin
-        // operation in progress
-        if (xcvr_reconfig_waitrequest) begin
-            // wait state, hold command
-            xcvr_reconfig_read_next = xcvr_reconfig_read_reg;
-            xcvr_reconfig_write_next = xcvr_reconfig_write_reg;
-        end else begin
-            // release command
-            xcvr_reconfig_read_next = 1'b0;
-            xcvr_reconfig_write_next = 1'b0;
-
-            if (xcvr_reconfig_read_reg) begin
-                // latch read data
-                read_data_next = xcvr_reconfig_readdata;
-                read_data_valid_next = 1'b1;
-            end
-        end
-        state_next = state_reg;
-    end else if (delay_count_reg != 0) begin
-        // stall for delay
-        delay_count_next = delay_count_reg - 1;
-        state_next = state_reg;
-    end else begin
-        read_data_valid_next = 1'b0;
-
-        case (state_reg)
-            STATE_IDLE: begin
-                // wait for PLL to lock
-                if (pll_locked_sync_3_reg) begin
-                    delay_count_next = 16'hffff;
-                    state_next = STATE_LOAD_PMA_1;
-                end else begin
-                    state_next = STATE_IDLE;
-                end
-            end
-            STATE_LOAD_PMA_1: begin
-                // load PMA config
-                xcvr_reconfig_address_next = 19'h40143;
-                xcvr_reconfig_writedata_next = 8'h80;
-                xcvr_reconfig_write_next = 1'b1;
-                state_next = STATE_LOAD_PMA_2;
-            end
-            STATE_LOAD_PMA_2: begin
-                // check status
-                if (read_data_valid_reg && read_data_reg[0]) begin
-                    // start initial adaptation
-                    xcvr_reconfig_address_next = 19'h200;
-                    xcvr_reconfig_writedata_next = 8'hD2;
-                    xcvr_reconfig_write_next = 1'b1;
-                    state_next = STATE_INIT_ADAPT_1;
-                end else begin
-                    // read status
-                    xcvr_reconfig_address_next = 19'h40144;
-                    xcvr_reconfig_read_next = 1'b1;
-                    state_next = STATE_LOAD_PMA_2;
-                end
-            end
-            STATE_INIT_ADAPT_1: begin
-                // start initial adaptation
-                xcvr_reconfig_address_next = 19'h201;
-                xcvr_reconfig_writedata_next = 8'h02;
-                xcvr_reconfig_write_next = 1'b1;
-                state_next = STATE_INIT_ADAPT_2;
-            end
-            STATE_INIT_ADAPT_2: begin
-                // start initial adaptation
-                xcvr_reconfig_address_next = 19'h202;
-                xcvr_reconfig_writedata_next = 8'h01;
-                xcvr_reconfig_write_next = 1'b1;
-                state_next = STATE_INIT_ADAPT_3;
-            end
-            STATE_INIT_ADAPT_3: begin
-                // start initial adaptation
-                xcvr_reconfig_address_next = 19'h203;
-                xcvr_reconfig_writedata_next = 8'h96;
-                xcvr_reconfig_write_next = 1'b1;
-                state_next = STATE_INIT_ADAPT_4;
-            end
-            STATE_INIT_ADAPT_4: begin
-                // check status
-                if (read_data_valid_reg && read_data_reg == 8'h80) begin
-                    // start continuous adaptation
-                    xcvr_reconfig_address_next = 19'h200;
-                    xcvr_reconfig_writedata_next = 8'hF6;
-                    xcvr_reconfig_write_next = 1'b1;
-                    state_next = STATE_CONT_ADAPT_1;
-                end else begin
-                    // read status
-                    xcvr_reconfig_address_next = 19'h207;
-                    xcvr_reconfig_read_next = 1'b1;
-                    state_next = STATE_INIT_ADAPT_4;
-                end
-            end
-            STATE_CONT_ADAPT_1: begin
-                // start continuous adaptation
-                xcvr_reconfig_address_next = 19'h201;
-                xcvr_reconfig_writedata_next = 8'h01;
-                xcvr_reconfig_write_next = 1'b1;
-                state_next = STATE_CONT_ADAPT_2;
-            end
-            STATE_CONT_ADAPT_2: begin
-                // start continuous adaptation
-                xcvr_reconfig_address_next = 19'h202;
-                xcvr_reconfig_writedata_next = 8'h03;
-                xcvr_reconfig_write_next = 1'b1;
-                state_next = STATE_CONT_ADAPT_3;
-            end
-            STATE_CONT_ADAPT_3: begin
-                // start continuous adaptation
-                xcvr_reconfig_address_next = 19'h203;
-                xcvr_reconfig_writedata_next = 8'h96;
-                xcvr_reconfig_write_next = 1'b1;
-                state_next = STATE_CONT_ADAPT_4;
-            end
-            STATE_CONT_ADAPT_4: begin
-                // check status
-                if (read_data_valid_reg && read_data_reg == 8'h80) begin
-                    // done
-                    state_next = STATE_DONE;
-                end else begin
-                    // read status
-                    xcvr_reconfig_address_next = 19'h207;
-                    xcvr_reconfig_read_next = 1'b1;
-                    state_next = STATE_CONT_ADAPT_4;
-                end
-            end
-            STATE_DONE: begin
-                // done with operation
-                state_next = STATE_DONE;
-            end
-        endcase
-    end
-
-    if (!pll_locked_sync_3_reg) begin
-        // go back to idle if PLL is unlocked
-        state_next = STATE_IDLE;
-    end
-end
-
-always @(posedge reconfig_clk) begin
-    state_reg <= state_next;
-
-    xcvr_reconfig_address_reg <= xcvr_reconfig_address_next;
-    xcvr_reconfig_read_reg <= xcvr_reconfig_read_next;
-    xcvr_reconfig_write_reg <= xcvr_reconfig_write_next;
-    xcvr_reconfig_writedata_reg <= xcvr_reconfig_writedata_next;
-
-    read_data_reg <= read_data_next;
-    read_data_valid_reg <= read_data_valid_next;
-
-    delay_count_reg <= delay_count_next;
-
-    if (reconfig_rst) begin
-        state_reg <= STATE_IDLE;
-
-        xcvr_reconfig_read_reg <= 1'b0;
-        xcvr_reconfig_write_reg <= 1'b0;
-
-        read_data_valid_reg <= 1'b0;
-
-        delay_count_reg <= 0;
-    end
-end
-
-endmodule
-
-`resetall

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile

@@ -1,260 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause-Views
-# Copyright (c) 2020-2023 The Regents of the University of California
-
-TOPLEVEL_LANG = verilog
-
-SIM ?= icarus
-WAVES ?= 0
-
-COCOTB_HDL_TIMEUNIT = 1ns
-COCOTB_HDL_TIMEPRECISION = 1ps
-
-DUT      = fpga_core
-TOPLEVEL = $(DUT)
-MODULE   = test_$(DUT)
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
-VERILOG_SOURCES += ../../rtl/common/cpl_write.v
-VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
-VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
-VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
-VERILOG_SOURCES += ../../rtl/common/queue_manager.v
-VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
-VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
-VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
-VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
-VERILOG_SOURCES += ../../rtl/common/tx_engine.v
-VERILOG_SOURCES += ../../rtl/common/rx_engine.v
-VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
-VERILOG_SOURCES += ../../rtl/common/rx_hash.v
-VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
-VERILOG_SOURCES += ../../rtl/common/stats_counter.v
-VERILOG_SOURCES += ../../rtl/common/stats_collect.v
-VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
-VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
-VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
-VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
-VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
-VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
-VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
-VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
-VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v
-VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
-VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
-VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
-VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
-VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
-VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
-VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
-VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
-VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
-VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
-VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fc_count.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_rx.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_tx.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_cfg.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_fc_counter.v
-VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
-
-# module parameters
-
-# Structural configuration
-export PARAM_IF_COUNT := 2
-export PARAM_PORTS_PER_IF := 1
-export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF)
-export PARAM_PORT_MASK := 0
-
-# Clock configuration
-export PARAM_CLK_PERIOD_NS_NUM := 4
-export PARAM_CLK_PERIOD_NS_DENOM := 1
-
-# PTP configuration
-export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048
-export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825
-export PARAM_PTP_CLOCK_PIPELINE := 0
-export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
-export PARAM_PTP_SEPARATE_TX_CLOCK := 0
-export PARAM_PTP_SEPARATE_RX_CLOCK := 0
-export PARAM_PTP_PORT_CDC_PIPELINE := 0
-export PARAM_PTP_PEROUT_ENABLE := 1
-export PARAM_PTP_PEROUT_COUNT := 1
-
-# Queue manager configuration
-export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
-export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
-export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
-export PARAM_CQ_OP_TABLE_SIZE := 32
-export PARAM_EQN_WIDTH := 6
-export PARAM_TX_QUEUE_INDEX_WIDTH := 13
-export PARAM_RX_QUEUE_INDEX_WIDTH := 8
-export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
-export PARAM_EQ_PIPELINE := 3
-export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
-export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
-export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
-
-# TX and RX engine configuration
-export PARAM_TX_DESC_TABLE_SIZE := 32
-export PARAM_RX_DESC_TABLE_SIZE := 32
-export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
-
-# Scheduler configuration
-export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
-export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
-export PARAM_TDMA_INDEX_WIDTH := 6
-
-# Interface configuration
-export PARAM_PTP_TS_ENABLE := 1
-export PARAM_TX_CPL_FIFO_DEPTH := 32
-export PARAM_TX_CHECKSUM_ENABLE := 1
-export PARAM_RX_HASH_ENABLE := 1
-export PARAM_RX_CHECKSUM_ENABLE := 1
-export PARAM_LFC_ENABLE := 1
-export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
-export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
-export PARAM_MAX_TX_SIZE := 9214
-export PARAM_MAX_RX_SIZE := 9214
-export PARAM_TX_RAM_SIZE := 32768
-export PARAM_RX_RAM_SIZE := 32768
-
-# Application block configuration
-export PARAM_APP_ID := $(shell echo $$((0x00000000)) )
-export PARAM_APP_ENABLE := 0
-export PARAM_APP_CTRL_ENABLE := 1
-export PARAM_APP_DMA_ENABLE := 1
-export PARAM_APP_AXIS_DIRECT_ENABLE := 1
-export PARAM_APP_AXIS_SYNC_ENABLE := 1
-export PARAM_APP_AXIS_IF_ENABLE := 1
-export PARAM_APP_STAT_ENABLE := 1
-
-# DMA interface configuration
-export PARAM_DMA_IMM_ENABLE := 0
-export PARAM_DMA_IMM_WIDTH := 32
-export PARAM_DMA_LEN_WIDTH := 16
-export PARAM_DMA_TAG_WIDTH := 16
-export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
-export PARAM_RAM_PIPELINE := 2
-
-# PCIe interface configuration
-export PARAM_SEG_COUNT := 2
-export PARAM_SEG_DATA_WIDTH := 256
-export PARAM_PF_COUNT := 1
-export PARAM_VF_COUNT := 0
-
-# Interrupt configuration
-export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
-
-# AXI lite interface configuration (control)
-export PARAM_AXIL_CTRL_DATA_WIDTH := 32
-export PARAM_AXIL_CTRL_ADDR_WIDTH := 24
-
-# AXI lite interface configuration (application control)
-export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH)
-export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24
-
-# Ethernet interface configuration
-export PARAM_AXIS_ETH_TX_PIPELINE := 0
-export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2
-export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0
-export PARAM_AXIS_ETH_RX_PIPELINE := 0
-export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2
-
-# Statistics counter subsystem
-export PARAM_STAT_ENABLE := 1
-export PARAM_STAT_DMA_ENABLE := 1
-export PARAM_STAT_PCIE_ENABLE := 1
-export PARAM_STAT_INC_WIDTH := 24
-export PARAM_STAT_ID_WIDTH := 12
-
-ifeq ($(SIM), icarus)
-	PLUSARGS += -fst
-
-	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
-
-	ifeq ($(WAVES), 1)
-		VERILOG_SOURCES += iverilog_dump.v
-		COMPILE_ARGS += -s iverilog_dump
-	endif
-else ifeq ($(SIM), verilator)
-	COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
-
-	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
-
-	ifeq ($(WAVES), 1)
-		COMPILE_ARGS += --trace-fst
-	endif
-endif
-
-include $(shell cocotb-config --makefiles)/Makefile.sim
-
-iverilog_dump.v:
-	echo 'module iverilog_dump();' > $@
-	echo 'initial begin' >> $@
-	echo '    $$dumpfile("$(TOPLEVEL).fst");' >> $@
-	echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
-	echo 'end' >> $@
-	echo 'endmodule' >> $@
-
-clean::
-	@rm -rf iverilog_dump.v
-	@rm -rf dump.fst $(TOPLEVEL).fst

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/mqnic.py

@@ -1 +0,0 @@
-../../../../../common/tb/mqnic.py

fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py

@@ -1,764 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause-Views
-# Copyright (c) 2020-2023 The Regents of the University of California
-
-import logging
-import os
-import sys
-
-import scapy.utils
-from scapy.layers.l2 import Ether
-from scapy.layers.inet import IP, UDP
-
-import cocotb_test.simulator
-
-import cocotb
-from cocotb.log import SimLog
-from cocotb.clock import Clock
-from cocotb.triggers import RisingEdge, FallingEdge, Timer
-
-from cocotbext.axi import AxiStreamBus
-from cocotbext.eth import EthMac
-from cocotbext.pcie.core import RootComplex
-from cocotbext.pcie.intel.ptile import PTilePcieDevice, PTileRxBus, PTileTxBus
-
-try:
-    import mqnic
-except ImportError:
-    # attempt import from current directory
-    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
-    try:
-        import mqnic
-    finally:
-        del sys.path[0]
-
-
-class TB(object):
-    def __init__(self, dut, msix_count=32):
-        self.dut = dut
-
-        self.log = SimLog("cocotb.tb")
-        self.log.setLevel(logging.DEBUG)
-
-        # PCIe
-        self.rc = RootComplex()
-
-        self.rc.max_payload_size = 0x1  # 256 bytes
-        self.rc.max_read_request_size = 0x2  # 512 bytes
-
-        self.dev = PTilePcieDevice(
-            # configuration options
-            pcie_generation=3,
-            pcie_link_width=16,
-            pld_clk_frequency=250e6,
-            pf_count=1,
-            max_payload_size=512,
-            enable_extended_tag=True,
-
-            pf0_msi_enable=False,
-            pf0_msi_count=1,
-            pf1_msi_enable=False,
-            pf1_msi_count=1,
-            pf2_msi_enable=False,
-            pf2_msi_count=1,
-            pf3_msi_enable=False,
-            pf3_msi_count=1,
-            pf0_msix_enable=True,
-            pf0_msix_table_size=msix_count-1,
-            pf0_msix_table_bir=0,
-            pf0_msix_table_offset=0x00010000,
-            pf0_msix_pba_bir=0,
-            pf0_msix_pba_offset=0x00018000,
-            pf1_msix_enable=False,
-            pf1_msix_table_size=0,
-            pf1_msix_table_bir=0,
-            pf1_msix_table_offset=0x00000000,
-            pf1_msix_pba_bir=0,
-            pf1_msix_pba_offset=0x00000000,
-            pf2_msix_enable=False,
-            pf2_msix_table_size=0,
-            pf2_msix_table_bir=0,
-            pf2_msix_table_offset=0x00000000,
-            pf2_msix_pba_bir=0,
-            pf2_msix_pba_offset=0x00000000,
-            pf3_msix_enable=False,
-            pf3_msix_table_size=0,
-            pf3_msix_table_bir=0,
-            pf3_msix_table_offset=0x00000000,
-            pf3_msix_pba_bir=0,
-            pf3_msix_pba_offset=0x00000000,
-
-            # signals
-            # Clock and reset
-            reset_status=dut.rst_250mhz,
-            # reset_status_n=dut.reset_status_n,
-            coreclkout_hip=dut.clk_250mhz,
-            # refclk0=dut.refclk0,
-            # refclk1=dut.refclk1,
-            # pin_perst_n=dut.pin_perst_n,
-
-            # RX interface
-            rx_bus=PTileRxBus.from_prefix(dut, "rx_st"),
-            # rx_par_err=dut.rx_par_err,
-
-            # TX interface
-            tx_bus=PTileTxBus.from_prefix(dut, "tx_st"),
-            # tx_par_err=dut.tx_par_err,
-
-            # RX flow control
-            rx_buffer_limit=dut.rx_buffer_limit,
-            rx_buffer_limit_tdm_idx=dut.rx_buffer_limit_tdm_idx,
-
-            # TX flow control
-            tx_cdts_limit=dut.tx_cdts_limit,
-            tx_cdts_limit_tdm_idx=dut.tx_cdts_limit_tdm_idx,
-
-            # Power management and hard IP status interface
-            # link_up=dut.link_up,
-            # dl_up=dut.dl_up,
-            # surprise_down_err=dut.surprise_down_err,
-            # ltssm_state=dut.ltssm_state,
-            # pm_state=dut.pm_state,
-            # pm_dstate=dut.pm_dstate,
-            # apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
-            # app_req_retry_en=dut.app_req_retry_en,
-
-            # Interrupt interface
-            # app_int=dut.app_int,
-            # msi_pnd_func=dut.msi_pnd_func,
-            # msi_pnd_byte=dut.msi_pnd_byte,
-            # msi_pnd_addr=dut.msi_pnd_addr,
-
-            # Error interface
-            # serr_out=dut.serr_out,
-            # hip_enter_err_mode=dut.hip_enter_err_mode,
-            # app_err_valid=dut.app_err_valid,
-            # app_err_hdr=dut.app_err_hdr,
-            # app_err_info=dut.app_err_info,
-            # app_err_func_num=dut.app_err_func_num,
-
-            # Completion timeout interface
-            # cpl_timeout=dut.cpl_timeout,
-            # cpl_timeout_avmm_clk=dut.cpl_timeout_avmm_clk,
-            # cpl_timeout_avmm_address=dut.cpl_timeout_avmm_address,
-            # cpl_timeout_avmm_read=dut.cpl_timeout_avmm_read,
-            # cpl_timeout_avmm_readdata=dut.cpl_timeout_avmm_readdata,
-            # cpl_timeout_avmm_readdatavalid=dut.cpl_timeout_avmm_readdatavalid,
-            # cpl_timeout_avmm_write=dut.cpl_timeout_avmm_write,
-            # cpl_timeout_avmm_writedata=dut.cpl_timeout_avmm_writedata,
-            # cpl_timeout_avmm_waitrequest=dut.cpl_timeout_avmm_waitrequest,
-
-            # Configuration output
-            tl_cfg_func=dut.tl_cfg_func,
-            tl_cfg_add=dut.tl_cfg_add,
-            tl_cfg_ctl=dut.tl_cfg_ctl,
-            # dl_timer_update=dut.dl_timer_update,
-
-            # Configuration intercept interface
-            # cii_req=dut.cii_req,
-            # cii_hdr_poisoned=dut.cii_hdr_poisoned,
-            # cii_hdr_first_be=dut.cii_hdr_first_be,
-            # cii_func_num=dut.cii_func_num,
-            # cii_wr_vf_active=dut.cii_wr_vf_active,
-            # cii_vf_num=dut.cii_vf_num,
-            # cii_wr=dut.cii_wr,
-            # cii_addr=dut.cii_addr,
-            # cii_dout=dut.cii_dout,
-            # cii_override_en=dut.cii_override_en,
-            # cii_override_din=dut.cii_override_din,
-            # cii_halt=dut.cii_halt,
-
-            # Hard IP reconfiguration interface
-            # hip_reconfig_clk=dut.hip_reconfig_clk,
-            # hip_reconfig_address=dut.hip_reconfig_address,
-            # hip_reconfig_read=dut.hip_reconfig_read,
-            # hip_reconfig_readdata=dut.hip_reconfig_readdata,
-            # hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
-            # hip_reconfig_write=dut.hip_reconfig_write,
-            # hip_reconfig_writedata=dut.hip_reconfig_writedata,
-            # hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
-
-            # Page request service
-            # prs_event_valid=dut.prs_event_valid,
-            # prs_event_func=dut.prs_event_func,
-            # prs_event=dut.prs_event,
-
-            # SR-IOV (VF error)
-            # vf_err_ur_posted_s0=dut.vf_err_ur_posted_s0,
-            # vf_err_ur_posted_s1=dut.vf_err_ur_posted_s1,
-            # vf_err_ur_posted_s2=dut.vf_err_ur_posted_s2,
-            # vf_err_ur_posted_s3=dut.vf_err_ur_posted_s3,
-            # vf_err_func_num_s0=dut.vf_err_func_num_s0,
-            # vf_err_func_num_s1=dut.vf_err_func_num_s1,
-            # vf_err_func_num_s2=dut.vf_err_func_num_s2,
-            # vf_err_func_num_s3=dut.vf_err_func_num_s3,
-            # vf_err_ca_postedreq_s0=dut.vf_err_ca_postedreq_s0,
-            # vf_err_ca_postedreq_s1=dut.vf_err_ca_postedreq_s1,
-            # vf_err_ca_postedreq_s2=dut.vf_err_ca_postedreq_s2,
-            # vf_err_ca_postedreq_s3=dut.vf_err_ca_postedreq_s3,
-            # vf_err_vf_num_s0=dut.vf_err_vf_num_s0,
-            # vf_err_vf_num_s1=dut.vf_err_vf_num_s1,
-            # vf_err_vf_num_s2=dut.vf_err_vf_num_s2,
-            # vf_err_vf_num_s3=dut.vf_err_vf_num_s3,
-            # vf_err_poisonedwrreq_s0=dut.vf_err_poisonedwrreq_s0,
-            # vf_err_poisonedwrreq_s1=dut.vf_err_poisonedwrreq_s1,
-            # vf_err_poisonedwrreq_s2=dut.vf_err_poisonedwrreq_s2,
-            # vf_err_poisonedwrreq_s3=dut.vf_err_poisonedwrreq_s3,
-            # vf_err_poisonedcompl_s0=dut.vf_err_poisonedcompl_s0,
-            # vf_err_poisonedcompl_s1=dut.vf_err_poisonedcompl_s1,
-            # vf_err_poisonedcompl_s2=dut.vf_err_poisonedcompl_s2,
-            # vf_err_poisonedcompl_s3=dut.vf_err_poisonedcompl_s3,
-            # user_vfnonfatalmsg_func_num=dut.user_vfnonfatalmsg_func_num,
-            # user_vfnonfatalmsg_vfnum=dut.user_vfnonfatalmsg_vfnum,
-            # user_sent_vfnonfatalmsg=dut.user_sent_vfnonfatalmsg,
-            # vf_err_overflow=dut.vf_err_overflow,
-
-            # FLR
-            # flr_rcvd_pf=dut.flr_rcvd_pf,
-            # flr_rcvd_vf=dut.flr_rcvd_vf,
-            # flr_rcvd_pf_num=dut.flr_rcvd_pf_num,
-            # flr_rcvd_vf_num=dut.flr_rcvd_vf_num,
-            # flr_completed_pf=dut.flr_completed_pf,
-            # flr_completed_vf=dut.flr_completed_vf,
-            # flr_completed_pf_num=dut.flr_completed_pf_num,
-            # flr_completed_vf_num=dut.flr_completed_vf_num,
-
-            # VirtIO
-            # virtio_pcicfg_vfaccess=dut.virtio_pcicfg_vfaccess,
-            # virtio_pcicfg_vfnum=dut.virtio_pcicfg_vfnum,
-            # virtio_pcicfg_pfnum=dut.virtio_pcicfg_pfnum,
-            # virtio_pcicfg_bar=dut.virtio_pcicfg_bar,
-            # virtio_pcicfg_length=dut.virtio_pcicfg_length,
-            # virtio_pcicfg_baroffset=dut.virtio_pcicfg_baroffset,
-            # virtio_pcicfg_cfgdata=dut.virtio_pcicfg_cfgdata,
-            # virtio_pcicfg_cfgwr=dut.virtio_pcicfg_cfgwr,
-            # virtio_pcicfg_cfgrd=dut.virtio_pcicfg_cfgrd,
-            # virtio_pcicfg_appvfnum=dut.virtio_pcicfg_appvfnum,
-            # virtio_pcicfg_apppfnum=dut.virtio_pcicfg_apppfnum,
-            # virtio_pcicfg_rdack=dut.virtio_pcicfg_rdack,
-            # virtio_pcicfg_rdbe=dut.virtio_pcicfg_rdbe,
-            # virtio_pcicfg_data=dut.virtio_pcicfg_data,
-        )
-
-        # self.dev.log.setLevel(logging.DEBUG)
-
-        self.rc.make_port().connect(self.dev)
-
-        self.driver = mqnic.Driver()
-
-        self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
-        if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
-            self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
-
-        cocotb.start_soon(Clock(dut.ptp_clk, 2.482, units="ns").start())
-        dut.ptp_rst.setimmediatevalue(0)
-        cocotb.start_soon(Clock(dut.ptp_sample_clk, 10, units="ns").start())
-
-        # Ethernet
-        self.qsfpdd_mac = []
-
-        for x in range(2):
-            macs = []
-            for y in range(1, 9):
-                cocotb.start_soon(Clock(getattr(dut, f"qsfpdd{x}_mac_{y}_rx_clk"), 2.482, units="ns").start())
-                cocotb.start_soon(Clock(getattr(dut, f"qsfpdd{x}_mac_{y}_tx_clk"), 2.482, units="ns").start())
-
-                mac = EthMac(
-                    tx_clk=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_clk"),
-                    tx_rst=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_rst"),
-                    tx_bus=AxiStreamBus.from_prefix(dut, f"qsfpdd{x}_mac_{y}_tx_axis"),
-                    tx_ptp_time=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_time"),
-                    tx_ptp_ts=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts"),
-                    tx_ptp_ts_tag=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts_tag"),
-                    tx_ptp_ts_valid=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts_valid"),
-                    rx_clk=getattr(dut, f"qsfpdd{x}_mac_{y}_rx_clk"),
-                    rx_rst=getattr(dut, f"qsfpdd{x}_mac_{y}_rx_rst"),
-                    rx_bus=AxiStreamBus.from_prefix(dut, f"qsfpdd{x}_mac_{y}_rx_axis"),
-                    rx_ptp_time=getattr(dut, f"qsfpdd{x}_mac_{y}_rx_ptp_time"),
-                    ifg=12, speed=25e9
-                )
-
-                macs.append(mac)
-
-                getattr(dut, f"qsfpdd{x}_mac_{y}_rx_status").setimmediatevalue(1)
-                getattr(dut, f"qsfpdd{x}_mac_{y}_rx_lfc_req").setimmediatevalue(0)
-                getattr(dut, f"qsfpdd{x}_mac_{y}_rx_pfc_req").setimmediatevalue(0)
-
-            self.qsfpdd_mac.append(macs)
-
-            getattr(dut, f"qsfpdd{x}_modprs_l").setimmediatevalue(0)
-            getattr(dut, f"qsfpdd{x}_int_l").setimmediatevalue(1)
-
-        dut.fpga_i2c_scl_i.setimmediatevalue(1)
-        dut.fpga_i2c_sda_i.setimmediatevalue(1)
-
-        dut.qsfpdd_i2c_scl_i.setimmediatevalue(1)
-        dut.qsfpdd_i2c_sda_i.setimmediatevalue(1)
-
-        self.loopback_enable = False
-        cocotb.start_soon(self._run_loopback())
-
-    async def init(self):
-
-        self.dut.ptp_rst.setimmediatevalue(0)
-        for x in range(2):
-            for y in range(1, 9):
-                getattr(self.dut, f"qsfpdd{x}_mac_{y}_rx_rst").setimmediatevalue(0)
-                getattr(self.dut, f"qsfpdd{x}_mac_{y}_tx_rst").setimmediatevalue(0)
-
-        await RisingEdge(self.dut.clk_250mhz)
-        await RisingEdge(self.dut.clk_250mhz)
-
-        self.dut.ptp_rst.setimmediatevalue(1)
-        for x in range(2):
-            for y in range(1, 9):
-                getattr(self.dut, f"qsfpdd{x}_mac_{y}_rx_rst").setimmediatevalue(1)
-                getattr(self.dut, f"qsfpdd{x}_mac_{y}_tx_rst").setimmediatevalue(1)
-
-        await FallingEdge(self.dut.rst_250mhz)
-        await Timer(100, 'ns')
-
-        await RisingEdge(self.dut.clk_250mhz)
-        await RisingEdge(self.dut.clk_250mhz)
-
-        self.dut.ptp_rst.setimmediatevalue(0)
-        for x in range(2):
-            for y in range(1, 9):
-                getattr(self.dut, f"qsfpdd{x}_mac_{y}_rx_rst").setimmediatevalue(0)
-                getattr(self.dut, f"qsfpdd{x}_mac_{y}_tx_rst").setimmediatevalue(0)
-
-        await self.rc.enumerate()
-
-    async def _run_loopback(self):
-        while True:
-            await RisingEdge(self.dut.clk_250mhz)
-
-            if self.loopback_enable:
-                for macs in self.qsfpdd_mac:
-                    for mac in macs:
-                        if not mac.tx.empty():
-                            await mac.rx.send(await mac.tx.recv())
-
-
-@cocotb.test()
-async def run_test_nic(dut):
-
-    tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
-
-    await tb.init()
-
-    tb.log.info("Init driver")
-    await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
-    await tb.driver.interfaces[0].open()
-    # await tb.driver.interfaces[1].open()
-
-    # enable queues
-    tb.log.info("Enable queues")
-    await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
-    for k in range(len(tb.driver.interfaces[0].txq)):
-        await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
-
-    # wait for all writes to complete
-    await tb.driver.hw_regs.read_dword(0)
-    tb.log.info("Init complete")
-
-    tb.log.info("Send and receive single packet")
-
-    data = bytearray([x % 256 for x in range(1024)])
-
-    await tb.driver.interfaces[0].start_xmit(data, 0)
-
-    pkt = await tb.qsfpdd_mac[0][0].tx.recv()
-    tb.log.info("Packet: %s", pkt)
-
-    await tb.qsfpdd_mac[0][0].rx.send(pkt)
-
-    pkt = await tb.driver.interfaces[0].recv()
-
-    tb.log.info("Packet: %s", pkt)
-    assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
-
-    # await tb.driver.interfaces[1].start_xmit(data, 0)
-
-    # pkt = await tb.qsfpdd_mac[1][0].tx.recv()
-    # tb.log.info("Packet: %s", pkt)
-
-    # await tb.qsfpdd_mac[1][0].rx.send(pkt)
-
-    # pkt = await tb.driver.interfaces[1].recv()
-
-    # tb.log.info("Packet: %s", pkt)
-    # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
-
-    tb.log.info("RX and TX checksum tests")
-
-    payload = bytes([x % 256 for x in range(256)])
-    eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
-    ip = IP(src='192.168.1.100', dst='192.168.1.101')
-    udp = UDP(sport=1, dport=2)
-    test_pkt = eth / ip / udp / payload
-
-    test_pkt2 = test_pkt.copy()
-    test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
-
-    await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
-
-    pkt = await tb.qsfpdd_mac[0][0].tx.recv()
-    tb.log.info("Packet: %s", pkt)
-
-    await tb.qsfpdd_mac[0][0].rx.send(pkt)
-
-    pkt = await tb.driver.interfaces[0].recv()
-
-    tb.log.info("Packet: %s", pkt)
-    assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
-    assert Ether(pkt.data).build() == test_pkt.build()
-
-    tb.log.info("Queue mapping offset test")
-
-    data = bytearray([x % 256 for x in range(1024)])
-
-    tb.loopback_enable = True
-
-    for k in range(4):
-        await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
-
-        await tb.driver.interfaces[0].start_xmit(data, 0)
-
-        pkt = await tb.driver.interfaces[0].recv()
-
-        tb.log.info("Packet: %s", pkt)
-        assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
-        assert pkt.queue == k
-
-    tb.loopback_enable = False
-
-    await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
-
-    tb.log.info("Queue mapping RSS mask test")
-
-    await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
-
-    for k in range(4):
-        await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
-
-    tb.loopback_enable = True
-
-    queues = set()
-
-    for k in range(64):
-        payload = bytes([x % 256 for x in range(256)])
-        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
-        ip = IP(src='192.168.1.100', dst='192.168.1.101')
-        udp = UDP(sport=1, dport=k+0)
-        test_pkt = eth / ip / udp / payload
-
-        test_pkt2 = test_pkt.copy()
-        test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
-
-        await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
-
-    for k in range(64):
-        pkt = await tb.driver.interfaces[0].recv()
-
-        tb.log.info("Packet: %s", pkt)
-        assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
-
-        queues.add(pkt.queue)
-
-    assert len(queues) == 4
-
-    tb.loopback_enable = False
-
-    await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
-
-    tb.log.info("Multiple small packets")
-
-    count = 64
-
-    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
-
-    tb.loopback_enable = True
-
-    for p in pkts:
-        await tb.driver.interfaces[0].start_xmit(p, 0)
-
-    for k in range(count):
-        pkt = await tb.driver.interfaces[0].recv()
-
-        tb.log.info("Packet: %s", pkt)
-        assert pkt.data == pkts[k]
-        assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
-
-    tb.loopback_enable = False
-
-    tb.log.info("Multiple large packets")
-
-    count = 64
-
-    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
-
-    tb.loopback_enable = True
-
-    for p in pkts:
-        await tb.driver.interfaces[0].start_xmit(p, 0)
-
-    for k in range(count):
-        pkt = await tb.driver.interfaces[0].recv()
-
-        tb.log.info("Packet: %s", pkt)
-        assert pkt.data == pkts[k]
-        assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
-
-    tb.loopback_enable = False
-
-    await RisingEdge(dut.clk_250mhz)
-    await RisingEdge(dut.clk_250mhz)
-
-
-# cocotb-test
-
-tests_dir = os.path.dirname(__file__)
-rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
-lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
-app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
-axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
-axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
-eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
-pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
-
-
-def test_fpga_core(request):
-    dut = "fpga_core"
-    module = os.path.splitext(os.path.basename(__file__))[0]
-    toplevel = dut
-
-    verilog_sources = [
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, "common", "mqnic_core_pcie_ptile.v"),
-        os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
-        os.path.join(rtl_dir, "common", "mqnic_core.v"),
-        os.path.join(rtl_dir, "common", "mqnic_interface.v"),
-        os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_egress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
-        os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
-        os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
-        os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
-        os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
-        os.path.join(rtl_dir, "common", "cpl_write.v"),
-        os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
-        os.path.join(rtl_dir, "common", "desc_fetch.v"),
-        os.path.join(rtl_dir, "common", "desc_op_mux.v"),
-        os.path.join(rtl_dir, "common", "queue_manager.v"),
-        os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
-        os.path.join(rtl_dir, "common", "tx_fifo.v"),
-        os.path.join(rtl_dir, "common", "rx_fifo.v"),
-        os.path.join(rtl_dir, "common", "tx_req_mux.v"),
-        os.path.join(rtl_dir, "common", "tx_engine.v"),
-        os.path.join(rtl_dir, "common", "rx_engine.v"),
-        os.path.join(rtl_dir, "common", "tx_checksum.v"),
-        os.path.join(rtl_dir, "common", "rx_hash.v"),
-        os.path.join(rtl_dir, "common", "rx_checksum.v"),
-        os.path.join(rtl_dir, "common", "stats_counter.v"),
-        os.path.join(rtl_dir, "common", "stats_collect.v"),
-        os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
-        os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
-        os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
-        os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
-        os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
-        os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
-        os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
-        os.path.join(rtl_dir, "common", "tdma_ber.v"),
-        os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
-        os.path.join(rtl_dir, "common", "i2c_single_reg.v"),
-        os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
-        os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
-        os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
-        os.path.join(eth_rtl_dir, "lfsr.v"),
-        os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
-        os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
-        os.path.join(eth_rtl_dir, "ptp_perout.v"),
-        os.path.join(axi_rtl_dir, "axil_interconnect.v"),
-        os.path.join(axi_rtl_dir, "axil_crossbar.v"),
-        os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
-        os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
-        os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
-        os.path.join(axi_rtl_dir, "axil_reg_if.v"),
-        os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
-        os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
-        os.path.join(axi_rtl_dir, "axil_register_rd.v"),
-        os.path.join(axi_rtl_dir, "axil_register_wr.v"),
-        os.path.join(axi_rtl_dir, "arbiter.v"),
-        os.path.join(axi_rtl_dir, "priority_encoder.v"),
-        os.path.join(axis_rtl_dir, "axis_adapter.v"),
-        os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
-        os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
-        os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
-        os.path.join(axis_rtl_dir, "axis_demux.v"),
-        os.path.join(axis_rtl_dir, "axis_fifo.v"),
-        os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
-        os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
-        os.path.join(axis_rtl_dir, "axis_register.v"),
-        os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
-        os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
-        os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
-        os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
-        os.path.join(pcie_rtl_dir, "pcie_tlp_fc_count.v"),
-        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
-        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
-        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
-        os.path.join(pcie_rtl_dir, "pcie_msix.v"),
-        os.path.join(pcie_rtl_dir, "irq_rate_limit.v"),
-        os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
-        os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
-        os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
-        os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
-        os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
-        os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
-        os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
-        os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
-        os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
-        os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
-        os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
-        os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
-        os.path.join(pcie_rtl_dir, "pcie_ptile_if.v"),
-        os.path.join(pcie_rtl_dir, "pcie_ptile_if_rx.v"),
-        os.path.join(pcie_rtl_dir, "pcie_ptile_if_tx.v"),
-        os.path.join(pcie_rtl_dir, "pcie_ptile_cfg.v"),
-        os.path.join(pcie_rtl_dir, "pcie_ptile_fc_counter.v"),
-        os.path.join(pcie_rtl_dir, "pulse_merge.v"),
-    ]
-
-    parameters = {}
-
-    # Structural configuration
-    parameters['IF_COUNT'] = 2
-    parameters['PORTS_PER_IF'] = 1
-    parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
-    parameters['PORT_MASK'] = 0
-
-    # Clock configuration
-    parameters['CLK_PERIOD_NS_NUM'] = 4
-    parameters['CLK_PERIOD_NS_DENOM'] = 1
-
-    # PTP configuration
-    parameters['PTP_CLK_PERIOD_NS_NUM'] = 2048
-    parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825
-    parameters['PTP_CLOCK_PIPELINE'] = 0
-    parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
-    parameters['PTP_SEPARATE_TX_CLOCK'] = 0
-    parameters['PTP_SEPARATE_RX_CLOCK'] = 0
-    parameters['PTP_PORT_CDC_PIPELINE'] = 0
-    parameters['PTP_PEROUT_ENABLE'] = 1
-    parameters['PTP_PEROUT_COUNT'] = 1
-
-    # Queue manager configuration
-    parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
-    parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
-    parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
-    parameters['CQ_OP_TABLE_SIZE'] = 32
-    parameters['EQN_WIDTH'] = 6
-    parameters['TX_QUEUE_INDEX_WIDTH'] = 13
-    parameters['RX_QUEUE_INDEX_WIDTH'] = 8
-    parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
-    parameters['EQ_PIPELINE'] = 3
-    parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
-    parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
-    parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
-
-    # TX and RX engine configuration
-    parameters['TX_DESC_TABLE_SIZE'] = 32
-    parameters['RX_DESC_TABLE_SIZE'] = 32
-    parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
-
-    # Scheduler configuration
-    parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
-    parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
-    parameters['TDMA_INDEX_WIDTH'] = 6
-
-    # Interface configuration
-    parameters['PTP_TS_ENABLE'] = 1
-    parameters['TX_CPL_FIFO_DEPTH'] = 32
-    parameters['TX_CHECKSUM_ENABLE'] = 1
-    parameters['RX_HASH_ENABLE'] = 1
-    parameters['RX_CHECKSUM_ENABLE'] = 1
-    parameters['LFC_ENABLE'] = 1
-    parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
-    parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
-    parameters['MAX_TX_SIZE'] = 9214
-    parameters['MAX_RX_SIZE'] = 9214
-    parameters['TX_RAM_SIZE'] = 32768
-    parameters['RX_RAM_SIZE'] = 32768
-
-    # Application block configuration
-    parameters['APP_ID'] = 0x00000000
-    parameters['APP_ENABLE'] = 0
-    parameters['APP_CTRL_ENABLE'] = 1
-    parameters['APP_DMA_ENABLE'] = 1
-    parameters['APP_AXIS_DIRECT_ENABLE'] = 1
-    parameters['APP_AXIS_SYNC_ENABLE'] = 1
-    parameters['APP_AXIS_IF_ENABLE'] = 1
-    parameters['APP_STAT_ENABLE'] = 1
-
-    # DMA interface configuration
-    parameters['DMA_IMM_ENABLE'] = 0
-    parameters['DMA_IMM_WIDTH'] = 32
-    parameters['DMA_LEN_WIDTH'] = 16
-    parameters['DMA_TAG_WIDTH'] = 16
-    parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
-    parameters['RAM_PIPELINE'] = 2
-
-    # PCIe interface configuration
-    parameters['SEG_COUNT'] = 2
-    parameters['SEG_DATA_WIDTH'] = 256
-    parameters['PF_COUNT'] = 1
-    parameters['VF_COUNT'] = 0
-
-    # Interrupt configuration
-    parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
-
-    # AXI lite interface configuration (control)
-    parameters['AXIL_CTRL_DATA_WIDTH'] = 32
-    parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
-
-    # AXI lite interface configuration (application control)
-    parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
-    parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
-
-    # Ethernet interface configuration
-    parameters['AXIS_ETH_TX_PIPELINE'] = 0
-    parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2
-    parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0
-    parameters['AXIS_ETH_RX_PIPELINE'] = 0
-    parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2
-
-    # Statistics counter subsystem
-    parameters['STAT_ENABLE'] = 1
-    parameters['STAT_DMA_ENABLE'] = 1
-    parameters['STAT_PCIE_ENABLE'] = 1
-    parameters['STAT_INC_WIDTH'] = 24
-    parameters['STAT_ID_WIDTH'] = 12
-
-    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
-
-    sim_build = os.path.join(tests_dir, "sim_build",
-        request.node.name.replace('[', '-').replace(']', ''))
-
-    cocotb_test.simulator.run(
-        python_search=[tests_dir],
-        verilog_sources=verilog_sources,
-        toplevel=toplevel,
-        module=module,
-        parameters=parameters,
-        sim_build=sim_build,
-        extra_env=extra_env,
-    )