diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl b/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl index 504586ec9..8a396a22c 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl +++ b/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4_uscale_plus_0] diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga_core.v index 51af00cfe..cebe44275 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga_core.v @@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -185,12 +185,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -209,7 +209,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -229,14 +229,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -697,22 +697,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py index e93dfd385..44533870c 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) async def init(self): @@ -255,17 +255,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/AU200/fpga_axi/ip/pcie4_uscale_plus_0.tcl b/example/AU200/fpga_axi/ip/pcie4_uscale_plus_0.tcl index 55d3ca6e8..8a0e0451b 100644 --- a/example/AU200/fpga_axi/ip/pcie4_uscale_plus_0.tcl +++ b/example/AU200/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4_uscale_plus_0] diff --git a/example/AU200/fpga_axi/rtl/fpga_core.v b/example/AU200/fpga_axi/rtl/fpga_core.v index 1f0d896cc..15cadcc28 100644 --- a/example/AU200/fpga_axi/rtl/fpga_core.v +++ b/example/AU200/fpga_axi/rtl/fpga_core.v @@ -144,19 +144,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -184,12 +184,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -208,7 +208,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -228,14 +228,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -694,22 +694,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py index f45ed9c9e..b6feb55ef 100644 --- a/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) dut.sw.setimmediatevalue(0) @@ -257,17 +257,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/AU250/fpga_axi/ip/pcie4_uscale_plus_0.tcl b/example/AU250/fpga_axi/ip/pcie4_uscale_plus_0.tcl index 55d3ca6e8..8a0e0451b 100644 --- a/example/AU250/fpga_axi/ip/pcie4_uscale_plus_0.tcl +++ b/example/AU250/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4_uscale_plus_0] diff --git a/example/AU250/fpga_axi/rtl/fpga_core.v b/example/AU250/fpga_axi/rtl/fpga_core.v index 1f0d896cc..15cadcc28 100644 --- a/example/AU250/fpga_axi/rtl/fpga_core.v +++ b/example/AU250/fpga_axi/rtl/fpga_core.v @@ -144,19 +144,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -184,12 +184,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -208,7 +208,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -228,14 +228,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -694,22 +694,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py index f45ed9c9e..b6feb55ef 100644 --- a/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) dut.sw.setimmediatevalue(0) @@ -257,17 +257,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/AU280/fpga_axi/ip/pcie4c_uscale_plus_0.tcl b/example/AU280/fpga_axi/ip/pcie4c_uscale_plus_0.tcl index 32664573b..13b91730e 100644 --- a/example/AU280/fpga_axi/ip/pcie4c_uscale_plus_0.tcl +++ b/example/AU280/fpga_axi/ip/pcie4c_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4c_uscale_plus_0] diff --git a/example/AU280/fpga_axi/rtl/fpga_core.v b/example/AU280/fpga_axi/rtl/fpga_core.v index 4c8774241..b0508724f 100644 --- a/example/AU280/fpga_axi/rtl/fpga_core.v +++ b/example/AU280/fpga_axi/rtl/fpga_core.v @@ -138,19 +138,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -178,12 +178,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -202,7 +202,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -222,14 +222,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -686,22 +686,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py index fba716246..9e2274437 100644 --- a/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) async def init(self): @@ -255,17 +255,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/AU50/fpga_axi/ip/pcie4c_uscale_plus_0.tcl b/example/AU50/fpga_axi/ip/pcie4c_uscale_plus_0.tcl index 32664573b..13b91730e 100644 --- a/example/AU50/fpga_axi/ip/pcie4c_uscale_plus_0.tcl +++ b/example/AU50/fpga_axi/ip/pcie4c_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4c_uscale_plus_0] diff --git a/example/AU50/fpga_axi/rtl/fpga_core.v b/example/AU50/fpga_axi/rtl/fpga_core.v index ef05d00a7..3aea3156e 100644 --- a/example/AU50/fpga_axi/rtl/fpga_core.v +++ b/example/AU50/fpga_axi/rtl/fpga_core.v @@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -185,12 +185,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -209,7 +209,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -229,14 +229,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -697,22 +697,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py index fba716246..9e2274437 100644 --- a/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) async def init(self): @@ -255,17 +255,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl b/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl index ef3e4146d..89c2b7473 100644 --- a/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl +++ b/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl @@ -18,12 +18,16 @@ set_property -dict [list \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_class_code_base {02} \ CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.PF0_INTERRUPT_PIN {NONE} \ CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_0} \ CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_0} \ diff --git a/example/ExaNIC_X10/fpga_axi/rtl/fpga_core.v b/example/ExaNIC_X10/fpga_axi/rtl/fpga_core.v index a2eb122d4..6eb1c9034 100644 --- a/example/ExaNIC_X10/fpga_axi/rtl/fpga_core.v +++ b/example/ExaNIC_X10/fpga_axi/rtl/fpga_core.v @@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -185,12 +185,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -209,7 +209,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -229,14 +229,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -699,22 +699,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py index 70c089c80..9afca08a7 100644 --- a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -229,7 +229,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) async def init(self): @@ -249,17 +249,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl b/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl index 0ae73b335..863a2ca12 100644 --- a/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl +++ b/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -19,12 +19,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ CONFIG.mode_selection {Advanced} \ diff --git a/example/ExaNIC_X25/fpga_axi/rtl/fpga_core.v b/example/ExaNIC_X25/fpga_axi/rtl/fpga_core.v index a8bbc1554..965c15d1a 100644 --- a/example/ExaNIC_X25/fpga_axi/rtl/fpga_core.v +++ b/example/ExaNIC_X25/fpga_axi/rtl/fpga_core.v @@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -185,12 +185,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -209,7 +209,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -229,14 +229,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -697,22 +697,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py index e93dfd385..44533870c 100644 --- a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) async def init(self): @@ -255,17 +255,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl b/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl index ef3e4146d..89c2b7473 100644 --- a/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl +++ b/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl @@ -18,12 +18,16 @@ set_property -dict [list \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_class_code_base {02} \ CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.PF0_INTERRUPT_PIN {NONE} \ CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_0} \ CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_0} \ diff --git a/example/VCU108/fpga_axi/rtl/fpga_core.v b/example/VCU108/fpga_axi/rtl/fpga_core.v index e806a6ab6..e7b3864d0 100644 --- a/example/VCU108/fpga_axi/rtl/fpga_core.v +++ b/example/VCU108/fpga_axi/rtl/fpga_core.v @@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [32:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [84:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [84:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [32:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [32:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -184,12 +184,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -208,7 +208,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -228,14 +228,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -691,22 +691,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py index 5d59c7afb..730f9139c 100644 --- a/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -229,7 +229,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -256,17 +256,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl b/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl index 504586ec9..8a396a22c 100644 --- a/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl +++ b/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4_uscale_plus_0] diff --git a/example/VCU118/fpga_axi_x8/rtl/fpga_core.v b/example/VCU118/fpga_axi_x8/rtl/fpga_core.v index 65a73bf53..a6e2c1d77 100644 --- a/example/VCU118/fpga_axi_x8/rtl/fpga_core.v +++ b/example/VCU118/fpga_axi_x8/rtl/fpga_core.v @@ -149,19 +149,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -189,12 +189,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -213,7 +213,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -233,14 +233,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -699,22 +699,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py index b42a57eae..04b73a12f 100644 --- a/example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py +++ b/example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -262,17 +262,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl b/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl index 55d3ca6e8..8a0e0451b 100644 --- a/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl +++ b/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4_uscale_plus_0] diff --git a/example/VCU1525/fpga_axi/rtl/fpga_core.v b/example/VCU1525/fpga_axi/rtl/fpga_core.v index 1f0d896cc..15cadcc28 100644 --- a/example/VCU1525/fpga_axi/rtl/fpga_core.v +++ b/example/VCU1525/fpga_axi/rtl/fpga_core.v @@ -144,19 +144,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -184,12 +184,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -208,7 +208,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -228,14 +228,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -694,22 +694,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py index f45ed9c9e..b6feb55ef 100644 --- a/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) dut.sw.setimmediatevalue(0) @@ -257,17 +257,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/ZCU106/fpga_axi/ip/pcie4_uscale_plus_0.tcl b/example/ZCU106/fpga_axi/ip/pcie4_uscale_plus_0.tcl index b118fd255..d448a77d6 100644 --- a/example/ZCU106/fpga_axi/ip/pcie4_uscale_plus_0.tcl +++ b/example/ZCU106/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4_uscale_plus_0] diff --git a/example/ZCU106/fpga_axi/rtl/fpga_core.v b/example/ZCU106/fpga_axi/rtl/fpga_core.v index 6e6742b64..9155bc955 100644 --- a/example/ZCU106/fpga_axi/rtl/fpga_core.v +++ b/example/ZCU106/fpga_axi/rtl/fpga_core.v @@ -149,19 +149,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -189,12 +189,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -213,7 +213,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -233,14 +233,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -699,22 +699,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py index 89c00a048..e4fa1ee3b 100644 --- a/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -262,17 +262,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' diff --git a/example/common/driver/example_driver.c b/example/common/driver/example_driver.c index 6cdcddf27..660002b01 100644 --- a/example/common/driver/example_driver.c +++ b/example/common/driver/example_driver.c @@ -157,11 +157,11 @@ static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent) dev_info(dev, "CC: %d", ioread32(edev->bar[0]+0x00040C)); // Read/write test - dev_info(dev, "write to BAR1"); - iowrite32(0x11223344, edev->bar[1]); + dev_info(dev, "write to BAR2"); + iowrite32(0x11223344, edev->bar[2]); - dev_info(dev, "read from BAR1"); - dev_info(dev, "%08x", ioread32(edev->bar[1])); + dev_info(dev, "read from BAR2"); + dev_info(dev, "%08x", ioread32(edev->bar[2])); // Dump counters dev_info(dev, "TLP counters"); diff --git a/example/fb2CG/fpga_axi/ip/pcie4_uscale_plus_0.tcl b/example/fb2CG/fpga_axi/ip/pcie4_uscale_plus_0.tcl index 55d3ca6e8..8a0e0451b 100644 --- a/example/fb2CG/fpga_axi/ip/pcie4_uscale_plus_0.tcl +++ b/example/fb2CG/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -17,12 +17,16 @@ set_property -dict [list \ CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_bar1_enabled {true} \ - CONFIG.pf0_bar1_type {Memory} \ - CONFIG.pf0_bar1_scale {Megabytes} \ - CONFIG.pf0_bar1_size {16} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_type {Memory} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ CONFIG.vendor_id {1234} \ CONFIG.en_msi_per_vec_masking {true} \ ] [get_ips pcie4_uscale_plus_0] diff --git a/example/fb2CG/fpga_axi/rtl/fpga_core.v b/example/fb2CG/fpga_axi/rtl/fpga_core.v index 2fee709e3..06d5b1039 100644 --- a/example/fb2CG/fpga_axi/rtl/fpga_core.v +++ b/example/fb2CG/fpga_axi/rtl/fpga_core.v @@ -146,19 +146,19 @@ wire axis_cc_tready_bar_0; wire axis_cc_tlast_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; -wire axis_cq_tvalid_bar_1; -wire axis_cq_tready_bar_1; -wire axis_cq_tlast_bar_1; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2; +wire axis_cq_tvalid_bar_2; +wire axis_cq_tready_bar_2; +wire axis_cq_tlast_bar_2; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; -wire axis_cc_tvalid_bar_1; -wire axis_cc_tready_bar_1; -wire axis_cc_tlast_bar_1; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2; +wire axis_cc_tvalid_bar_2; +wire axis_cc_tready_bar_2; +wire axis_cc_tlast_bar_2; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2; wire [2:0] bar_id; wire [1:0] select; @@ -186,12 +186,12 @@ cq_demux_inst ( /* * AXI output (CQ) */ - .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), - .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), - .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), - .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), - .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), - .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}), /* * Fields @@ -210,7 +210,7 @@ cq_demux_inst ( .select(select) ); -assign select[1] = bar_id == 3'd1; +assign select[1] = bar_id == 3'd2; assign select[0] = bar_id == 3'd0; axis_arb_mux #( @@ -230,14 +230,14 @@ cc_mux_inst ( /* * AXI inputs */ - .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), - .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), - .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), - .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), - .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}), /* * AXI output @@ -699,22 +699,22 @@ pcie_us_axi_master_inst ( /* * AXI input (CQ) */ - .s_axis_cq_tdata(axis_cq_tdata_bar_1), - .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), - .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), - .s_axis_cq_tready(axis_cq_tready_bar_1), - .s_axis_cq_tlast(axis_cq_tlast_bar_1), - .s_axis_cq_tuser(axis_cq_tuser_bar_1), + .s_axis_cq_tdata(axis_cq_tdata_bar_2), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_2), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_2), + .s_axis_cq_tready(axis_cq_tready_bar_2), + .s_axis_cq_tlast(axis_cq_tlast_bar_2), + .s_axis_cq_tuser(axis_cq_tuser_bar_2), /* * AXI output (CC) */ - .m_axis_cc_tdata(axis_cc_tdata_bar_1), - .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), - .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), - .m_axis_cc_tready(axis_cc_tready_bar_1), - .m_axis_cc_tlast(axis_cc_tlast_bar_1), - .m_axis_cc_tuser(axis_cc_tuser_bar_1), + .m_axis_cc_tdata(axis_cc_tdata_bar_2), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_2), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_2), + .m_axis_cc_tready(axis_cc_tready_bar_2), + .m_axis_cc_tlast(axis_cc_tlast_bar_2), + .m_axis_cc_tuser(axis_cc_tuser_bar_2), /* * AXI Master output diff --git a/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py index fba716246..9e2274437 100644 --- a/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -235,7 +235,7 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(1, 2**22) + self.dev.functions[0].configure_bar(2, 2**22) async def init(self): @@ -255,17 +255,17 @@ async def run_test(dut): mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] - dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] + dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] - tb.log.info("Test memory write to BAR 1") + tb.log.info("Test memory write to BAR 2") - await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') + await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') - tb.log.info("Test memory read from BAR 1") + tb.log.info("Test memory read from BAR 2") - val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) + val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44'