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Use 64 bit BARs in example designs

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This commit is contained in:
Alex Forencich 2021-06-16 23:23:53 -07:00
parent a79027fdd1
commit ccc44d7dbb
37 changed files with 616 additions and 568 deletions
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12
example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl
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@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

74
example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga_core.v
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@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -185,12 +185,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -209,7 +209,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -229,14 +229,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -697,22 +697,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
async def init(self): async def init(self):
@ -255,17 +255,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/AU200/fpga_axi/ip/pcie4_uscale_plus_0.tcl
View File

@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

74
example/AU200/fpga_axi/rtl/fpga_core.v
View File

@ -144,19 +144,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -184,12 +184,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -208,7 +208,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -228,14 +228,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -694,22 +694,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
dut.sw.setimmediatevalue(0) dut.sw.setimmediatevalue(0)
@ -257,17 +257,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/AU250/fpga_axi/ip/pcie4_uscale_plus_0.tcl
View File

@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

74
example/AU250/fpga_axi/rtl/fpga_core.v
View File

@ -144,19 +144,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -184,12 +184,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -208,7 +208,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -228,14 +228,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -694,22 +694,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
dut.sw.setimmediatevalue(0) dut.sw.setimmediatevalue(0)
@ -257,17 +257,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/AU280/fpga_axi/ip/pcie4c_uscale_plus_0.tcl
View File

@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4c_uscale_plus_0] ] [get_ips pcie4c_uscale_plus_0]

74
example/AU280/fpga_axi/rtl/fpga_core.v
View File

@ -138,19 +138,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -178,12 +178,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -202,7 +202,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -222,14 +222,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -686,22 +686,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
async def init(self): async def init(self):
@ -255,17 +255,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/AU50/fpga_axi/ip/pcie4c_uscale_plus_0.tcl
View File

@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4c_uscale_plus_0] ] [get_ips pcie4c_uscale_plus_0]

74
example/AU50/fpga_axi/rtl/fpga_core.v
View File

@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -185,12 +185,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -209,7 +209,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -229,14 +229,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -697,22 +697,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
async def init(self): async def init(self):
@ -255,17 +255,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl
View File

@ -18,12 +18,16 @@ set_property -dict [list \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_class_code_base {02} \ CONFIG.pf0_class_code_base {02} \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.PF0_INTERRUPT_PIN {NONE} \ CONFIG.PF0_INTERRUPT_PIN {NONE} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_0} \ CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_0} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_0} \ CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_0} \

74
example/ExaNIC_X10/fpga_axi/rtl/fpga_core.v
View File

@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -185,12 +185,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -209,7 +209,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -229,14 +229,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -699,22 +699,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -229,7 +229,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
async def init(self): async def init(self):
@ -249,17 +249,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl
View File

@ -19,12 +19,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
CONFIG.mode_selection {Advanced} \ CONFIG.mode_selection {Advanced} \

74
example/ExaNIC_X25/fpga_axi/rtl/fpga_core.v
View File

@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -185,12 +185,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -209,7 +209,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -229,14 +229,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -697,22 +697,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
async def init(self): async def init(self):
@ -255,17 +255,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl
View File

@ -18,12 +18,16 @@ set_property -dict [list \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_class_code_base {02} \ CONFIG.pf0_class_code_base {02} \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.PF0_INTERRUPT_PIN {NONE} \ CONFIG.PF0_INTERRUPT_PIN {NONE} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_0} \ CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_0} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_0} \ CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_0} \

74
example/VCU108/fpga_axi/rtl/fpga_core.v
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@ -145,19 +145,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [32:0] axis_cc_tuser_bar_0; wire [32:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [84:0] axis_cq_tuser_bar_1; wire [84:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [32:0] axis_cc_tuser_bar_1; wire [32:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -184,12 +184,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -208,7 +208,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -228,14 +228,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -691,22 +691,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -229,7 +229,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
dut.btnu.setimmediatevalue(0) dut.btnu.setimmediatevalue(0)
dut.btnl.setimmediatevalue(0) dut.btnl.setimmediatevalue(0)
@ -256,17 +256,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl
View File

@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

74
example/VCU118/fpga_axi_x8/rtl/fpga_core.v
View File

@ -149,19 +149,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -189,12 +189,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -213,7 +213,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -233,14 +233,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -699,22 +699,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
dut.btnu.setimmediatevalue(0) dut.btnu.setimmediatevalue(0)
dut.btnl.setimmediatevalue(0) dut.btnl.setimmediatevalue(0)
@ -262,17 +262,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl
View File

@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

74
example/VCU1525/fpga_axi/rtl/fpga_core.v
View File

@ -144,19 +144,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -184,12 +184,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -208,7 +208,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -228,14 +228,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -694,22 +694,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
dut.sw.setimmediatevalue(0) dut.sw.setimmediatevalue(0)
@ -257,17 +257,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

12
example/ZCU106/fpga_axi/ip/pcie4_uscale_plus_0.tcl
View File

@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

74
example/ZCU106/fpga_axi/rtl/fpga_core.v
View File

@ -149,19 +149,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -189,12 +189,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -213,7 +213,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -233,14 +233,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -699,22 +699,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
dut.btnu.setimmediatevalue(0) dut.btnu.setimmediatevalue(0)
dut.btnl.setimmediatevalue(0) dut.btnl.setimmediatevalue(0)
@ -262,17 +262,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'

8
example/common/driver/example_driver.c
View File

@ -157,11 +157,11 @@ static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
dev_info(dev, "CC: %d", ioread32(edev->bar[0]+0x00040C)); dev_info(dev, "CC: %d", ioread32(edev->bar[0]+0x00040C));
// Read/write test // Read/write test
dev_info(dev, "write to BAR1"); dev_info(dev, "write to BAR2");
iowrite32(0x11223344, edev->bar[1]); iowrite32(0x11223344, edev->bar[2]);
dev_info(dev, "read from BAR1"); dev_info(dev, "read from BAR2");
dev_info(dev, "%08x", ioread32(edev->bar[1])); dev_info(dev, "%08x", ioread32(edev->bar[2]));
// Dump counters // Dump counters
dev_info(dev, "TLP counters"); dev_info(dev, "TLP counters");

12
example/fb2CG/fpga_axi/ip/pcie4_uscale_plus_0.tcl
View File

@ -17,12 +17,16 @@ set_property -dict [list \
CONFIG.pf0_class_code_sub {00} \ CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_base_class_menu {Network_controller} \ CONFIG.pf0_base_class_menu {Network_controller} \
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_bar1_enabled {true} \ CONFIG.pf0_bar2_64bit {true} \
CONFIG.pf0_bar1_type {Memory} \ CONFIG.pf0_bar2_prefetchable {true} \
CONFIG.pf0_bar1_scale {Megabytes} \ CONFIG.pf0_bar2_enabled {true} \
CONFIG.pf0_bar1_size {16} \ CONFIG.pf0_bar2_type {Memory} \
CONFIG.pf0_bar2_scale {Megabytes} \
CONFIG.pf0_bar2_size {16} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \ CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

74
example/fb2CG/fpga_axi/rtl/fpga_core.v
View File

@ -146,19 +146,19 @@ wire axis_cc_tready_bar_0;
wire axis_cc_tlast_bar_0; wire axis_cc_tlast_bar_0;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_2;
wire axis_cq_tvalid_bar_1; wire axis_cq_tvalid_bar_2;
wire axis_cq_tready_bar_1; wire axis_cq_tready_bar_2;
wire axis_cq_tlast_bar_1; wire axis_cq_tlast_bar_2;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_1; wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_2;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_2;
wire axis_cc_tvalid_bar_1; wire axis_cc_tvalid_bar_2;
wire axis_cc_tready_bar_1; wire axis_cc_tready_bar_2;
wire axis_cc_tlast_bar_1; wire axis_cc_tlast_bar_2;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_1; wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
wire [2:0] bar_id; wire [2:0] bar_id;
wire [1:0] select; wire [1:0] select;
@ -186,12 +186,12 @@ cq_demux_inst (
/* /*
* AXI output (CQ) * AXI output (CQ)
*/ */
.m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
.m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
.m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
.m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
.m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
.m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
/* /*
* Fields * Fields
@ -210,7 +210,7 @@ cq_demux_inst (
.select(select) .select(select)
); );
assign select[1] = bar_id == 3'd1; assign select[1] = bar_id == 3'd2;
assign select[0] = bar_id == 3'd0; assign select[0] = bar_id == 3'd0;
axis_arb_mux #( axis_arb_mux #(
@ -230,14 +230,14 @@ cc_mux_inst (
/* /*
* AXI inputs * AXI inputs
*/ */
.s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
.s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
.s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
.s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
.s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
.s_axis_tid(0), .s_axis_tid(0),
.s_axis_tdest(0), .s_axis_tdest(0),
.s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
/* /*
* AXI output * AXI output
@ -699,22 +699,22 @@ pcie_us_axi_master_inst (
/* /*
* AXI input (CQ) * AXI input (CQ)
*/ */
.s_axis_cq_tdata(axis_cq_tdata_bar_1), .s_axis_cq_tdata(axis_cq_tdata_bar_2),
.s_axis_cq_tkeep(axis_cq_tkeep_bar_1), .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
.s_axis_cq_tvalid(axis_cq_tvalid_bar_1), .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
.s_axis_cq_tready(axis_cq_tready_bar_1), .s_axis_cq_tready(axis_cq_tready_bar_2),
.s_axis_cq_tlast(axis_cq_tlast_bar_1), .s_axis_cq_tlast(axis_cq_tlast_bar_2),
.s_axis_cq_tuser(axis_cq_tuser_bar_1), .s_axis_cq_tuser(axis_cq_tuser_bar_2),
/* /*
* AXI output (CC) * AXI output (CC)
*/ */
.m_axis_cc_tdata(axis_cc_tdata_bar_1), .m_axis_cc_tdata(axis_cc_tdata_bar_2),
.m_axis_cc_tkeep(axis_cc_tkeep_bar_1), .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
.m_axis_cc_tvalid(axis_cc_tvalid_bar_1), .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
.m_axis_cc_tready(axis_cc_tready_bar_1), .m_axis_cc_tready(axis_cc_tready_bar_2),
.m_axis_cc_tlast(axis_cc_tlast_bar_1), .m_axis_cc_tlast(axis_cc_tlast_bar_2),
.m_axis_cc_tuser(axis_cc_tuser_bar_1), .m_axis_cc_tuser(axis_cc_tuser_bar_2),
/* /*
* AXI Master output * AXI Master output

12
example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -235,7 +235,7 @@ class TB(object):
self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**22) self.dev.functions[0].configure_bar(0, 2**22)
self.dev.functions[0].configure_bar(1, 2**22) self.dev.functions[0].configure_bar(2, 2**22)
async def init(self): async def init(self):
@ -255,17 +255,17 @@ async def run_test(dut):
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar1 = tb.rc.tree[0][0].bar_addr[1] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
tb.log.info("Test memory write to BAR 1") tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44') await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
await Timer(100, 'ns') await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 1") tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar1, 4, 1000) val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
tb.log.info("Read data: %s", val) tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44' assert val == b'\x11\x22\x33\x44'