mirror of
https://github.com/corundum/corundum.git
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fpga/mqnic/Alveo: Rework AU280 clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
152c96dc00
commit
cccd983975
@ -275,7 +275,8 @@ parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
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wire pcie_user_clk;
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wire pcie_user_reset;
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wire clk_161mhz_ref_int;
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wire clk_100mhz_0_ibufg;
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wire clk_100mhz_0_int;
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wire clk_50mhz_mmcm_out;
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wire clk_125mhz_mmcm_out;
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@ -292,19 +293,35 @@ wire mmcm_rst = pcie_user_reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_100mhz_0_ibufg_inst (
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.O (clk_100mhz_0_ibufg),
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.I (clk_100mhz_0_p),
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.IB (clk_100mhz_0_n)
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);
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BUFG
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clk_100mhz_0_bufg_inst (
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.I(clk_100mhz_0_ibufg),
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.O(clk_100mhz_0_int)
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);
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// MMCM instance
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// 161.13 MHz in, 50 MHz + 125 MHz out
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// 100 MHz in, 125 MHz + 50 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 128, D = 15 sets Fvco = 1375 MHz (in range)
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// Divide by 27.5 to get output frequency of 50 MHz
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// Divide by 11 to get output frequency of 125 MHz
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// M = 10, D = 1 sets Fvco = 1000 MHz
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// Divide by 8 to get output frequency of 125 MHz
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// Divide by 20 to get output frequency of 50 MHz
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MMCME4_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(27.5),
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(11),
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.CLKOUT1_DIVIDE(20),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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@ -322,22 +339,22 @@ MMCME4_BASE #(
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(128),
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.CLKFBOUT_MULT_F(10),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(15),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(6.206),
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.CLKIN1_PERIOD(10.000),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_161mhz_ref_int),
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.CLKIN1(clk_100mhz_0_int),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_50mhz_mmcm_out),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(clk_125mhz_mmcm_out),
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.CLKOUT1(clk_50mhz_mmcm_out),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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@ -1045,8 +1062,6 @@ wire qsfp0_mgt_refclk_1;
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wire qsfp0_mgt_refclk_1_int;
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wire qsfp0_mgt_refclk_1_bufg;
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assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
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IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
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.I (qsfp0_mgt_refclk_1_p),
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.IB (qsfp0_mgt_refclk_1_n),
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@ -1338,18 +1353,6 @@ wire [DDR_CH-1:0] ddr_status;
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generate
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wire clk_100mhz_0_ibufg;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_100mhz_0_ibufg_inst (
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.O (clk_100mhz_0_ibufg),
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.I (clk_100mhz_0_p),
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.IB (clk_100mhz_0_n)
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);
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if (DDR_ENABLE && DDR_CH > 0) begin
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reg ddr4_rst_reg = 1'b1;
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@ -1363,7 +1366,7 @@ always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
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end
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ddr4_0 ddr4_c0_inst (
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.c0_sys_clk_i(clk_100mhz_0_ibufg),
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.c0_sys_clk_i(clk_100mhz_0_int),
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.sys_rst(ddr4_rst_reg),
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.c0_init_calib_complete(ddr_status[0 +: 1]),
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@ -1489,6 +1492,7 @@ assign ddr_status = 0;
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end
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wire clk_100mhz_1_ibufg;
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wire clk_100mhz_1_int;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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@ -1500,6 +1504,12 @@ clk_100mhz_1_ibufg_inst (
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.IB (clk_100mhz_1_n)
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);
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BUFG
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clk_100mhz_1_bufg_inst (
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.I(clk_100mhz_1_ibufg),
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.O(clk_100mhz_1_int)
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);
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if (DDR_ENABLE && DDR_CH > 1) begin
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reg ddr4_rst_reg = 1'b1;
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@ -1513,7 +1523,7 @@ always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
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end
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ddr4_0 ddr4_c1_inst (
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.c0_sys_clk_i(clk_100mhz_1_ibufg),
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.c0_sys_clk_i(clk_100mhz_1_int),
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.sys_rst(ddr4_rst_reg),
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.c0_init_calib_complete(ddr_status[1 +: 1]),
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@ -1671,13 +1681,7 @@ generate
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if (HBM_ENABLE) begin
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wire hbm_ref_clk;
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BUFG
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hbm_ref_clk_bufg_inst (
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.I(clk_100mhz_0_ibufg),
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.O(hbm_ref_clk)
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);
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wire hbm_ref_clk = clk_100mhz_0_int;
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wire hbm_cattrip_1;
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wire hbm_cattrip_2;
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@ -281,7 +281,8 @@ parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
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wire pcie_user_clk;
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wire pcie_user_reset;
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wire clk_161mhz_ref_int;
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wire clk_100mhz_0_ibufg;
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wire clk_100mhz_0_int;
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wire clk_50mhz_mmcm_out;
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wire clk_125mhz_mmcm_out;
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@ -298,19 +299,35 @@ wire mmcm_rst = pcie_user_reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_100mhz_0_ibufg_inst (
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.O (clk_100mhz_0_ibufg),
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.I (clk_100mhz_0_p),
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.IB (clk_100mhz_0_n)
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);
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BUFG
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clk_100mhz_0_bufg_inst (
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.I(clk_100mhz_0_ibufg),
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.O(clk_100mhz_0_int)
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);
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// MMCM instance
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// 161.13 MHz in, 50 MHz + 125 MHz out
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// 100 MHz in, 125 MHz + 50 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 128, D = 15 sets Fvco = 1375 MHz (in range)
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// Divide by 27.5 to get output frequency of 50 MHz
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// Divide by 11 to get output frequency of 125 MHz
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// M = 10, D = 1 sets Fvco = 1000 MHz
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// Divide by 8 to get output frequency of 125 MHz
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// Divide by 20 to get output frequency of 50 MHz
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MMCME4_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(27.5),
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(11),
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.CLKOUT1_DIVIDE(20),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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@ -328,22 +345,22 @@ MMCME4_BASE #(
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(128),
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.CLKFBOUT_MULT_F(10),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(15),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(6.206),
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.CLKIN1_PERIOD(10.000),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_161mhz_ref_int),
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.CLKIN1(clk_100mhz_0_int),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_50mhz_mmcm_out),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(clk_125mhz_mmcm_out),
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.CLKOUT1(clk_50mhz_mmcm_out),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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@ -1024,8 +1041,6 @@ wire qsfp0_mgt_refclk_1;
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wire qsfp0_mgt_refclk_1_int;
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wire qsfp0_mgt_refclk_1_bufg;
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assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
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IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
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.I (qsfp0_mgt_refclk_1_p),
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.IB (qsfp0_mgt_refclk_1_n),
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@ -1375,18 +1390,6 @@ wire [DDR_CH-1:0] ddr_status;
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generate
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wire clk_100mhz_0_ibufg;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_100mhz_0_ibufg_inst (
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.O (clk_100mhz_0_ibufg),
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.I (clk_100mhz_0_p),
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.IB (clk_100mhz_0_n)
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);
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if (DDR_ENABLE && DDR_CH > 0) begin
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reg ddr4_rst_reg = 1'b1;
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@ -1400,7 +1403,7 @@ always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
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end
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ddr4_0 ddr4_c0_inst (
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.c0_sys_clk_i(clk_100mhz_0_ibufg),
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.c0_sys_clk_i(clk_100mhz_0_int),
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.sys_rst(ddr4_rst_reg),
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.c0_init_calib_complete(ddr_status[0 +: 1]),
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@ -1526,6 +1529,7 @@ assign ddr_status = 0;
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end
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wire clk_100mhz_1_ibufg;
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wire clk_100mhz_1_int;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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@ -1537,6 +1541,12 @@ clk_100mhz_1_ibufg_inst (
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.IB (clk_100mhz_1_n)
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);
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BUFG
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clk_100mhz_1_bufg_inst (
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.I(clk_100mhz_1_ibufg),
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.O(clk_100mhz_1_int)
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);
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if (DDR_ENABLE && DDR_CH > 1) begin
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reg ddr4_rst_reg = 1'b1;
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@ -1550,7 +1560,7 @@ always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
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end
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ddr4_0 ddr4_c1_inst (
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.c0_sys_clk_i(clk_100mhz_1_ibufg),
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.c0_sys_clk_i(clk_100mhz_1_int),
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.sys_rst(ddr4_rst_reg),
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.c0_init_calib_complete(ddr_status[1 +: 1]),
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@ -1708,13 +1718,7 @@ generate
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if (HBM_ENABLE) begin
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wire hbm_ref_clk;
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BUFG
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hbm_ref_clk_bufg_inst (
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.I(clk_100mhz_0_ibufg),
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.O(hbm_ref_clk)
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);
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wire hbm_ref_clk = clk_100mhz_0_int;
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wire hbm_cattrip_1;
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wire hbm_cattrip_2;
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