From cd7ec5d5e370503058f4a942e958c64523f90087 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 7 Nov 2023 22:27:54 -0800 Subject: [PATCH] fpga/mqnic Merge BittWare XUP-P3R and XUSP3S designs Signed-off-by: Alex Forencich --- fpga/mqnic/XUPP3R/fpga_25g/README.md | 12 +- .../fpga_25g/{fpga => fpga_XUPP3R}/Makefile | 8 +- .../fpga_25g/{fpga => fpga_XUPP3R}/config.tcl | 0 .../{fpga_10g => fpga_XUPP3R_10g}/Makefile | 8 +- .../{fpga_10g => fpga_XUPP3R_10g}/config.tcl | 0 .../fpga_25g/fpga_XUSP3S}/Makefile | 10 +- .../fpga_25g/fpga_XUSP3S}/config.tcl | 0 .../fpga_25g/fpga_XUSP3S_10g}/Makefile | 10 +- .../fpga_25g/fpga_XUSP3S_10g}/config.tcl | 0 .../fpga_XUSP3S_app_dma_bench}/Makefile | 10 +- .../fpga_XUSP3S_app_dma_bench}/config.tcl | 0 .../fpga_25g/{fpga.xdc => fpga_xupp3r.xdc} | 0 .../fpga_25g/fpga_xusp3s.xdc} | 0 .../ip/{ddr4_0.tcl => ddr4_0_xupp3r.tcl} | 0 .../fpga_25g/ip/ddr4_0_xusp3s.tcl} | 0 .../fpga_25g/ip/ddr4_sodimm_0_xusp3s.tcl} | 0 .../{placement.xdc => placement_xupp3r.xdc} | 0 .../fpga_25g/placement_xusp3s.xdc} | 0 fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v | 12 +- .../fpga_25g/rtl/{fpga.v => fpga_xupp3r.v} | 2 + .../fpga_25g/rtl/fpga_xusp3s.v} | 17 +- fpga/mqnic/XUSP3S/fpga_25g/README.md | 23 - fpga/mqnic/XUSP3S/fpga_25g/app | 1 - fpga/mqnic/XUSP3S/fpga_25g/boot.xdc | 4 - fpga/mqnic/XUSP3S/fpga_25g/common/vivado.mk | 137 -- .../mqnic/XUSP3S/fpga_25g/ip/eth_xcvr_gty.tcl | 103 - .../XUSP3S/fpga_25g/ip/pcie3_ultrascale_0.tcl | 32 - fpga/mqnic/XUSP3S/fpga_25g/lib | 1 - fpga/mqnic/XUSP3S/fpga_25g/rtl/common | 1 - fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v | 2086 ----------------- fpga/mqnic/XUSP3S/fpga_25g/rtl/sync_signal.v | 62 - .../XUSP3S/fpga_25g/tb/fpga_core/Makefile | 261 --- .../XUSP3S/fpga_25g/tb/fpga_core/mqnic.py | 1 - .../fpga_25g/tb/fpga_core/test_fpga_core.py | 787 ------- 34 files changed, 53 insertions(+), 3535 deletions(-) rename fpga/mqnic/XUPP3R/fpga_25g/{fpga => fpga_XUPP3R}/Makefile (98%) rename fpga/mqnic/XUPP3R/fpga_25g/{fpga => fpga_XUPP3R}/config.tcl (100%) rename fpga/mqnic/XUPP3R/fpga_25g/{fpga_10g => fpga_XUPP3R_10g}/Makefile (98%) rename fpga/mqnic/XUPP3R/fpga_25g/{fpga_10g => fpga_XUPP3R_10g}/config.tcl (100%) rename fpga/mqnic/{XUSP3S/fpga_25g/fpga => XUPP3R/fpga_25g/fpga_XUSP3S}/Makefile (98%) rename fpga/mqnic/{XUSP3S/fpga_25g/fpga => XUPP3R/fpga_25g/fpga_XUSP3S}/config.tcl (100%) rename fpga/mqnic/{XUSP3S/fpga_25g/fpga_10g => XUPP3R/fpga_25g/fpga_XUSP3S_10g}/Makefile (98%) rename fpga/mqnic/{XUSP3S/fpga_25g/fpga_10g => XUPP3R/fpga_25g/fpga_XUSP3S_10g}/config.tcl (100%) rename fpga/mqnic/{XUSP3S/fpga_25g/fpga_app_dma_bench => XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench}/Makefile (98%) rename fpga/mqnic/{XUSP3S/fpga_25g/fpga_app_dma_bench => XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench}/config.tcl (100%) rename fpga/mqnic/XUPP3R/fpga_25g/{fpga.xdc => fpga_xupp3r.xdc} (100%) rename fpga/mqnic/{XUSP3S/fpga_25g/fpga.xdc => XUPP3R/fpga_25g/fpga_xusp3s.xdc} (100%) rename fpga/mqnic/XUPP3R/fpga_25g/ip/{ddr4_0.tcl => ddr4_0_xupp3r.tcl} (100%) rename fpga/mqnic/{XUSP3S/fpga_25g/ip/ddr4_0.tcl => XUPP3R/fpga_25g/ip/ddr4_0_xusp3s.tcl} (100%) rename fpga/mqnic/{XUSP3S/fpga_25g/ip/ddr4_sodimm_0.tcl => XUPP3R/fpga_25g/ip/ddr4_sodimm_0_xusp3s.tcl} (100%) rename fpga/mqnic/XUPP3R/fpga_25g/{placement.xdc => placement_xupp3r.xdc} (100%) rename fpga/mqnic/{XUSP3S/fpga_25g/placement.xdc => XUPP3R/fpga_25g/placement_xusp3s.xdc} (100%) rename fpga/mqnic/XUPP3R/fpga_25g/rtl/{fpga.v => fpga_xupp3r.v} (99%) rename fpga/mqnic/{XUSP3S/fpga_25g/rtl/fpga.v => XUPP3R/fpga_25g/rtl/fpga_xusp3s.v} (99%) delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/README.md delete mode 120000 fpga/mqnic/XUSP3S/fpga_25g/app delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/boot.xdc delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/common/vivado.mk delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/ip/eth_xcvr_gty.tcl delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/ip/pcie3_ultrascale_0.tcl delete mode 120000 fpga/mqnic/XUSP3S/fpga_25g/lib delete mode 120000 fpga/mqnic/XUSP3S/fpga_25g/rtl/common delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py diff --git a/fpga/mqnic/XUPP3R/fpga_25g/README.md b/fpga/mqnic/XUPP3R/fpga_25g/README.md index f66ba6bf4..d60c63c09 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/README.md +++ b/fpga/mqnic/XUPP3R/fpga_25g/README.md @@ -1,12 +1,16 @@ -# Corundum mqnic for XUP-P3R +# Corundum mqnic for XUP-P3R/XUSP3S ## Introduction -This design targets the BittWare XUP-P3R FPGA board. +This design targets the BittWare XUP-P3R/XUSP3S FPGA board. -* FPGA: xcvu9p-flgb2104-2-e +* FPGA + * XUP-P3R: xcvu9p-flgb2104-2-e + * XUSP3S: xcvu095-ffvb2104-2-e * PHY: 10G BASE-R PHY IP core and internal GTY transceiver -* RAM: 4x DDR4 DIMM +* RAM + * XUP-P3R: 4x DDR4 DIMM + * XUSP3S: 8 GB DDR4 2400 (2x 512M x72) + 2x SODIMM ## Quick start diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/Makefile similarity index 98% rename from fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/Makefile index eb5c63c05..ee72d9ea9 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_xupp3r.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -130,8 +130,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_xupp3r.xdc +XDC_FILES += placement_xupp3r.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl @@ -146,7 +146,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -#IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0_xupp3r.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/config.tcl similarity index 100% rename from fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/Makefile similarity index 98% rename from fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/Makefile index eb5c63c05..ee72d9ea9 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_xupp3r.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -130,8 +130,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_xupp3r.xdc +XDC_FILES += placement_xupp3r.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl @@ -146,7 +146,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -#IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_0_xupp3r.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/config.tcl similarity index 100% rename from fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/config.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/Makefile similarity index 98% rename from fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/Makefile index 9d457dc70..8026e9413 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = VirtexUltrascale # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_xusp3s.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -130,8 +130,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_xusp3s.xdc +XDC_FILES += placement_xusp3s.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl @@ -146,8 +146,8 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -#IP_TCL_FILES += ip/ddr4_0.tcl -#IP_TCL_FILES += ip/ddr4_sodimm_0.tcl +#IP_TCL_FILES += ip/ddr4_0_xusp3s.tcl +#IP_TCL_FILES += ip/ddr4_sodimm_0_xusp3s.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl similarity index 100% rename from fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/Makefile similarity index 98% rename from fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/Makefile index 9d457dc70..8026e9413 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = VirtexUltrascale # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_xusp3s.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -130,8 +130,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_xusp3s.xdc +XDC_FILES += placement_xusp3s.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl @@ -146,8 +146,8 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -#IP_TCL_FILES += ip/ddr4_0.tcl -#IP_TCL_FILES += ip/ddr4_sodimm_0.tcl +#IP_TCL_FILES += ip/ddr4_0_xusp3s.tcl +#IP_TCL_FILES += ip/ddr4_sodimm_0_xusp3s.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/config.tcl similarity index 100% rename from fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/config.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/Makefile similarity index 98% rename from fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/Makefile index 375c175d5..938e19bfd 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = VirtexUltrascale # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_xusp3s.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -136,8 +136,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_xusp3s.xdc +XDC_FILES += placement_xusp3s.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl @@ -156,8 +156,8 @@ XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl -IP_TCL_FILES += ip/ddr4_0.tcl -IP_TCL_FILES += ip/ddr4_sodimm_0.tcl +IP_TCL_FILES += ip/ddr4_0_xusp3s.tcl +IP_TCL_FILES += ip/ddr4_sodimm_0_xusp3s.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/config.tcl similarity index 100% rename from fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc b/fpga/mqnic/XUPP3R/fpga_25g/fpga_xupp3r.xdc similarity index 100% rename from fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_xupp3r.xdc diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga.xdc b/fpga/mqnic/XUPP3R/fpga_25g/fpga_xusp3s.xdc similarity index 100% rename from fpga/mqnic/XUSP3S/fpga_25g/fpga.xdc rename to fpga/mqnic/XUPP3R/fpga_25g/fpga_xusp3s.xdc diff --git a/fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0_xupp3r.tcl similarity index 100% rename from fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0.tcl rename to fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0_xupp3r.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0_xusp3s.tcl similarity index 100% rename from fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_0.tcl rename to fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0_xusp3s.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_sodimm_0.tcl b/fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_sodimm_0_xusp3s.tcl similarity index 100% rename from fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_sodimm_0.tcl rename to fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_sodimm_0_xusp3s.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/placement.xdc b/fpga/mqnic/XUPP3R/fpga_25g/placement_xupp3r.xdc similarity index 100% rename from fpga/mqnic/XUPP3R/fpga_25g/placement.xdc rename to fpga/mqnic/XUPP3R/fpga_25g/placement_xupp3r.xdc diff --git a/fpga/mqnic/XUSP3S/fpga_25g/placement.xdc b/fpga/mqnic/XUPP3R/fpga_25g/placement_xusp3s.xdc similarity index 100% rename from fpga/mqnic/XUSP3S/fpga_25g/placement.xdc rename to fpga/mqnic/XUPP3R/fpga_25g/placement_xusp3s.xdc diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index ed22b33b6..372385cc8 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -26,6 +26,8 @@ module fpga_core # // Board configuration parameter TDMA_BER_ENABLE = 0, + parameter XCVR_DRP_INFO = {8'h09, 8'h03, 8'd0, 8'd4}, + parameter FLASH_SEG_SIZE = 32'h0C000000, // Structural configuration parameter IF_COUNT = 2, @@ -994,7 +996,7 @@ always @(posedge clk_250mhz) begin ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) ctrl_reg_rd_data_reg[7:4] <= 0; // default segment ctrl_reg_rd_data_reg[11:8] <= 1; // fallback segment - ctrl_reg_rd_data_reg[31:12] <= 32'h0C000000 >> 12; // first segment size (192 M) + ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG_SIZE >> 12; // first segment size end RBB+8'h70: begin // SPI flash ctrl: control 0 @@ -1048,7 +1050,7 @@ end rb_drp #( .DRP_ADDR_WIDTH(24), .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .DRP_INFO(XCVR_DRP_INFO), .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), @@ -1090,7 +1092,7 @@ qsfp0_rb_drp_inst ( rb_drp #( .DRP_ADDR_WIDTH(24), .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .DRP_INFO(XCVR_DRP_INFO), .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), @@ -1132,7 +1134,7 @@ qsfp1_rb_drp_inst ( rb_drp #( .DRP_ADDR_WIDTH(24), .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .DRP_INFO(XCVR_DRP_INFO), .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), @@ -1174,7 +1176,7 @@ qsfp2_rb_drp_inst ( rb_drp #( .DRP_ADDR_WIDTH(24), .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .DRP_INFO(XCVR_DRP_INFO), .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v similarity index 99% rename from fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v rename to fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v index bf20bf3b3..c7caeba4e 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v @@ -2439,6 +2439,8 @@ fpga_core #( // Board configuration .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + .XCVR_DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .FLASH_SEG_SIZE(32'h0C000000), // Structural configuration .IF_COUNT(IF_COUNT), diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v similarity index 99% rename from fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v rename to fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v index 816c74167..9197a8fb0 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v @@ -2458,6 +2458,8 @@ fpga_core #( // Board configuration .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + .XCVR_DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), + .FLASH_SEG_SIZE(32'h03000000), // Structural configuration .IF_COUNT(IF_COUNT), @@ -2661,8 +2663,10 @@ core_inst ( .m_axis_cc_tuser(axis_cc_tuser), .m_axis_cc_tvalid(axis_cc_tvalid), - .s_axis_rq_seq_num(pcie_rq_seq_num), - .s_axis_rq_seq_num_valid(pcie_rq_seq_num_vld), + .s_axis_rq_seq_num_0(pcie_rq_seq_num), + .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld), + .s_axis_rq_seq_num_1(4'd0), + .s_axis_rq_seq_num_valid_1(1'b0), .pcie_tfc_nph_av(pcie_tfc_nph_av), .pcie_tfc_npd_av(pcie_tfc_npd_av), @@ -2671,7 +2675,8 @@ core_inst ( .cfg_max_read_req(cfg_max_read_req), .cfg_rcb_status(cfg_rcb_status), - .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_addr(cfg_mgmt_addr[9:0]), + .cfg_mgmt_function_number(cfg_mgmt_addr[17:10]), .cfg_mgmt_write(cfg_mgmt_write), .cfg_mgmt_write_data(cfg_mgmt_write_data), .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), @@ -2694,6 +2699,8 @@ core_inst ( .cfg_interrupt_msix_address(cfg_interrupt_msix_address), .cfg_interrupt_msix_data(cfg_interrupt_msix_data), .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(), + .cfg_interrupt_msix_vec_pending_status(1'b0), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), @@ -3031,7 +3038,7 @@ core_inst ( .ddr_status(ddr_status), /* - * BPI flash + * QSPI flash */ .fpga_boot(fpga_boot), .qspi_clk(qspi_clk_int), @@ -3041,6 +3048,8 @@ core_inst ( .qspi_cs(qspi_cs_int) ); +assign cfg_mgmt_addr[18] = 1'b0; + endmodule `resetall diff --git a/fpga/mqnic/XUSP3S/fpga_25g/README.md b/fpga/mqnic/XUSP3S/fpga_25g/README.md deleted file mode 100644 index e45bc8a8a..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/README.md +++ /dev/null @@ -1,23 +0,0 @@ -# Corundum mqnic for XUSP3S - -## Introduction - -This design targets the BittWare XUSP3S FPGA board. - -* FPGA: xcvu095-ffvb2104-2-e -* PHY: 10G BASE-R PHY IP core and internal GTY transceiver -* RAM: 8 GB DDR4 2400 (2x 512M x72) + 2x SODIMM - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/XUSP3S/fpga_25g/app b/fpga/mqnic/XUSP3S/fpga_25g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/XUSP3S/fpga_25g/boot.xdc b/fpga/mqnic/XUSP3S/fpga_25g/boot.xdc deleted file mode 100644 index 5fb323e94..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/boot.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for FPGA boot logic - -set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] -set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/common/vivado.mk b/fpga/mqnic/XUSP3S/fpga_25g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/XUSP3S/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/XUSP3S/fpga_25g/ip/eth_xcvr_gty.tcl deleted file mode 100644 index c7e049079..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/ip/eth_xcvr_gty.tcl +++ /dev/null @@ -1,103 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2022-2023 The Regents of the University of California - -set base_name {eth_xcvr_gty} - -set preset {GTY-10GBASE-R} - -set freerun_freq {125} -set line_rate {25.78125} -set sec_line_rate {10.3125} -set refclk_freq {322.265625} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {64} -set int_data_width $user_data_width -set rx_eq_mode {DFE} -set extra_ports [list] -set extra_pll_ports [list] -# DRP connections -lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out -lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out -# PLL reset and power down -lappend extra_pll_ports qpll0reset_in qpll1reset_in -lappend extra_pll_ports qpll0pd_in qpll1pd_in -# PLL clocking -lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out -lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out -# channel reset -lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out -lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out -# channel power down -lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in -# channel clock selection -lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in -# channel polarity -lappend extra_ports txpolarity_in rxpolarity_in -# channel TX driver -lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in -# channel CDR -lappend extra_ports rxcdrlock_out rxcdrhold_in -# channel EQ -lappend extra_ports rxlpmen_in -# channel digital monitor -lappend extra_ports dmonitorout_out -# channel PRBS -lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out -# channel eye scan -lappend extra_ports eyescandataerror_out -# channel loopback -lappend extra_ports loopback_in - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config RX_EQ_MODE $rx_eq_mode -if {$sec_line_rate != 0} { - dict set config SECONDARY_QPLL_ENABLE true - dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn - dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq -} else { - dict set config SECONDARY_QPLL_ENABLE false -} -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} -dict set config LOCATE_TX_USER_CLOCKING {CORE} -dict set config LOCATE_RX_USER_CLOCKING {CORE} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/XUSP3S/fpga_25g/ip/pcie3_ultrascale_0.tcl b/fpga/mqnic/XUSP3S/fpga_25g/ip/pcie3_ultrascale_0.tcl deleted file mode 100644 index feb528331..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/ip/pcie3_ultrascale_0.tcl +++ /dev/null @@ -1,32 +0,0 @@ - -create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 - -set_property -dict [list \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ - CONFIG.AXISTEN_IF_RC_STRADDLE {true} \ - CONFIG.axisten_if_width {256_bit} \ - CONFIG.extended_tag_field {true} \ - CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ - CONFIG.axisten_freq {250} \ - CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ - CONFIG.pf0_class_code_base {02} \ - CONFIG.pf0_class_code_sub {00} \ - CONFIG.pf0_class_code_interface {00} \ - CONFIG.PF0_DEVICE_ID {1001} \ - CONFIG.PF0_SUBSYSTEM_ID {8823} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {12ba} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_prefetchable {true} \ - CONFIG.pf0_bar0_scale {Megabytes} \ - CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_msi_enabled {false} \ - CONFIG.pf0_msix_enabled {true} \ - CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ - CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ - CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ - CONFIG.vendor_id {1234} \ - CONFIG.mode_selection {Advanced} \ -] [get_ips pcie3_ultrascale_0] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/lib b/fpga/mqnic/XUSP3S/fpga_25g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/common b/fpga/mqnic/XUSP3S/fpga_25g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v deleted file mode 100644 index be2e46f0a..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v +++ /dev/null @@ -1,2086 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'h3842093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h12ba_8823, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Board configuration - parameter TDMA_BER_ENABLE = 0, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 512, - parameter PTP_CLK_PERIOD_NS_DENOM = 165, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 1, - parameter PTP_PEROUT_COUNT = 1, - parameter IF_PTP_PERIOD_NS = 6'h6, - parameter IF_PTP_PERIOD_FNS = 16'h6666, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 11, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 16, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter ENABLE_PADDING = 1, - parameter ENABLE_DIC = 1, - parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 31, - parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 256, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = 75, - parameter AXIS_PCIE_RQ_USER_WIDTH = 60, - parameter AXIS_PCIE_CQ_USER_WIDTH = 85, - parameter AXIS_PCIE_CC_USER_WIDTH = 33, - parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, - parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter RQ_SEQ_NUM_WIDTH = 4, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 64, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter XGMII_DATA_WIDTH = 64, - parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, - parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 0, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, - parameter AXIS_ETH_TX_TS_PIPELINE = 0, - parameter AXIS_ETH_RX_PIPELINE = 0, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - output wire [3:0] led, - input wire ext_pps_in, - input wire ext_clk_in, - - /* - * I2C - */ - input wire eeprom_i2c_scl_i, - output wire eeprom_i2c_scl_o, - output wire eeprom_i2c_scl_t, - input wire eeprom_i2c_sda_i, - output wire eeprom_i2c_sda_o, - output wire eeprom_i2c_sda_t, - - /* - * PCIe - */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, - - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, - - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num, - input wire s_axis_rq_seq_num_valid, - - input wire [1:0] pcie_tfc_nph_av, - input wire [1:0] pcie_tfc_npd_av, - - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, - - output wire [18:0] cfg_mgmt_addr, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, - - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - input wire [1:0] cfg_interrupt_msix_enable, - input wire [1:0] cfg_interrupt_msix_mask, - input wire [7:0] cfg_interrupt_msix_vf_enable, - input wire [7:0] cfg_interrupt_msix_vf_mask, - output wire [63:0] cfg_interrupt_msix_address, - output wire [31:0] cfg_interrupt_msix_data, - output wire cfg_interrupt_msix_int, - input wire cfg_interrupt_msix_sent, - input wire cfg_interrupt_msix_fail, - output wire [3:0] cfg_interrupt_msi_function_number, - - output wire status_error_cor, - output wire status_error_uncor, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp0_tx_clk_1, - input wire qsfp0_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1, - output wire qsfp0_cfg_tx_prbs31_enable_1, - input wire qsfp0_rx_clk_1, - input wire qsfp0_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1, - output wire qsfp0_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp0_rx_error_count_1, - input wire qsfp0_rx_status_1, - input wire qsfp0_tx_clk_2, - input wire qsfp0_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2, - output wire qsfp0_cfg_tx_prbs31_enable_2, - input wire qsfp0_rx_clk_2, - input wire qsfp0_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2, - output wire qsfp0_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp0_rx_error_count_2, - input wire qsfp0_rx_status_2, - input wire qsfp0_tx_clk_3, - input wire qsfp0_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3, - output wire qsfp0_cfg_tx_prbs31_enable_3, - input wire qsfp0_rx_clk_3, - input wire qsfp0_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3, - output wire qsfp0_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp0_rx_error_count_3, - input wire qsfp0_rx_status_3, - input wire qsfp0_tx_clk_4, - input wire qsfp0_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4, - output wire qsfp0_cfg_tx_prbs31_enable_4, - input wire qsfp0_rx_clk_4, - input wire qsfp0_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4, - output wire qsfp0_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp0_rx_error_count_4, - input wire qsfp0_rx_status_4, - - input wire qsfp0_drp_clk, - input wire qsfp0_drp_rst, - output wire [23:0] qsfp0_drp_addr, - output wire [15:0] qsfp0_drp_di, - output wire qsfp0_drp_en, - output wire qsfp0_drp_we, - input wire [15:0] qsfp0_drp_do, - input wire qsfp0_drp_rdy, - - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - - input wire qsfp0_i2c_scl_i, - output wire qsfp0_i2c_scl_o, - output wire qsfp0_i2c_scl_t, - input wire qsfp0_i2c_sda_i, - output wire qsfp0_i2c_sda_o, - output wire qsfp0_i2c_sda_t, - - input wire qsfp1_tx_clk_1, - input wire qsfp1_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1, - output wire qsfp1_cfg_tx_prbs31_enable_1, - input wire qsfp1_rx_clk_1, - input wire qsfp1_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1, - output wire qsfp1_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp1_rx_error_count_1, - input wire qsfp1_rx_status_1, - input wire qsfp1_tx_clk_2, - input wire qsfp1_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2, - output wire qsfp1_cfg_tx_prbs31_enable_2, - input wire qsfp1_rx_clk_2, - input wire qsfp1_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2, - output wire qsfp1_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp1_rx_error_count_2, - input wire qsfp1_rx_status_2, - input wire qsfp1_tx_clk_3, - input wire qsfp1_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3, - output wire qsfp1_cfg_tx_prbs31_enable_3, - input wire qsfp1_rx_clk_3, - input wire qsfp1_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3, - output wire qsfp1_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp1_rx_error_count_3, - input wire qsfp1_rx_status_3, - input wire qsfp1_tx_clk_4, - input wire qsfp1_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4, - output wire qsfp1_cfg_tx_prbs31_enable_4, - input wire qsfp1_rx_clk_4, - input wire qsfp1_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4, - output wire qsfp1_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp1_rx_error_count_4, - input wire qsfp1_rx_status_4, - - input wire qsfp1_drp_clk, - input wire qsfp1_drp_rst, - output wire [23:0] qsfp1_drp_addr, - output wire [15:0] qsfp1_drp_di, - output wire qsfp1_drp_en, - output wire qsfp1_drp_we, - input wire [15:0] qsfp1_drp_do, - input wire qsfp1_drp_rdy, - - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - - input wire qsfp1_i2c_scl_i, - output wire qsfp1_i2c_scl_o, - output wire qsfp1_i2c_scl_t, - input wire qsfp1_i2c_sda_i, - output wire qsfp1_i2c_sda_o, - output wire qsfp1_i2c_sda_t, - - input wire qsfp2_tx_clk_1, - input wire qsfp2_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1, - output wire qsfp2_cfg_tx_prbs31_enable_1, - input wire qsfp2_rx_clk_1, - input wire qsfp2_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1, - output wire qsfp2_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp2_rx_error_count_1, - input wire qsfp2_rx_status_1, - input wire qsfp2_tx_clk_2, - input wire qsfp2_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2, - output wire qsfp2_cfg_tx_prbs31_enable_2, - input wire qsfp2_rx_clk_2, - input wire qsfp2_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2, - output wire qsfp2_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp2_rx_error_count_2, - input wire qsfp2_rx_status_2, - input wire qsfp2_tx_clk_3, - input wire qsfp2_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3, - output wire qsfp2_cfg_tx_prbs31_enable_3, - input wire qsfp2_rx_clk_3, - input wire qsfp2_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3, - output wire qsfp2_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp2_rx_error_count_3, - input wire qsfp2_rx_status_3, - input wire qsfp2_tx_clk_4, - input wire qsfp2_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4, - output wire qsfp2_cfg_tx_prbs31_enable_4, - input wire qsfp2_rx_clk_4, - input wire qsfp2_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4, - output wire qsfp2_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp2_rx_error_count_4, - input wire qsfp2_rx_status_4, - - input wire qsfp2_drp_clk, - input wire qsfp2_drp_rst, - output wire [23:0] qsfp2_drp_addr, - output wire [15:0] qsfp2_drp_di, - output wire qsfp2_drp_en, - output wire qsfp2_drp_we, - input wire [15:0] qsfp2_drp_do, - input wire qsfp2_drp_rdy, - - output wire qsfp2_resetl, - input wire qsfp2_modprsl, - input wire qsfp2_intl, - output wire qsfp2_lpmode, - - input wire qsfp2_i2c_scl_i, - output wire qsfp2_i2c_scl_o, - output wire qsfp2_i2c_scl_t, - input wire qsfp2_i2c_sda_i, - output wire qsfp2_i2c_sda_o, - output wire qsfp2_i2c_sda_t, - - input wire qsfp3_tx_clk_1, - input wire qsfp3_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1, - output wire qsfp3_cfg_tx_prbs31_enable_1, - input wire qsfp3_rx_clk_1, - input wire qsfp3_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1, - output wire qsfp3_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp3_rx_error_count_1, - input wire qsfp3_rx_status_1, - input wire qsfp3_tx_clk_2, - input wire qsfp3_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2, - output wire qsfp3_cfg_tx_prbs31_enable_2, - input wire qsfp3_rx_clk_2, - input wire qsfp3_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2, - output wire qsfp3_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp3_rx_error_count_2, - input wire qsfp3_rx_status_2, - input wire qsfp3_tx_clk_3, - input wire qsfp3_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3, - output wire qsfp3_cfg_tx_prbs31_enable_3, - input wire qsfp3_rx_clk_3, - input wire qsfp3_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3, - output wire qsfp3_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp3_rx_error_count_3, - input wire qsfp3_rx_status_3, - input wire qsfp3_tx_clk_4, - input wire qsfp3_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4, - output wire qsfp3_cfg_tx_prbs31_enable_4, - input wire qsfp3_rx_clk_4, - input wire qsfp3_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4, - output wire qsfp3_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp3_rx_error_count_4, - input wire qsfp3_rx_status_4, - - input wire qsfp3_drp_clk, - input wire qsfp3_drp_rst, - output wire [23:0] qsfp3_drp_addr, - output wire [15:0] qsfp3_drp_di, - output wire qsfp3_drp_en, - output wire qsfp3_drp_we, - input wire [15:0] qsfp3_drp_do, - input wire qsfp3_drp_rdy, - - output wire qsfp3_resetl, - input wire qsfp3_modprsl, - input wire qsfp3_intl, - output wire qsfp3_lpmode, - - input wire qsfp3_i2c_scl_i, - output wire qsfp3_i2c_scl_o, - output wire qsfp3_i2c_scl_t, - input wire qsfp3_i2c_sda_i, - output wire qsfp3_i2c_sda_o, - output wire qsfp3_i2c_sda_t, - - /* - * DDR - */ - input wire [DDR_CH-1:0] ddr_clk, - input wire [DDR_CH-1:0] ddr_rst, - - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, - output wire [DDR_CH-1:0] m_axi_ddr_awlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, - output wire [DDR_CH-1:0] m_axi_ddr_awvalid, - input wire [DDR_CH-1:0] m_axi_ddr_awready, - output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, - output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, - output wire [DDR_CH-1:0] m_axi_ddr_wlast, - output wire [DDR_CH-1:0] m_axi_ddr_wvalid, - input wire [DDR_CH-1:0] m_axi_ddr_wready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, - input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, - input wire [DDR_CH-1:0] m_axi_ddr_bvalid, - output wire [DDR_CH-1:0] m_axi_ddr_bready, - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, - output wire [DDR_CH-1:0] m_axi_ddr_arlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, - output wire [DDR_CH-1:0] m_axi_ddr_arvalid, - input wire [DDR_CH-1:0] m_axi_ddr_arready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, - input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, - input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, - input wire [DDR_CH-1:0] m_axi_ddr_rlast, - input wire [DDR_CH-1:0] m_axi_ddr_rvalid, - output wire [DDR_CH-1:0] m_axi_ddr_rready, - - input wire [DDR_CH-1:0] ddr_status, - - /* - * BPI Flash - */ - output wire fpga_boot, - output wire qspi_clk, - input wire [3:0] qspi_dq_i, - output wire [3:0] qspi_dq_o, - output wire [3:0] qspi_dq_oe, - output wire qspi_cs -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -localparam RB_DRP_QSFP0_BASE = RB_BASE_ADDR + 16'h80; -localparam RB_DRP_QSFP1_BASE = RB_DRP_QSFP0_BASE + 16'h20; -localparam RB_DRP_QSFP2_BASE = RB_DRP_QSFP1_BASE + 16'h20; -localparam RB_DRP_QSFP3_BASE = RB_DRP_QSFP2_BASE + 16'h20; - -initial begin - if (PORT_COUNT > 16) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// AXI lite connections -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; -wire [2:0] axil_csr_awprot; -wire axil_csr_awvalid; -wire axil_csr_awready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; -wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; -wire axil_csr_wvalid; -wire axil_csr_wready; -wire [1:0] axil_csr_bresp; -wire axil_csr_bvalid; -wire axil_csr_bready; -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; -wire [2:0] axil_csr_arprot; -wire axil_csr_arvalid; -wire axil_csr_arready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; -wire [1:0] axil_csr_rresp; -wire axil_csr_rvalid; -wire axil_csr_rready; - -// PTP -wire ptp_td_sd; -wire ptp_pps; -wire ptp_pps_str; -wire ptp_sync_locked; -wire [63:0] ptp_sync_ts_rel; -wire ptp_sync_ts_rel_step; -wire [95:0] ptp_sync_ts_tod; -wire ptp_sync_ts_tod_step; -wire ptp_sync_pps; -wire ptp_sync_pps_str; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -wire qsfp0_drp_reg_wr_wait; -wire qsfp0_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp0_drp_reg_rd_data; -wire qsfp0_drp_reg_rd_wait; -wire qsfp0_drp_reg_rd_ack; - -wire qsfp1_drp_reg_wr_wait; -wire qsfp1_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data; -wire qsfp1_drp_reg_rd_wait; -wire qsfp1_drp_reg_rd_ack; - -wire qsfp2_drp_reg_wr_wait; -wire qsfp2_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp2_drp_reg_rd_data; -wire qsfp2_drp_reg_rd_wait; -wire qsfp2_drp_reg_rd_ack; - -wire qsfp3_drp_reg_wr_wait; -wire qsfp3_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp3_drp_reg_rd_data; -wire qsfp3_drp_reg_rd_wait; -wire qsfp3_drp_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg qsfp0_reset_reg = 1'b0; -reg qsfp1_reset_reg = 1'b0; -reg qsfp2_reset_reg = 1'b0; -reg qsfp3_reset_reg = 1'b0; - -reg qsfp0_lpmode_reg = 1'b0; -reg qsfp1_lpmode_reg = 1'b0; -reg qsfp2_lpmode_reg = 1'b0; -reg qsfp3_lpmode_reg = 1'b0; - -reg eeprom_i2c_scl_o_reg = 1'b1; -reg eeprom_i2c_sda_o_reg = 1'b1; - -reg qsfp0_i2c_scl_o_reg = 1'b1; -reg qsfp0_i2c_sda_o_reg = 1'b1; - -reg qsfp1_i2c_scl_o_reg = 1'b1; -reg qsfp1_i2c_sda_o_reg = 1'b1; - -reg qsfp2_i2c_scl_o_reg = 1'b1; -reg qsfp2_i2c_sda_o_reg = 1'b1; - -reg qsfp3_i2c_scl_o_reg = 1'b1; -reg qsfp3_i2c_sda_o_reg = 1'b1; - -reg fpga_boot_reg = 1'b0; - -reg qspi_clk_reg = 1'b0; -reg qspi_cs_reg = 1'b1; -reg [3:0] qspi_dq_o_reg = 4'd0; -reg [3:0] qspi_dq_oe_reg = 4'd0; - -assign ctrl_reg_wr_wait = qsfp0_drp_reg_wr_wait | qsfp1_drp_reg_wr_wait | qsfp2_drp_reg_wr_wait | qsfp3_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp0_drp_reg_wr_ack | qsfp1_drp_reg_wr_ack | qsfp2_drp_reg_wr_ack | qsfp3_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp0_drp_reg_rd_data | qsfp1_drp_reg_rd_data | qsfp2_drp_reg_rd_data | qsfp3_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp0_drp_reg_rd_wait | qsfp1_drp_reg_rd_wait | qsfp2_drp_reg_rd_wait | qsfp3_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp0_drp_reg_rd_ack | qsfp1_drp_reg_rd_ack | qsfp2_drp_reg_rd_ack | qsfp3_drp_reg_rd_ack; - -assign qsfp0_resetl = !qsfp0_reset_reg; -assign qsfp1_resetl = !qsfp1_reset_reg; -assign qsfp2_resetl = !qsfp2_reset_reg; -assign qsfp3_resetl = !qsfp3_reset_reg; - -assign qsfp0_lpmode = qsfp0_lpmode_reg; -assign qsfp1_lpmode = qsfp1_lpmode_reg; -assign qsfp2_lpmode = qsfp2_lpmode_reg; -assign qsfp3_lpmode = qsfp3_lpmode_reg; - -assign eeprom_i2c_scl_o = eeprom_i2c_scl_o_reg; -assign eeprom_i2c_scl_t = eeprom_i2c_scl_o_reg; -assign eeprom_i2c_sda_o = eeprom_i2c_sda_o_reg; -assign eeprom_i2c_sda_t = eeprom_i2c_sda_o_reg; - -assign qsfp0_i2c_scl_o = qsfp0_i2c_scl_o_reg; -assign qsfp0_i2c_scl_t = qsfp0_i2c_scl_o_reg; -assign qsfp0_i2c_sda_o = qsfp0_i2c_sda_o_reg; -assign qsfp0_i2c_sda_t = qsfp0_i2c_sda_o_reg; - -assign qsfp1_i2c_scl_o = qsfp1_i2c_scl_o_reg; -assign qsfp1_i2c_scl_t = qsfp1_i2c_scl_o_reg; -assign qsfp1_i2c_sda_o = qsfp1_i2c_sda_o_reg; -assign qsfp1_i2c_sda_t = qsfp1_i2c_sda_o_reg; - -assign qsfp2_i2c_scl_o = qsfp2_i2c_scl_o_reg; -assign qsfp2_i2c_scl_t = qsfp2_i2c_scl_o_reg; -assign qsfp2_i2c_sda_o = qsfp2_i2c_sda_o_reg; -assign qsfp2_i2c_sda_t = qsfp2_i2c_sda_o_reg; - -assign qsfp3_i2c_scl_o = qsfp3_i2c_scl_o_reg; -assign qsfp3_i2c_scl_t = qsfp3_i2c_scl_o_reg; -assign qsfp3_i2c_sda_o = qsfp3_i2c_sda_o_reg; -assign qsfp3_i2c_sda_t = qsfp3_i2c_sda_o_reg; - -assign fpga_boot = fpga_boot_reg; - -assign qspi_clk = qspi_clk_reg; -assign qspi_cs = qspi_cs_reg; -assign qspi_dq_o = qspi_dq_o_reg; -assign qspi_dq_oe = qspi_dq_oe_reg; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // FW ID - 8'h0C: begin - // FW ID: FPGA JTAG ID - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - // I2C 0 - RBB+8'h0C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - qsfp0_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp0_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // I2C 1 - RBB+8'h1C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - qsfp1_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp1_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // I2C 2 - RBB+8'h2C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - qsfp2_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp2_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // I2C 3 - RBB+8'h3C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - qsfp3_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp3_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // I2C 4 - RBB+8'h4C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - eeprom_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - eeprom_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // XCVR GPIO - RBB+8'h5C: begin - // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - qsfp0_reset_reg <= ctrl_reg_wr_data[4]; - qsfp0_lpmode_reg <= ctrl_reg_wr_data[5]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp1_reset_reg <= ctrl_reg_wr_data[12]; - qsfp1_lpmode_reg <= ctrl_reg_wr_data[13]; - end - if (ctrl_reg_wr_strb[2]) begin - qsfp2_reset_reg <= ctrl_reg_wr_data[20]; - qsfp2_lpmode_reg <= ctrl_reg_wr_data[21]; - end - if (ctrl_reg_wr_strb[3]) begin - qsfp3_reset_reg <= ctrl_reg_wr_data[28]; - qsfp3_lpmode_reg <= ctrl_reg_wr_data[29]; - end - end - // QSPI flash - RBB+8'h6C: begin - // SPI flash ctrl: format - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - RBB+8'h70: begin - // SPI flash ctrl: control 0 - if (ctrl_reg_wr_strb[0]) begin - qspi_dq_o_reg <= ctrl_reg_wr_data[3:0]; - end - if (ctrl_reg_wr_strb[1]) begin - qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8]; - end - if (ctrl_reg_wr_strb[2]) begin - qspi_clk_reg <= ctrl_reg_wr_data[16]; - qspi_cs_reg <= ctrl_reg_wr_data[17]; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header - RBB+8'h0C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= qsfp0_i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= qsfp0_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= qsfp0_i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= qsfp0_i2c_sda_o_reg; - end - // I2C 1 - RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // I2C ctrl: Next header - RBB+8'h1C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= qsfp1_i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= qsfp1_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= qsfp1_i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= qsfp1_i2c_sda_o_reg; - end - // I2C 2 - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h30; // I2C ctrl: Next header - RBB+8'h2C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= qsfp2_i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= qsfp2_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= qsfp2_i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= qsfp2_i2c_sda_o_reg; - end - // I2C 3 - RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h38: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // I2C ctrl: Next header - RBB+8'h3C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= qsfp3_i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= qsfp3_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= qsfp3_i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= qsfp3_i2c_sda_o_reg; - end - // I2C 4 - RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h48: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h50; // I2C ctrl: Next header - RBB+8'h4C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= eeprom_i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= eeprom_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= eeprom_i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= eeprom_i2c_sda_o_reg; - end - // XCVR GPIO - RBB+8'h50: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type - RBB+8'h54: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version - RBB+8'h58: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h60; // XCVR GPIO: Next header - RBB+8'h5C: begin - // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !qsfp0_modprsl; - ctrl_reg_rd_data_reg[1] <= !qsfp0_intl; - ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg; - ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg; - ctrl_reg_rd_data_reg[8] <= !qsfp1_modprsl; - ctrl_reg_rd_data_reg[9] <= !qsfp1_intl; - ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg; - ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg; - ctrl_reg_rd_data_reg[16] <= !qsfp2_modprsl; - ctrl_reg_rd_data_reg[17] <= !qsfp2_intl; - ctrl_reg_rd_data_reg[20] <= qsfp2_reset_reg; - ctrl_reg_rd_data_reg[21] <= qsfp2_lpmode_reg; - ctrl_reg_rd_data_reg[24] <= !qsfp3_modprsl; - ctrl_reg_rd_data_reg[25] <= !qsfp3_intl; - ctrl_reg_rd_data_reg[28] <= qsfp3_reset_reg; - ctrl_reg_rd_data_reg[29] <= qsfp3_lpmode_reg; - end - // QSPI flash - RBB+8'h60: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type - RBB+8'h64: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version - RBB+8'h68: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // SPI flash ctrl: Next header - RBB+8'h6C: begin - // SPI flash ctrl: format - ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) - ctrl_reg_rd_data_reg[7:4] <= 0; // default segment - ctrl_reg_rd_data_reg[11:8] <= 1; // fallback segment - ctrl_reg_rd_data_reg[31:12] <= 32'h03000000 >> 12; // first segment size (48 M) - end - RBB+8'h70: begin - // SPI flash ctrl: control 0 - ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i; - ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe; - ctrl_reg_rd_data_reg[16] <= qspi_clk; - ctrl_reg_rd_data_reg[17] <= qspi_cs; - end - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - qsfp0_reset_reg <= 1'b0; - qsfp1_reset_reg <= 1'b0; - qsfp2_reset_reg <= 1'b0; - qsfp3_reset_reg <= 1'b0; - - qsfp0_lpmode_reg <= 1'b0; - qsfp1_lpmode_reg <= 1'b0; - qsfp2_lpmode_reg <= 1'b0; - qsfp3_lpmode_reg <= 1'b0; - - eeprom_i2c_scl_o_reg <= 1'b1; - eeprom_i2c_sda_o_reg <= 1'b1; - - qsfp0_i2c_scl_o_reg <= 1'b1; - qsfp0_i2c_sda_o_reg <= 1'b1; - - qsfp1_i2c_scl_o_reg <= 1'b1; - qsfp1_i2c_sda_o_reg <= 1'b1; - - qsfp2_i2c_scl_o_reg <= 1'b1; - qsfp2_i2c_sda_o_reg <= 1'b1; - - qsfp3_i2c_scl_o_reg <= 1'b1; - qsfp3_i2c_sda_o_reg <= 1'b1; - - fpga_boot_reg <= 1'b0; - - qspi_clk_reg <= 1'b0; - qspi_cs_reg <= 1'b1; - qspi_dq_o_reg <= 4'd0; - qspi_dq_oe_reg <= 4'd0; - end -end - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP0_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP1_BASE) -) -qsfp0_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp0_drp_reg_wr_wait), - .reg_wr_ack(qsfp0_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp0_drp_reg_rd_data), - .reg_rd_wait(qsfp0_drp_reg_rd_wait), - .reg_rd_ack(qsfp0_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy) -); - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP1_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP2_BASE) -) -qsfp1_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp1_drp_reg_wr_wait), - .reg_wr_ack(qsfp1_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp1_drp_reg_rd_data), - .reg_rd_wait(qsfp1_drp_reg_rd_wait), - .reg_rd_ack(qsfp1_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy) -); - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP2_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP3_BASE) -) -qsfp2_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp2_drp_reg_wr_wait), - .reg_wr_ack(qsfp2_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp2_drp_reg_rd_data), - .reg_rd_wait(qsfp2_drp_reg_rd_wait), - .reg_rd_ack(qsfp2_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp2_drp_clk), - .drp_rst(qsfp2_drp_rst), - .drp_addr(qsfp2_drp_addr), - .drp_di(qsfp2_drp_di), - .drp_en(qsfp2_drp_en), - .drp_we(qsfp2_drp_we), - .drp_do(qsfp2_drp_do), - .drp_rdy(qsfp2_drp_rdy) -); - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP3_BASE), - .RB_NEXT_PTR(0) -) -qsfp3_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp3_drp_reg_wr_wait), - .reg_wr_ack(qsfp3_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp3_drp_reg_rd_data), - .reg_rd_wait(qsfp3_drp_reg_rd_wait), - .reg_rd_ack(qsfp3_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp3_drp_clk), - .drp_rst(qsfp3_drp_rst), - .drp_addr(qsfp3_drp_addr), - .drp_di(qsfp3_drp_di), - .drp_en(qsfp3_drp_en), - .drp_we(qsfp3_drp_we), - .drp_do(qsfp3_drp_do), - .drp_rdy(qsfp3_drp_rdy) -); - -generate - -if (TDMA_BER_ENABLE) begin - - // BER tester - tdma_ber #( - .COUNT(16), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(16)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) - ) - tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp3_rx_error_count_4, qsfp3_rx_error_count_3, qsfp3_rx_error_count_2, qsfp3_rx_error_count_1, qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_cfg_tx_prbs31_enable({qsfp3_cfg_tx_prbs31_enable_4, qsfp3_cfg_tx_prbs31_enable_3, qsfp3_cfg_tx_prbs31_enable_2, qsfp3_cfg_tx_prbs31_enable_1, qsfp2_cfg_tx_prbs31_enable_4, qsfp2_cfg_tx_prbs31_enable_3, qsfp2_cfg_tx_prbs31_enable_2, qsfp2_cfg_tx_prbs31_enable_1, qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}), - .phy_cfg_rx_prbs31_enable({qsfp3_cfg_rx_prbs31_enable_4, qsfp3_cfg_rx_prbs31_enable_3, qsfp3_cfg_rx_prbs31_enable_2, qsfp3_cfg_rx_prbs31_enable_1, qsfp2_cfg_rx_prbs31_enable_4, qsfp2_cfg_rx_prbs31_enable_3, qsfp2_cfg_rx_prbs31_enable_2, qsfp2_cfg_rx_prbs31_enable_1, qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_tod), - .ptp_ts_step(ptp_sync_ts_tod_step) - ); - -end else begin - - assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0; - assign qsfp2_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp2_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp2_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp2_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp2_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp2_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp2_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp2_cfg_rx_prbs31_enable_4 = 1'b0; - assign qsfp3_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp3_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp3_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp3_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp3_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp3_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp3_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp3_cfg_rx_prbs31_enable_4 = 1'b0; - -end - -endgenerate - -assign led[2:0] = 3'b111; -assign led[3] = !ptp_pps_str; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -wire [PORT_COUNT-1:0] port_xgmii_tx_clk; -wire [PORT_COUNT-1:0] port_xgmii_tx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; - -wire [PORT_COUNT-1:0] port_xgmii_rx_clk; -wire [PORT_COUNT-1:0] port_xgmii_rx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; - -mqnic_port_map_phy_xgmii #( - .PHY_COUNT(16), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(4), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), - .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) -) -mqnic_port_map_phy_xgmii_inst ( - // towards PHY - .phy_xgmii_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_xgmii_tx_rst({qsfp3_tx_rst_4, qsfp3_tx_rst_3, qsfp3_tx_rst_2, qsfp3_tx_rst_1, qsfp2_tx_rst_4, qsfp2_tx_rst_3, qsfp2_tx_rst_2, qsfp2_tx_rst_1, qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}), - .phy_xgmii_txd({qsfp3_txd_4, qsfp3_txd_3, qsfp3_txd_2, qsfp3_txd_1, qsfp2_txd_4, qsfp2_txd_3, qsfp2_txd_2, qsfp2_txd_1, qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}), - .phy_xgmii_txc({qsfp3_txc_4, qsfp3_txc_3, qsfp3_txc_2, qsfp3_txc_1, qsfp2_txc_4, qsfp2_txc_3, qsfp2_txc_2, qsfp2_txc_1, qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}), - .phy_tx_status(16'hffff), - - .phy_xgmii_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_xgmii_rx_rst({qsfp3_rx_rst_4, qsfp3_rx_rst_3, qsfp3_rx_rst_2, qsfp3_rx_rst_1, qsfp2_rx_rst_4, qsfp2_rx_rst_3, qsfp2_rx_rst_2, qsfp2_rx_rst_1, qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}), - .phy_xgmii_rxd({qsfp3_rxd_4, qsfp3_rxd_3, qsfp3_rxd_2, qsfp3_rxd_1, qsfp2_rxd_4, qsfp2_rxd_3, qsfp2_rxd_2, qsfp2_rxd_1, qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}), - .phy_xgmii_rxc({qsfp3_rxc_4, qsfp3_rxc_3, qsfp3_rxc_2, qsfp3_rxc_1, qsfp2_rxc_4, qsfp2_rxc_3, qsfp2_rxc_2, qsfp2_rxc_1, qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}), - .phy_rx_status({qsfp3_rx_status_4, qsfp3_rx_status_3, qsfp3_rx_status_2, qsfp3_rx_status_1, qsfp2_rx_status_4, qsfp2_rx_status_3, qsfp2_rx_status_2, qsfp2_rx_status_1, qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}), - - // towards MAC - .port_xgmii_tx_clk(port_xgmii_tx_clk), - .port_xgmii_tx_rst(port_xgmii_tx_rst), - .port_xgmii_txd(port_xgmii_txd), - .port_xgmii_txc(port_xgmii_txc), - .port_tx_status(eth_tx_status), - - .port_xgmii_rx_clk(port_xgmii_rx_clk), - .port_xgmii_rx_rst(port_xgmii_rx_rst), - .port_xgmii_rxd(port_xgmii_rxd), - .port_xgmii_rxc(port_xgmii_rxc), - .port_rx_status(eth_rx_status) -); - -generate - genvar n; - - for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac - - assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; - assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; - assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; - assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; - - eth_mac_10g #( - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .ENABLE_PADDING(ENABLE_PADDING), - .ENABLE_DIC(ENABLE_DIC), - .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), - .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), - .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_PTP_TS_CTRL_IN_TUSER(0), - .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), - .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .PFC_ENABLE(PFC_ENABLE), - .PAUSE_ENABLE(LFC_ENABLE) - ) - eth_mac_inst ( - .tx_clk(port_xgmii_tx_clk[n]), - .tx_rst(port_xgmii_tx_rst[n]), - .rx_clk(port_xgmii_rx_clk[n]), - .rx_rst(port_xgmii_rx_rst[n]), - - /* - * AXI input - */ - .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), - .tx_axis_tready(axis_eth_tx_tready[n +: 1]), - .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), - .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), - - /* - * AXI output - */ - .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), - .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), - .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), - - /* - * XGMII interface - */ - .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - - /* - * PTP - */ - .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), - .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), - - /* - * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) - */ - .tx_lfc_req(eth_tx_lfc_req[n +: 1]), - .tx_lfc_resend(1'b0), - .rx_lfc_en(eth_rx_lfc_en[n +: 1]), - .rx_lfc_req(eth_rx_lfc_req[n +: 1]), - .rx_lfc_ack(eth_rx_lfc_ack[n +: 1]), - - /* - * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) - */ - .tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]), - .tx_pfc_resend(1'b0), - .rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]), - .rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]), - .rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]), - - /* - * Pause interface - */ - .tx_lfc_pause_en(1'b1), - .tx_pause_req(1'b0), - .tx_pause_ack(), - - /* - * Status - */ - .tx_start_packet(), - .tx_error_underflow(), - .rx_start_packet(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - .stat_tx_mcf(), - .stat_rx_mcf(), - .stat_tx_lfc_pkt(), - .stat_tx_lfc_xon(), - .stat_tx_lfc_xoff(), - .stat_tx_lfc_paused(), - .stat_tx_pfc_pkt(), - .stat_tx_pfc_xon(), - .stat_tx_pfc_xoff(), - .stat_tx_pfc_paused(), - .stat_rx_lfc_pkt(), - .stat_rx_lfc_xon(), - .stat_rx_lfc_xoff(), - .stat_rx_lfc_paused(), - .stat_rx_pfc_pkt(), - .stat_rx_pfc_xon(), - .stat_rx_pfc_xoff(), - .stat_rx_pfc_paused(), - - /* - * Configuration - */ - .cfg_ifg(8'd12), - .cfg_tx_enable(eth_tx_enable[n +: 1]), - .cfg_rx_enable(eth_rx_enable[n +: 1]), - .cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01), - .cfg_mcf_rx_check_eth_dst_mcast(1'b1), - .cfg_mcf_rx_eth_dst_ucast(48'd0), - .cfg_mcf_rx_check_eth_dst_ucast(1'b0), - .cfg_mcf_rx_eth_src(48'd0), - .cfg_mcf_rx_check_eth_src(1'b0), - .cfg_mcf_rx_eth_type(16'h8808), - .cfg_mcf_rx_opcode_lfc(16'h0001), - .cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]), - .cfg_mcf_rx_opcode_pfc(16'h0101), - .cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0), - .cfg_mcf_rx_forward(1'b0), - .cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]), - .cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01), - .cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C), - .cfg_tx_lfc_eth_type(16'h8808), - .cfg_tx_lfc_opcode(16'h0001), - .cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]), - .cfg_tx_lfc_quanta(16'hffff), - .cfg_tx_lfc_refresh(16'h7fff), - .cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01), - .cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C), - .cfg_tx_pfc_eth_type(16'h8808), - .cfg_tx_pfc_opcode(16'h0101), - .cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0), - .cfg_tx_pfc_quanta({8{16'hffff}}), - .cfg_tx_pfc_refresh({8{16'h7fff}}), - .cfg_rx_lfc_opcode(16'h0001), - .cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]), - .cfg_rx_pfc_opcode(16'h0101), - .cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0) - ); - - end - -endgenerate - -mqnic_core_pcie_us #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(0), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .DDR_GROUP_SIZE(1), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_AWUSER_ENABLE(0), - .AXI_DDR_WUSER_ENABLE(0), - .AXI_DDR_BUSER_ENABLE(0), - .AXI_DDR_ARUSER_ENABLE(0), - .AXI_DDR_RUSER_ENABLE(0), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - .AXI_DDR_FIXED_BURST(0), - .AXI_DDR_WRAP_BURST(1), - .HBM_ENABLE(0), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * AXI input (RC) - */ - .s_axis_rc_tdata(s_axis_rc_tdata), - .s_axis_rc_tkeep(s_axis_rc_tkeep), - .s_axis_rc_tvalid(s_axis_rc_tvalid), - .s_axis_rc_tready(s_axis_rc_tready), - .s_axis_rc_tlast(s_axis_rc_tlast), - .s_axis_rc_tuser(s_axis_rc_tuser), - - /* - * AXI output (RQ) - */ - .m_axis_rq_tdata(m_axis_rq_tdata), - .m_axis_rq_tkeep(m_axis_rq_tkeep), - .m_axis_rq_tvalid(m_axis_rq_tvalid), - .m_axis_rq_tready(m_axis_rq_tready), - .m_axis_rq_tlast(m_axis_rq_tlast), - .m_axis_rq_tuser(m_axis_rq_tuser), - - /* - * AXI input (CQ) - */ - .s_axis_cq_tdata(s_axis_cq_tdata), - .s_axis_cq_tkeep(s_axis_cq_tkeep), - .s_axis_cq_tvalid(s_axis_cq_tvalid), - .s_axis_cq_tready(s_axis_cq_tready), - .s_axis_cq_tlast(s_axis_cq_tlast), - .s_axis_cq_tuser(s_axis_cq_tuser), - - /* - * AXI output (CC) - */ - .m_axis_cc_tdata(m_axis_cc_tdata), - .m_axis_cc_tkeep(m_axis_cc_tkeep), - .m_axis_cc_tvalid(m_axis_cc_tvalid), - .m_axis_cc_tready(m_axis_cc_tready), - .m_axis_cc_tlast(m_axis_cc_tlast), - .m_axis_cc_tuser(m_axis_cc_tuser), - - /* - * Transmit sequence number input - */ - .s_axis_rq_seq_num_0(s_axis_rq_seq_num), - .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid), - .s_axis_rq_seq_num_1(4'd0), - .s_axis_rq_seq_num_valid_1(1'b0), - - /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration inputs - */ - .cfg_max_read_req(cfg_max_read_req), - .cfg_max_payload(cfg_max_payload), - .cfg_rcb_status(cfg_rcb_status), - - /* - * Configuration interface - */ - .cfg_mgmt_addr(cfg_mgmt_addr[9:0]), - .cfg_mgmt_function_number(cfg_mgmt_addr[17:10]), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - /* - * Interrupt interface - */ - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(), - .cfg_interrupt_msix_vec_pending_status(1'b0), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - /* - * PCIe error outputs - */ - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(axil_csr_awaddr), - .m_axil_csr_awprot(axil_csr_awprot), - .m_axil_csr_awvalid(axil_csr_awvalid), - .m_axil_csr_awready(axil_csr_awready), - .m_axil_csr_wdata(axil_csr_wdata), - .m_axil_csr_wstrb(axil_csr_wstrb), - .m_axil_csr_wvalid(axil_csr_wvalid), - .m_axil_csr_wready(axil_csr_wready), - .m_axil_csr_bresp(axil_csr_bresp), - .m_axil_csr_bvalid(axil_csr_bvalid), - .m_axil_csr_bready(axil_csr_bready), - .m_axil_csr_araddr(axil_csr_araddr), - .m_axil_csr_arprot(axil_csr_arprot), - .m_axil_csr_arvalid(axil_csr_arvalid), - .m_axil_csr_arready(axil_csr_arready), - .m_axil_csr_rdata(axil_csr_rdata), - .m_axil_csr_rresp(axil_csr_rresp), - .m_axil_csr_rvalid(axil_csr_rvalid), - .m_axil_csr_rready(axil_csr_rready), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_td_sd(ptp_td_sd), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_sync_locked(ptp_sync_locked), - .ptp_sync_ts_rel(ptp_sync_ts_rel), - .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), - .ptp_sync_ts_tod(ptp_sync_ts_tod), - .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_pps_str(ptp_sync_pps_str), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(0), - .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), - .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(0), - .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), - .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * HBM - */ - .hbm_clk(0), - .hbm_rst(0), - - .m_axi_hbm_awid(), - .m_axi_hbm_awaddr(), - .m_axi_hbm_awlen(), - .m_axi_hbm_awsize(), - .m_axi_hbm_awburst(), - .m_axi_hbm_awlock(), - .m_axi_hbm_awcache(), - .m_axi_hbm_awprot(), - .m_axi_hbm_awqos(), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(), - .m_axi_hbm_awready(0), - .m_axi_hbm_wdata(), - .m_axi_hbm_wstrb(), - .m_axi_hbm_wlast(), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(), - .m_axi_hbm_wready(0), - .m_axi_hbm_bid(0), - .m_axi_hbm_bresp(0), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(0), - .m_axi_hbm_bready(), - .m_axi_hbm_arid(), - .m_axi_hbm_araddr(), - .m_axi_hbm_arlen(), - .m_axi_hbm_arsize(), - .m_axi_hbm_arburst(), - .m_axi_hbm_arlock(), - .m_axi_hbm_arcache(), - .m_axi_hbm_arprot(), - .m_axi_hbm_arqos(), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(), - .m_axi_hbm_arready(0), - .m_axi_hbm_rid(0), - .m_axi_hbm_rdata(0), - .m_axi_hbm_rresp(0), - .m_axi_hbm_rlast(0), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(0), - .m_axi_hbm_rready(), - - .hbm_status(0), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -assign cfg_mgmt_addr[18] = 1'b0; - -endmodule - -`resetall diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile deleted file mode 100644 index 74cae1598..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile +++ /dev/null @@ -1,261 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rb_drp.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 2 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 -export PARAM_PTP_CLOCK_PIPELINE := 0 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 0 -export PARAM_PTP_PEROUT_ENABLE := 1 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 5 -export PARAM_TX_QUEUE_INDEX_WIDTH := 11 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 32768 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_AXIS_PCIE_DATA_WIDTH := 256 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 0 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0 -export PARAM_AXIS_ETH_RX_PIPELINE := 0 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 1cfd089ce..000000000 --- a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,787 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import struct -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus -from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.xilinx.us import UltraScalePcieDevice - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = UltraScalePcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=8, - user_clk_frequency=250e6, - alignment="dword", - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - pf_count=1, - max_payload_size=1024, - enable_client_tag=True, - enable_extended_tag=True, - enable_parity=False, - enable_rx_msg_interface=False, - enable_sriov=False, - enable_extended_configuration=False, - - pf0_msi_enable=False, - pf0_msi_count=32, - pf1_msi_enable=False, - pf1_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - - # signals - # Clock and Reset Interface - user_clk=dut.clk_250mhz, - user_reset=dut.rst_250mhz, - # user_lnk_up - # sys_clk - # sys_clk_gt - # sys_reset - # phy_rdy_out - - # Requester reQuest Interface - rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), - pcie_rq_seq_num=dut.s_axis_rq_seq_num, - pcie_rq_seq_num_vld=dut.s_axis_rq_seq_num_valid, - # pcie_rq_tag - # pcie_rq_tag_av - # pcie_rq_tag_vld - - # Requester Completion Interface - rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), - - # Completer reQuest Interface - cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - # pcie_cq_np_req - # pcie_cq_np_req_count - - # Completer Completion Interface - cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), - - # Transmit Flow Control Interface - # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, - # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, - - # Configuration Management Interface - cfg_mgmt_addr=dut.cfg_mgmt_addr, - cfg_mgmt_write=dut.cfg_mgmt_write, - cfg_mgmt_write_data=dut.cfg_mgmt_write_data, - cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, - cfg_mgmt_read=dut.cfg_mgmt_read, - cfg_mgmt_read_data=dut.cfg_mgmt_read_data, - cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, - # cfg_mgmt_debug_access - - # Configuration Status Interface - # cfg_phy_link_down - # cfg_phy_link_status - # cfg_negotiated_width - # cfg_current_speed - cfg_max_payload=dut.cfg_max_payload, - cfg_max_read_req=dut.cfg_max_read_req, - # cfg_function_status - # cfg_vf_status - # cfg_function_power_state - # cfg_vf_power_state - # cfg_link_power_state - # cfg_err_cor_out - # cfg_err_nonfatal_out - # cfg_err_fatal_out - # cfg_local_error_out - # cfg_local_error_valid - # cfg_rx_pm_state - # cfg_tx_pm_state - # cfg_ltssm_state - cfg_rcb_status=dut.cfg_rcb_status, - # cfg_obff_enable - # cfg_pl_status_change - # cfg_tph_requester_enable - # cfg_tph_st_mode - # cfg_vf_tph_requester_enable - # cfg_vf_tph_st_mode - - # Configuration Received Message Interface - # cfg_msg_received - # cfg_msg_received_data - # cfg_msg_received_type - - # Configuration Transmit Message Interface - # cfg_msg_transmit - # cfg_msg_transmit_type - # cfg_msg_transmit_data - # cfg_msg_transmit_done - - # Configuration Flow Control Interface - cfg_fc_ph=dut.cfg_fc_ph, - cfg_fc_pd=dut.cfg_fc_pd, - cfg_fc_nph=dut.cfg_fc_nph, - cfg_fc_npd=dut.cfg_fc_npd, - cfg_fc_cplh=dut.cfg_fc_cplh, - cfg_fc_cpld=dut.cfg_fc_cpld, - cfg_fc_sel=dut.cfg_fc_sel, - - # Configuration Control Interface - # cfg_hot_reset_in - # cfg_hot_reset_out - # cfg_config_space_enable - # cfg_dsn - # cfg_bus_number - # cfg_ds_port_number - # cfg_ds_bus_number - # cfg_ds_device_number - # cfg_ds_function_number - # cfg_power_state_change_ack - # cfg_power_state_change_interrupt - cfg_err_cor_in=dut.status_error_cor, - cfg_err_uncor_in=dut.status_error_uncor, - # cfg_flr_in_process - # cfg_flr_done - # cfg_vf_flr_in_process - # cfg_vf_flr_func_num - # cfg_vf_flr_done - # cfg_pm_aspm_l1_entry_reject - # cfg_pm_aspm_tx_l0s_entry_disable - # cfg_req_pm_transition_l23_ready - # cfg_link_training_enable - - # Configuration Interrupt Controller Interface - # cfg_interrupt_int - # cfg_interrupt_sent - # cfg_interrupt_pending - # cfg_interrupt_msi_enable - # cfg_interrupt_msi_vf_enable - # cfg_interrupt_msi_mmenable - # cfg_interrupt_msi_mask_update - # cfg_interrupt_msi_data - # cfg_interrupt_msi_select - # cfg_interrupt_msi_int - # cfg_interrupt_msi_pending_status - # cfg_interrupt_msi_pending_status_data_enable - # cfg_interrupt_msi_pending_status_function_num - # cfg_interrupt_msi_sent - # cfg_interrupt_msi_fail - cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, - cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, - cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, - cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, - cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, - cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, - cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, - cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, - cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, - # cfg_interrupt_msi_attr - # cfg_interrupt_msi_tph_present - # cfg_interrupt_msi_tph_type - # cfg_interrupt_msi_tph_st_tag - cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, - - # Configuration Extend Interface - # cfg_ext_read_received - # cfg_ext_write_received - # cfg_ext_register_number - # cfg_ext_function_number - # cfg_ext_write_data - # cfg_ext_write_byte_enable - # cfg_ext_read_data - # cfg_ext_read_data_valid - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 3.102, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) - - # Ethernet - self.qsfp_source = [] - self.qsfp_sink = [] - - for x in range(4): - sources = [] - sinks = [] - for y in range(1, 5): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) - source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) - sources.append(source) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) - sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) - sinks.append(sink) - getattr(dut, f"qsfp{x}_rx_status_{y}").setimmediatevalue(1) - getattr(dut, f"qsfp{x}_rx_error_count_{y}").setimmediatevalue(0) - self.qsfp_source.append(sources) - self.qsfp_sink.append(sinks) - - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_drp_clk"), 8, units="ns").start()) - getattr(dut, f"qsfp{x}_drp_rst").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_drp_do").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_drp_rdy").setimmediatevalue(0) - - getattr(dut, f"qsfp{x}_modprsl").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_intl").setimmediatevalue(1) - getattr(dut, f"qsfp{x}_i2c_scl_i").setimmediatevalue(1) - getattr(dut, f"qsfp{x}_i2c_sda_i").setimmediatevalue(1) - - dut.eeprom_i2c_scl_i.setimmediatevalue(1) - dut.eeprom_i2c_sda_i.setimmediatevalue(1) - - dut.ext_pps_in.setimmediatevalue(0) - dut.ext_clk_in.setimmediatevalue(0) - - dut.qspi_dq_i.setimmediatevalue(0) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - for x in range(4): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - for x in range(4): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(1) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - for x in range(4): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - for x in range(len(self.qsfp_sink)): - for y in range(len(self.qsfp_sink[x])): - if not self.qsfp_sink[x][y].empty(): - await self.qsfp_source[x][y].send(await self.qsfp_sink[x][y].recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - # await tb.driver.interfaces[1].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfp_sink[0][0].recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_source[0][0].send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - # await tb.driver.interfaces[1].start_xmit(data, 0) - - # pkt = await tb.qsfp_sink[1][0].recv() - # tb.log.info("Packet: %s", pkt) - - # await tb.qsfp_source[1][0].send(pkt) - - # pkt = await tb.driver.interfaces[1].recv() - - # tb.log.info("Packet: %s", pkt) - # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfp_sink[0][0].recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_source[0][0].send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - if tb.driver.interfaces[0].if_feature_lfc: - tb.log.info("Test LFC pause frame RX") - - await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN) - await tb.driver.hw_regs.read_dword(0) - - lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000) - - await tb.qsfp_source[0][0].send(XgmiiFrame.from_payload(bytes(lfc_xoff))) - - count = 16 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - if tb.driver.interfaces[0].if_feature_rx_csum: - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "rb_drp.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "tdma_scheduler.v"), - os.path.join(rtl_dir, "common", "tdma_ber.v"), - os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"), - os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), - os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_td_phc.v"), - os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 2 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 512 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 - parameters['PTP_CLOCK_PIPELINE'] = 0 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 0 - parameters['PTP_PEROUT_ENABLE'] = 0 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 9 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 32768 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['AXIS_PCIE_DATA_WIDTH'] = 256 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 0 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0 - parameters['AXIS_ETH_RX_PIPELINE'] = 0 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - )