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Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters

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This commit is contained in:
Alex Forencich 2021-09-08 00:18:11 -07:00
parent c00a53155d
commit cef144e376
19 changed files with 68 additions and 2 deletions
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4
fpga/common/rtl/mqnic_core_pcie.v
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@ -107,6 +107,8 @@ module mqnic_core_pcie #
parameter RX_RAM_SIZE = 32768,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
@ -350,8 +352,6 @@ module mqnic_core_pcie #
);
parameter DMA_ADDR_WIDTH = 64;
parameter DMA_LEN_WIDTH = 16;
parameter DMA_TAG_WIDTH = 16;
parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2;
parameter RAM_SEG_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH*2/RAM_SEG_COUNT;

4
fpga/common/rtl/mqnic_core_pcie_us.v
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@ -107,6 +107,8 @@ module mqnic_core_pcie_us #
parameter RX_RAM_SIZE = 32768,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
@ -696,6 +698,8 @@ mqnic_core_pcie #(
.RX_RAM_SIZE(RX_RAM_SIZE),
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration

6
fpga/common/tb/mqnic_core_pcie_us/Makefile
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@ -164,6 +164,8 @@ export PARAM_TX_RAM_SIZE ?= 131072
export PARAM_RX_RAM_SIZE ?= 131072
# DMA interface configuration
export PARAM_DMA_LEN_WIDTH ?= 16
export PARAM_DMA_TAG_WIDTH ?= 16
export PARAM_RAM_PIPELINE ?= 2
# PCIe interface configuration
@ -240,6 +242,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@ -312,6 +316,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)

2
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -645,6 +645,8 @@ def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width,
parameters['RX_RAM_SIZE'] = 131072
# DMA interface configuration
parameters['DMA_LEN_WIDTH'] = 16
parameters['DMA_TAG_WIDTH'] = 16
parameters['RAM_PIPELINE'] = 2
# PCIe interface configuration

2
fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
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@ -94,6 +94,8 @@ dict set params TX_RAM_SIZE "131072"
dict set params RX_RAM_SIZE "131072"
# DMA interface configuration
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_PIPELINE "2"
# PCIe interface configuration

4
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
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@ -98,6 +98,8 @@ module fpga #
parameter RX_RAM_SIZE = 131072,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
@ -1698,6 +1700,8 @@ fpga_core #(
.RX_RAM_SIZE(RX_RAM_SIZE),
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration

4
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
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@ -106,6 +106,8 @@ module fpga_core #
parameter RX_RAM_SIZE = 131072,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
@ -824,6 +826,8 @@ mqnic_core_pcie_us #(
.RX_RAM_SIZE(RX_RAM_SIZE),
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration

6
fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
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@ -166,6 +166,8 @@ export PARAM_TX_RAM_SIZE ?= 131072
export PARAM_RX_RAM_SIZE ?= 131072
# DMA interface configuration
export PARAM_DMA_LEN_WIDTH ?= 16
export PARAM_DMA_TAG_WIDTH ?= 16
export PARAM_RAM_PIPELINE ?= 2
# PCIe interface configuration
@ -234,6 +236,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@ -300,6 +304,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)

2
fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
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@ -648,6 +648,8 @@ def test_fpga_core(request):
parameters['RX_RAM_SIZE'] = 131072
# DMA interface configuration
parameters['DMA_LEN_WIDTH'] = 16
parameters['DMA_TAG_WIDTH'] = 16
parameters['RAM_PIPELINE'] = 2
# PCIe interface configuration

2
fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl
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@ -111,6 +111,8 @@ dict set params TX_RAM_SIZE "32768"
dict set params RX_RAM_SIZE "32768"
# DMA interface configuration
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_PIPELINE "2"
# PCIe interface configuration

4
fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v
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@ -98,6 +98,8 @@ module fpga #
parameter RX_RAM_SIZE = 32768,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
@ -1618,6 +1620,8 @@ fpga_core #(
.RX_RAM_SIZE(RX_RAM_SIZE),
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration

4
fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v
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@ -111,6 +111,8 @@ module fpga_core #
parameter RX_RAM_SIZE = 32768,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
@ -1082,6 +1084,8 @@ mqnic_core_pcie_us #(
.RX_RAM_SIZE(RX_RAM_SIZE),
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration

6
fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile
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@ -173,6 +173,8 @@ export PARAM_TX_RAM_SIZE ?= 32768
export PARAM_RX_RAM_SIZE ?= 32768
# DMA interface configuration
export PARAM_DMA_LEN_WIDTH ?= 16
export PARAM_DMA_TAG_WIDTH ?= 16
export PARAM_RAM_PIPELINE ?= 2
# PCIe interface configuration
@ -241,6 +243,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@ -307,6 +311,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)

2
fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py
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@ -697,6 +697,8 @@ def test_fpga_core(request):
parameters['RX_RAM_SIZE'] = 32768
# DMA interface configuration
parameters['DMA_LEN_WIDTH'] = 16
parameters['DMA_TAG_WIDTH'] = 16
parameters['RAM_PIPELINE'] = 2
# PCIe interface configuration

2
fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
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@ -111,6 +111,8 @@ dict set params TX_RAM_SIZE "32768"
dict set params RX_RAM_SIZE "32768"
# DMA interface configuration
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_PIPELINE "2"
# PCIe interface configuration

4
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
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@ -98,6 +98,8 @@ module fpga #
parameter RX_RAM_SIZE = 32768,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
@ -1634,6 +1636,8 @@ fpga_core #(
.RX_RAM_SIZE(RX_RAM_SIZE),
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration

4
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -111,6 +111,8 @@ module fpga_core #
parameter RX_RAM_SIZE = 32768,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
@ -1082,6 +1084,8 @@ mqnic_core_pcie_us #(
.RX_RAM_SIZE(RX_RAM_SIZE),
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration

6
fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
View File

@ -173,6 +173,8 @@ export PARAM_TX_RAM_SIZE ?= 32768
export PARAM_RX_RAM_SIZE ?= 32768
# DMA interface configuration
export PARAM_DMA_LEN_WIDTH ?= 16
export PARAM_DMA_TAG_WIDTH ?= 16
export PARAM_RAM_PIPELINE ?= 2
# PCIe interface configuration
@ -241,6 +243,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@ -307,6 +311,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)

2
fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
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@ -697,6 +697,8 @@ def test_fpga_core(request):
parameters['RX_RAM_SIZE'] = 32768
# DMA interface configuration
parameters['DMA_LEN_WIDTH'] = 16
parameters['DMA_TAG_WIDTH'] = 16
parameters['RAM_PIPELINE'] = 2
# PCIe interface configuration