From cef144e3760183654dba0509c5a94d56bc709d15 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 8 Sep 2021 00:18:11 -0700
Subject: [PATCH] Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters

---
 fpga/common/rtl/mqnic_core_pcie.v                           | 4 ++--
 fpga/common/rtl/mqnic_core_pcie_us.v                        | 4 ++++
 fpga/common/tb/mqnic_core_pcie_us/Makefile                  | 6 ++++++
 .../common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 2 ++
 fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl                  | 2 ++
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v                       | 4 ++++
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v                  | 4 ++++
 fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile            | 6 ++++++
 fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py   | 2 ++
 fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl                   | 2 ++
 fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v                        | 4 ++++
 fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v                   | 4 ++++
 fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile             | 6 ++++++
 fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py    | 2 ++
 fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl                   | 2 ++
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v                        | 4 ++++
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v                   | 4 ++++
 fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile             | 6 ++++++
 fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py    | 2 ++
 19 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v
index 3b9db705f..540dcea39 100644
--- a/fpga/common/rtl/mqnic_core_pcie.v
+++ b/fpga/common/rtl/mqnic_core_pcie.v
@@ -107,6 +107,8 @@ module mqnic_core_pcie #
     parameter RX_RAM_SIZE = 32768,
 
     // DMA interface configuration
+    parameter DMA_LEN_WIDTH = 16,
+    parameter DMA_TAG_WIDTH = 16,
     parameter RAM_PIPELINE = 2,
 
     // PCIe interface configuration
@@ -350,8 +352,6 @@ module mqnic_core_pcie #
 );
 
 parameter DMA_ADDR_WIDTH = 64;
-parameter DMA_LEN_WIDTH = 16;
-parameter DMA_TAG_WIDTH = 16;
 
 parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2;
 parameter RAM_SEG_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH*2/RAM_SEG_COUNT;
diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v
index 925731866..6475163a8 100644
--- a/fpga/common/rtl/mqnic_core_pcie_us.v
+++ b/fpga/common/rtl/mqnic_core_pcie_us.v
@@ -107,6 +107,8 @@ module mqnic_core_pcie_us #
     parameter RX_RAM_SIZE = 32768,
 
     // DMA interface configuration
+    parameter DMA_LEN_WIDTH = 16,
+    parameter DMA_TAG_WIDTH = 16,
     parameter RAM_PIPELINE = 2,
 
     // PCIe interface configuration
@@ -696,6 +698,8 @@ mqnic_core_pcie #(
     .RX_RAM_SIZE(RX_RAM_SIZE),
 
     // DMA interface configuration
+    .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
+    .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_PIPELINE(RAM_PIPELINE),
 
     // PCIe interface configuration
diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile
index a5a7f66ad..06e3fa6e3 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile
@@ -164,6 +164,8 @@ export PARAM_TX_RAM_SIZE ?= 131072
 export PARAM_RX_RAM_SIZE ?= 131072
 
 # DMA interface configuration
+export PARAM_DMA_LEN_WIDTH ?= 16
+export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_PIPELINE ?= 2
 
 # PCIe interface configuration
@@ -240,6 +242,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
 	COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
 	COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@@ -312,6 +316,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
 	COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
 	COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
+	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
+	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
 	COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
 	COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index b61618ea4..21dc50858 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -645,6 +645,8 @@ def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width,
     parameters['RX_RAM_SIZE'] = 131072
 
     # DMA interface configuration
+    parameters['DMA_LEN_WIDTH'] = 16
+    parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_PIPELINE'] = 2
 
     # PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
index 21a53685c..ba0d11f78 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
@@ -94,6 +94,8 @@ dict set params TX_RAM_SIZE "131072"
 dict set params RX_RAM_SIZE "131072"
 
 # DMA interface configuration
+dict set params DMA_LEN_WIDTH "16"
+dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
index 8e4627c59..ce7e4d422 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
@@ -98,6 +98,8 @@ module fpga #
     parameter RX_RAM_SIZE = 131072,
 
     // DMA interface configuration
+    parameter DMA_LEN_WIDTH = 16,
+    parameter DMA_TAG_WIDTH = 16,
     parameter RAM_PIPELINE = 2,
 
     // PCIe interface configuration
@@ -1698,6 +1700,8 @@ fpga_core #(
     .RX_RAM_SIZE(RX_RAM_SIZE),
 
     // DMA interface configuration
+    .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
+    .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_PIPELINE(RAM_PIPELINE),
 
     // PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
index 865d45bbc..91ab720d2 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
@@ -106,6 +106,8 @@ module fpga_core #
     parameter RX_RAM_SIZE = 131072,
 
     // DMA interface configuration
+    parameter DMA_LEN_WIDTH = 16,
+    parameter DMA_TAG_WIDTH = 16,
     parameter RAM_PIPELINE = 2,
 
     // PCIe interface configuration
@@ -824,6 +826,8 @@ mqnic_core_pcie_us #(
     .RX_RAM_SIZE(RX_RAM_SIZE),
 
     // DMA interface configuration
+    .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
+    .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_PIPELINE(RAM_PIPELINE),
 
     // PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
index 13c876d88..6d44aa6ab 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
@@ -166,6 +166,8 @@ export PARAM_TX_RAM_SIZE ?= 131072
 export PARAM_RX_RAM_SIZE ?= 131072
 
 # DMA interface configuration
+export PARAM_DMA_LEN_WIDTH ?= 16
+export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_PIPELINE ?= 2
 
 # PCIe interface configuration
@@ -234,6 +236,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
 	COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
 	COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@@ -300,6 +304,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
 	COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
 	COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
+	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
+	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
 	COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
 	COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
index 5ece45ad8..6e363479e 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -648,6 +648,8 @@ def test_fpga_core(request):
     parameters['RX_RAM_SIZE'] = 131072
 
     # DMA interface configuration
+    parameters['DMA_LEN_WIDTH'] = 16
+    parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_PIPELINE'] = 2
 
     # PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl
index cce2200a4..52da915cb 100644
--- a/fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl
@@ -111,6 +111,8 @@ dict set params TX_RAM_SIZE "32768"
 dict set params RX_RAM_SIZE "32768"
 
 # DMA interface configuration
+dict set params DMA_LEN_WIDTH "16"
+dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v
index 64d972a3a..ee39db286 100644
--- a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v
@@ -98,6 +98,8 @@ module fpga #
     parameter RX_RAM_SIZE = 32768,
 
     // DMA interface configuration
+    parameter DMA_LEN_WIDTH = 16,
+    parameter DMA_TAG_WIDTH = 16,
     parameter RAM_PIPELINE = 2,
 
     // PCIe interface configuration
@@ -1618,6 +1620,8 @@ fpga_core #(
     .RX_RAM_SIZE(RX_RAM_SIZE),
 
     // DMA interface configuration
+    .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
+    .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_PIPELINE(RAM_PIPELINE),
 
     // PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v
index 4a1346b98..5de9e51ca 100644
--- a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v
@@ -111,6 +111,8 @@ module fpga_core #
     parameter RX_RAM_SIZE = 32768,
 
     // DMA interface configuration
+    parameter DMA_LEN_WIDTH = 16,
+    parameter DMA_TAG_WIDTH = 16,
     parameter RAM_PIPELINE = 2,
 
     // PCIe interface configuration
@@ -1082,6 +1084,8 @@ mqnic_core_pcie_us #(
     .RX_RAM_SIZE(RX_RAM_SIZE),
 
     // DMA interface configuration
+    .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
+    .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_PIPELINE(RAM_PIPELINE),
 
     // PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile
index 497ee5f54..18dfa84a1 100644
--- a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile
@@ -173,6 +173,8 @@ export PARAM_TX_RAM_SIZE ?= 32768
 export PARAM_RX_RAM_SIZE ?= 32768
 
 # DMA interface configuration
+export PARAM_DMA_LEN_WIDTH ?= 16
+export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_PIPELINE ?= 2
 
 # PCIe interface configuration
@@ -241,6 +243,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
 	COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
 	COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@@ -307,6 +311,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
 	COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
 	COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
+	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
+	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
 	COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
 	COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
diff --git a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py
index 3ae2619a8..c96a17840 100644
--- a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -697,6 +697,8 @@ def test_fpga_core(request):
     parameters['RX_RAM_SIZE'] = 32768
 
     # DMA interface configuration
+    parameters['DMA_LEN_WIDTH'] = 16
+    parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_PIPELINE'] = 2
 
     # PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
index cce2200a4..52da915cb 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
@@ -111,6 +111,8 @@ dict set params TX_RAM_SIZE "32768"
 dict set params RX_RAM_SIZE "32768"
 
 # DMA interface configuration
+dict set params DMA_LEN_WIDTH "16"
+dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
index 950d1717e..873bd0efa 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
@@ -98,6 +98,8 @@ module fpga #
     parameter RX_RAM_SIZE = 32768,
 
     // DMA interface configuration
+    parameter DMA_LEN_WIDTH = 16,
+    parameter DMA_TAG_WIDTH = 16,
     parameter RAM_PIPELINE = 2,
 
     // PCIe interface configuration
@@ -1634,6 +1636,8 @@ fpga_core #(
     .RX_RAM_SIZE(RX_RAM_SIZE),
 
     // DMA interface configuration
+    .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
+    .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_PIPELINE(RAM_PIPELINE),
 
     // PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
index 503cfcdb2..cbf04dcfa 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
@@ -111,6 +111,8 @@ module fpga_core #
     parameter RX_RAM_SIZE = 32768,
 
     // DMA interface configuration
+    parameter DMA_LEN_WIDTH = 16,
+    parameter DMA_TAG_WIDTH = 16,
     parameter RAM_PIPELINE = 2,
 
     // PCIe interface configuration
@@ -1082,6 +1084,8 @@ mqnic_core_pcie_us #(
     .RX_RAM_SIZE(RX_RAM_SIZE),
 
     // DMA interface configuration
+    .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
+    .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_PIPELINE(RAM_PIPELINE),
 
     // PCIe interface configuration
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
index 497ee5f54..18dfa84a1 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
@@ -173,6 +173,8 @@ export PARAM_TX_RAM_SIZE ?= 32768
 export PARAM_RX_RAM_SIZE ?= 32768
 
 # DMA interface configuration
+export PARAM_DMA_LEN_WIDTH ?= 16
+export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_PIPELINE ?= 2
 
 # PCIe interface configuration
@@ -241,6 +243,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
 	COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
 	COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@@ -307,6 +311,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
 	COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
 	COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
+	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
+	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
 	COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
 	COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
index 846df18f2..7e4ee8362 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -697,6 +697,8 @@ def test_fpga_core(request):
     parameters['RX_RAM_SIZE'] = 32768
 
     # DMA interface configuration
+    parameters['DMA_LEN_WIDTH'] = 16
+    parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_PIPELINE'] = 2
 
     # PCIe interface configuration