From cf441f004dd5ada2ca51e85d292830bf3c444793 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 22 Sep 2023 01:07:12 -0700 Subject: [PATCH] Rename source sync signals in PTP CDC module for consistency Signed-off-by: Alex Forencich --- rtl/ptp_clock_cdc.v | 42 ++++++++++++++++++------------------ syn/vivado/ptp_clock_cdc.tcl | 18 ++++++++-------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/rtl/ptp_clock_cdc.v b/rtl/ptp_clock_cdc.v index 062a241e7..ea73773e9 100644 --- a/rtl/ptp_clock_cdc.v +++ b/rtl/ptp_clock_cdc.v @@ -110,10 +110,10 @@ reg [47:0] dest_ts_s_capt_reg = 0; reg [TS_NS_WIDTH-1:0] dest_ts_ns_capt_reg = 0; reg [TS_FNS_WIDTH-1:0] dest_ts_fns_capt_reg = 0; -reg [47:0] ts_s_sync_reg = 0; -reg [TS_NS_WIDTH-1:0] ts_ns_sync_reg = 0; -reg [TS_FNS_WIDTH-1:0] ts_fns_sync_reg = 0; -reg ts_step_sync_reg = 0; +reg [47:0] src_ts_s_sync_reg = 0; +reg [TS_NS_WIDTH-1:0] src_ts_ns_sync_reg = 0; +reg [TS_FNS_WIDTH-1:0] src_ts_fns_sync_reg = 0; +reg src_ts_step_sync_reg = 0; reg [47:0] ts_s_reg = 0, ts_s_next; reg [TS_NS_WIDTH-1:0] ts_ns_reg = 0, ts_ns_next; @@ -449,11 +449,11 @@ always @(posedge output_clk) begin if (src_sync_sync2_reg ^ src_sync_sync3_reg) begin // store captured source TS if (TS_WIDTH == 96) begin - ts_s_sync_reg <= src_ts_s_capt_reg; + src_ts_s_sync_reg <= src_ts_s_capt_reg; end - ts_ns_sync_reg <= src_ts_ns_capt_reg; - ts_fns_sync_reg <= src_ts_fns_capt_reg; - ts_step_sync_reg <= src_ts_step_capt_reg; + src_ts_ns_sync_reg <= src_ts_ns_capt_reg; + src_ts_fns_sync_reg <= src_ts_fns_capt_reg; + src_ts_step_sync_reg <= src_ts_step_capt_reg; ts_sync_valid_reg <= ts_capt_valid_reg; ts_capt_valid_reg <= 1'b0; @@ -561,16 +561,16 @@ always @* begin if (ts_sync_valid_reg) begin // Read new value if (TS_WIDTH == 96) begin - if (ts_step_sync_reg || sec_mismatch_reg) begin + if (src_ts_step_sync_reg || sec_mismatch_reg) begin // input stepped sec_mismatch_next = 1'b0; - ts_s_next = ts_s_sync_reg; - ts_ns_next = ts_ns_sync_reg; - ts_ns_inc_next = ts_ns_sync_reg; + ts_s_next = src_ts_s_sync_reg; + ts_ns_next = src_ts_ns_sync_reg; + ts_ns_inc_next = src_ts_ns_sync_reg; ts_ns_ovf_next[30] = 1'b1; - ts_fns_next = ts_fns_sync_reg; - ts_fns_inc_next = ts_fns_sync_reg; + ts_fns_next = src_ts_fns_sync_reg; + ts_fns_inc_next = src_ts_fns_sync_reg; ts_step_next = 1; end else begin // input did not step @@ -578,16 +578,16 @@ always @* begin diff_valid_next = 1'b1; end // compute difference - ts_s_msb_diff_next = ts_s_sync_reg[47:8] != dest_ts_s_capt_reg[47:8]; - ts_s_diff_next = ts_s_sync_reg[7:0] - dest_ts_s_capt_reg[7:0]; - {ts_ns_diff_next, ts_fns_diff_next} = {ts_ns_sync_reg, ts_fns_sync_reg} - {dest_ts_ns_capt_reg, dest_ts_fns_capt_reg}; + ts_s_msb_diff_next = src_ts_s_sync_reg[47:8] != dest_ts_s_capt_reg[47:8]; + ts_s_diff_next = src_ts_s_sync_reg[7:0] - dest_ts_s_capt_reg[7:0]; + {ts_ns_diff_next, ts_fns_diff_next} = {src_ts_ns_sync_reg, src_ts_fns_sync_reg} - {dest_ts_ns_capt_reg, dest_ts_fns_capt_reg}; end else if (TS_WIDTH == 64) begin - if (ts_step_sync_reg || sec_mismatch_reg) begin + if (src_ts_step_sync_reg || sec_mismatch_reg) begin // input stepped sec_mismatch_next = 1'b0; - ts_ns_next = ts_ns_sync_reg; - ts_fns_next = ts_fns_sync_reg; + ts_ns_next = src_ts_ns_sync_reg; + ts_fns_next = src_ts_fns_sync_reg; ts_step_next = 1; end else begin // input did not step @@ -595,7 +595,7 @@ always @* begin diff_valid_next = 1'b1; end // compute difference - {ts_ns_diff_next, ts_fns_diff_next} = {ts_ns_sync_reg, ts_fns_sync_reg} - {dest_ts_ns_capt_reg, dest_ts_fns_capt_reg}; + {ts_ns_diff_next, ts_fns_diff_next} = {src_ts_ns_sync_reg, src_ts_fns_sync_reg} - {dest_ts_ns_capt_reg, dest_ts_fns_capt_reg}; end end diff --git a/syn/vivado/ptp_clock_cdc.tcl b/syn/vivado/ptp_clock_cdc.tcl index a51364781..9974c7b26 100644 --- a/syn/vivado/ptp_clock_cdc.tcl +++ b/syn/vivado/ptp_clock_cdc.tcl @@ -31,22 +31,22 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NA set output_clk_period [if {[llength $output_clk]} {get_property -min PERIOD $output_clk} {expr 1.0}] # timestamp synchronization - set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/ts_(s|ns|fns|step)_sync_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"] + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/src_ts_(s|ns|fns|step)_sync_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"] if {[llength [get_cells "$inst/src_ts_s_capt_reg_reg[*]"]]} { - set_max_delay -from [get_cells "$inst/src_ts_s_capt_reg_reg[*]"] -to [get_cells "$inst/ts_s_sync_reg_reg[*]"] -datapath_only $output_clk_period - set_bus_skew -from [get_cells "$inst/src_ts_s_capt_reg_reg[*]"] -to [get_cells "$inst/ts_s_sync_reg_reg[*]"] $input_clk_period + set_max_delay -from [get_cells "$inst/src_ts_s_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_s_sync_reg_reg[*]"] -datapath_only $output_clk_period + set_bus_skew -from [get_cells "$inst/src_ts_s_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_s_sync_reg_reg[*]"] $input_clk_period } - set_max_delay -from [get_cells "$inst/src_ts_ns_capt_reg_reg[*]"] -to [get_cells "$inst/ts_ns_sync_reg_reg[*]"] -datapath_only $output_clk_period - set_bus_skew -from [get_cells "$inst/src_ts_ns_capt_reg_reg[*]"] -to [get_cells "$inst/ts_ns_sync_reg_reg[*]"] $input_clk_period + set_max_delay -from [get_cells "$inst/src_ts_ns_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_ns_sync_reg_reg[*]"] -datapath_only $output_clk_period + set_bus_skew -from [get_cells "$inst/src_ts_ns_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_ns_sync_reg_reg[*]"] $input_clk_period - set_max_delay -from [get_cells "$inst/src_ts_fns_capt_reg_reg[*]"] -to [get_cells "$inst/ts_fns_sync_reg_reg[*]"] -datapath_only $output_clk_period - set_bus_skew -from [get_cells "$inst/src_ts_fns_capt_reg_reg[*]"] -to [get_cells "$inst/ts_fns_sync_reg_reg[*]"] $input_clk_period + set_max_delay -from [get_cells "$inst/src_ts_fns_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_fns_sync_reg_reg[*]"] -datapath_only $output_clk_period + set_bus_skew -from [get_cells "$inst/src_ts_fns_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_fns_sync_reg_reg[*]"] $input_clk_period if {[llength [get_cells "$inst/src_ts_step_capt_reg_reg"]]} { - set_max_delay -from [get_cells "$inst/src_ts_step_capt_reg_reg"] -to [get_cells "$inst/ts_step_sync_reg_reg"] -datapath_only $output_clk_period - set_bus_skew -from [get_cells "$inst/src_ts_step_capt_reg_reg"] -to [get_cells "$inst/ts_step_sync_reg_reg"] $input_clk_period + set_max_delay -from [get_cells "$inst/src_ts_step_capt_reg_reg"] -to [get_cells "$inst/src_ts_step_sync_reg_reg"] -datapath_only $output_clk_period + set_bus_skew -from [get_cells "$inst/src_ts_step_capt_reg_reg"] -to [get_cells "$inst/src_ts_step_sync_reg_reg"] $input_clk_period } # sample clock