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https://github.com/corundum/corundum.git
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Update port handling
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parent
381fd871c5
commit
cf45a1b6fa
@ -88,6 +88,9 @@ static int mqnic_open(struct net_device *ndev)
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priv->tx_ring[k]->tx_queue = netdev_get_tx_queue(ndev, k);
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}
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// enable first port
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mqnic_activate_port(priv, priv->ports[0]);
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priv->port_up = true;
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netif_tx_start_all_queues(ndev);
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@ -120,6 +123,12 @@ static int mqnic_close(struct net_device *ndev)
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priv->port_up = false;
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spin_unlock_bh(&priv->stats_lock);
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// disable ports
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for (k = 0; k < priv->port_count; k++)
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{
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mqnic_deactivate_port(priv, priv->ports[k]);
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}
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// deactivate TX queues
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for (k = 0; k < priv->tx_queue_count; k++)
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{
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@ -37,7 +37,6 @@ int mqnic_create_port(struct mqnic_priv *priv, struct mqnic_port **port_ptr, int
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{
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struct device *dev = priv->dev;
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struct mqnic_port *port;
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int k;
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port = kzalloc(sizeof(*port), GFP_KERNEL);
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if (!port)
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@ -46,6 +45,8 @@ int mqnic_create_port(struct mqnic_priv *priv, struct mqnic_port **port_ptr, int
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return -ENOMEM;
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}
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*port_ptr = port;
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port->dev = dev;
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port->ndev = priv->ndev;
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@ -68,28 +69,13 @@ int mqnic_create_port(struct mqnic_priv *priv, struct mqnic_port **port_ptr, int
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port->sched_type = ioread32(port->hw_addr+MQNIC_PORT_REG_SCHED_TYPE);
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dev_info(dev, "Scheduler type: 0x%08x", port->sched_type);
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// disable schedulers
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iowrite32(0, port->hw_addr+MQNIC_PORT_REG_SCHED_ENABLE);
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// enable schedulers
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iowrite32(0xffffffff, port->hw_addr+MQNIC_PORT_REG_SCHED_ENABLE);
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for (k = 0; k < priv->tx_queue_count; k++)
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{
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iowrite32(1, port->hw_addr+port->sched_offset+k*4);
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}
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// scheduler queue enable
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iowrite32(0xffffffff, port->hw_addr+port->sched_offset+0x0200);
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// scheduler global enable
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iowrite32(0xffffffff, port->hw_addr+port->sched_offset+0x0300);
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mqnic_deactivate_port(priv, port);
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return 0;
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}
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void mqnic_destroy_port(struct mqnic_priv *priv, struct mqnic_port **port_ptr)
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{
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struct device *dev = priv->dev;
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struct mqnic_port *port = *port_ptr;
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*port_ptr = NULL;
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@ -100,9 +86,21 @@ void mqnic_destroy_port(struct mqnic_priv *priv, struct mqnic_port **port_ptr)
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int mqnic_activate_port(struct mqnic_priv *priv, struct mqnic_port *port)
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{
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int k;
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// enable schedulers
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iowrite32(0xffffffff, port->hw_addr+MQNIC_PORT_REG_SCHED_ENABLE);
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for (k = 0; k < priv->tx_queue_count; k++)
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{
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iowrite32(3, port->hw_addr+port->sched_offset+k*4);
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}
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// scheduler queue enable
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iowrite32(0xffffffff, port->hw_addr+port->sched_offset+0x0200);
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// scheduler global enable
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iowrite32(0xffffffff, port->hw_addr+port->sched_offset+0x0300);
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return 0;
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}
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