FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Decouple transmit completion handling from PTP timestamping

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-05-01 17:41:47 -07:00
parent 53f3547ef5
commit cfdd6f5455
173 changed files with 2387 additions and 2951 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
View File

@ -51,7 +51,6 @@ module mqnic_app_block #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -61,7 +60,12 @@ module mqnic_app_block #
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_TAG_WIDTH = 16,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
// Application configuration
parameter APP_ID = 32'h12348001,
@ -101,7 +105,7 @@ module mqnic_app_block #
// Ethernet interface configuration (direct, async)
parameter AXIS_DATA_WIDTH = 512,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
@ -319,15 +323,15 @@ module mqnic_app_block #
output wire [PORT_COUNT-1:0] m_axis_direct_tx_tlast,
output wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] m_axis_direct_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_direct_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_direct_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_direct_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_direct_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_direct_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_direct_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_direct_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_direct_tx_cpl_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_direct_tx_ptp_ts,
output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_direct_tx_ptp_ts_tag,
output wire [PORT_COUNT-1:0] m_axis_direct_tx_ptp_ts_valid,
input wire [PORT_COUNT-1:0] m_axis_direct_tx_ptp_ts_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_direct_tx_cpl_ts,
output wire [PORT_COUNT*TX_TAG_WIDTH-1:0] m_axis_direct_tx_cpl_tag,
output wire [PORT_COUNT-1:0] m_axis_direct_tx_cpl_valid,
input wire [PORT_COUNT-1:0] m_axis_direct_tx_cpl_ready,
input wire [PORT_COUNT-1:0] direct_rx_clk,
input wire [PORT_COUNT-1:0] direct_rx_rst,
@ -363,15 +367,15 @@ module mqnic_app_block #
output wire [PORT_COUNT-1:0] m_axis_sync_tx_tlast,
output wire [PORT_COUNT*AXIS_SYNC_TX_USER_WIDTH-1:0] m_axis_sync_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_sync_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_sync_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_sync_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_sync_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_sync_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_sync_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_sync_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_sync_tx_cpl_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_sync_tx_ptp_ts,
output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_sync_tx_ptp_ts_tag,
output wire [PORT_COUNT-1:0] m_axis_sync_tx_ptp_ts_valid,
input wire [PORT_COUNT-1:0] m_axis_sync_tx_ptp_ts_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_sync_tx_cpl_ts,
output wire [PORT_COUNT*TX_TAG_WIDTH-1:0] m_axis_sync_tx_cpl_tag,
output wire [PORT_COUNT-1:0] m_axis_sync_tx_cpl_valid,
input wire [PORT_COUNT-1:0] m_axis_sync_tx_cpl_ready,
input wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] s_axis_sync_rx_tdata,
input wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_sync_rx_tkeep,
@ -408,15 +412,15 @@ module mqnic_app_block #
output wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] m_axis_if_tx_tdest,
output wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] m_axis_if_tx_tuser,
input wire [IF_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_ptp_ts,
input wire [IF_COUNT*PTP_TAG_WIDTH-1:0] s_axis_if_tx_ptp_ts_tag,
input wire [IF_COUNT-1:0] s_axis_if_tx_ptp_ts_valid,
output wire [IF_COUNT-1:0] s_axis_if_tx_ptp_ts_ready,
input wire [IF_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_cpl_ts,
input wire [IF_COUNT*TX_TAG_WIDTH-1:0] s_axis_if_tx_cpl_tag,
input wire [IF_COUNT-1:0] s_axis_if_tx_cpl_valid,
output wire [IF_COUNT-1:0] s_axis_if_tx_cpl_ready,
output wire [IF_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts,
output wire [IF_COUNT*PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag,
output wire [IF_COUNT-1:0] m_axis_if_tx_ptp_ts_valid,
input wire [IF_COUNT-1:0] m_axis_if_tx_ptp_ts_ready,
output wire [IF_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_cpl_ts,
output wire [IF_COUNT*TX_TAG_WIDTH-1:0] m_axis_if_tx_cpl_tag,
output wire [IF_COUNT-1:0] m_axis_if_tx_cpl_valid,
input wire [IF_COUNT-1:0] m_axis_if_tx_cpl_ready,
input wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_rx_tdata,
input wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_rx_tkeep,
@ -499,10 +503,10 @@ assign s_axis_direct_tx_tready = m_axis_direct_tx_tready;
assign m_axis_direct_tx_tlast = s_axis_direct_tx_tlast;
assign m_axis_direct_tx_tuser = s_axis_direct_tx_tuser;
assign m_axis_direct_tx_ptp_ts = s_axis_direct_tx_ptp_ts;
assign m_axis_direct_tx_ptp_ts_tag = s_axis_direct_tx_ptp_ts_tag;
assign m_axis_direct_tx_ptp_ts_valid = s_axis_direct_tx_ptp_ts_valid;
assign s_axis_direct_tx_ptp_ts_ready = m_axis_direct_tx_ptp_ts_ready;
assign m_axis_direct_tx_cpl_ts = s_axis_direct_tx_cpl_ts;
assign m_axis_direct_tx_cpl_tag = s_axis_direct_tx_cpl_tag;
assign m_axis_direct_tx_cpl_valid = s_axis_direct_tx_cpl_valid;
assign s_axis_direct_tx_cpl_ready = m_axis_direct_tx_cpl_ready;
assign m_axis_direct_rx_tdata = s_axis_direct_rx_tdata;
assign m_axis_direct_rx_tkeep = s_axis_direct_rx_tkeep;
@ -521,10 +525,10 @@ assign s_axis_sync_tx_tready = m_axis_sync_tx_tready;
assign m_axis_sync_tx_tlast = s_axis_sync_tx_tlast;
assign m_axis_sync_tx_tuser = s_axis_sync_tx_tuser;
assign m_axis_sync_tx_ptp_ts = s_axis_sync_tx_ptp_ts;
assign m_axis_sync_tx_ptp_ts_tag = s_axis_sync_tx_ptp_ts_tag;
assign m_axis_sync_tx_ptp_ts_valid = s_axis_sync_tx_ptp_ts_valid;
assign s_axis_sync_tx_ptp_ts_ready = m_axis_sync_tx_ptp_ts_ready;
assign m_axis_sync_tx_cpl_ts = s_axis_sync_tx_cpl_ts;
assign m_axis_sync_tx_cpl_tag = s_axis_sync_tx_cpl_tag;
assign m_axis_sync_tx_cpl_valid = s_axis_sync_tx_cpl_valid;
assign s_axis_sync_tx_cpl_ready = m_axis_sync_tx_cpl_ready;
assign m_axis_sync_rx_tdata = s_axis_sync_rx_tdata;
assign m_axis_sync_rx_tkeep = s_axis_sync_rx_tkeep;
@ -545,10 +549,10 @@ assign m_axis_if_tx_tid = s_axis_if_tx_tid;
assign m_axis_if_tx_tdest = s_axis_if_tx_tdest;
assign m_axis_if_tx_tuser = s_axis_if_tx_tuser;
assign m_axis_if_tx_ptp_ts = s_axis_if_tx_ptp_ts;
assign m_axis_if_tx_ptp_ts_tag = s_axis_if_tx_ptp_ts_tag;
assign m_axis_if_tx_ptp_ts_valid = s_axis_if_tx_ptp_ts_valid;
assign s_axis_if_tx_ptp_ts_ready = m_axis_if_tx_ptp_ts_ready;
assign m_axis_if_tx_cpl_ts = s_axis_if_tx_cpl_ts;
assign m_axis_if_tx_cpl_tag = s_axis_if_tx_cpl_tag;
assign m_axis_if_tx_cpl_valid = s_axis_if_tx_cpl_valid;
assign s_axis_if_tx_cpl_ready = m_axis_if_tx_cpl_ready;
assign m_axis_if_rx_tdata = s_axis_if_rx_tdata;
assign m_axis_if_rx_tkeep = s_axis_if_rx_tkeep;

25
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
View File

@ -143,7 +143,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -159,21 +159,20 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -274,8 +273,9 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -366,8 +366,9 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

46
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -301,14 +301,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
@ -797,17 +797,18 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
@pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
"axis_eth_data_width", "axis_eth_sync_data_width"), [
(1, 1, 256, 64, 64),
(2, 1, 256, 64, 64),
(1, 2, 256, 64, 64),
(1, 1, 256, 64, 128),
(1, 1, 512, 64, 64),
(1, 1, 512, 64, 128),
(1, 1, 512, 512, 512),
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
(1, 1, 256, 64, 64, 1),
(1, 1, 256, 64, 64, 0),
(2, 1, 256, 64, 64, 1),
(1, 2, 256, 64, 64, 1),
(1, 1, 256, 64, 128, 1),
(1, 1, 512, 64, 64, 1),
(1, 1, 512, 64, 128, 1),
(1, 1, 512, 512, 512, 1),
])
def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
axis_eth_data_width, axis_eth_sync_data_width):
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
dut = "mqnic_core_pcie_us"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
@ -918,7 +919,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -934,21 +935,20 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

80
fpga/app/template/rtl/mqnic_app_block.v
View File

@ -51,7 +51,6 @@ module mqnic_app_block #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -61,7 +60,12 @@ module mqnic_app_block #
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_TAG_WIDTH = 16,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
// Application configuration
parameter APP_ID = 32'h12340001,
@ -101,7 +105,7 @@ module mqnic_app_block #
// Ethernet interface configuration (direct, async)
parameter AXIS_DATA_WIDTH = 512,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
@ -319,15 +323,15 @@ module mqnic_app_block #
output wire [PORT_COUNT-1:0] m_axis_direct_tx_tlast,
output wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] m_axis_direct_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_direct_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_direct_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_direct_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_direct_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_direct_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_direct_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_direct_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_direct_tx_cpl_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_direct_tx_ptp_ts,
output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_direct_tx_ptp_ts_tag,
output wire [PORT_COUNT-1:0] m_axis_direct_tx_ptp_ts_valid,
input wire [PORT_COUNT-1:0] m_axis_direct_tx_ptp_ts_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_direct_tx_cpl_ts,
output wire [PORT_COUNT*TX_TAG_WIDTH-1:0] m_axis_direct_tx_cpl_tag,
output wire [PORT_COUNT-1:0] m_axis_direct_tx_cpl_valid,
input wire [PORT_COUNT-1:0] m_axis_direct_tx_cpl_ready,
input wire [PORT_COUNT-1:0] direct_rx_clk,
input wire [PORT_COUNT-1:0] direct_rx_rst,
@ -363,15 +367,15 @@ module mqnic_app_block #
output wire [PORT_COUNT-1:0] m_axis_sync_tx_tlast,
output wire [PORT_COUNT*AXIS_SYNC_TX_USER_WIDTH-1:0] m_axis_sync_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_sync_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_sync_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_sync_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_sync_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_sync_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_sync_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_sync_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_sync_tx_cpl_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_sync_tx_ptp_ts,
output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_sync_tx_ptp_ts_tag,
output wire [PORT_COUNT-1:0] m_axis_sync_tx_ptp_ts_valid,
input wire [PORT_COUNT-1:0] m_axis_sync_tx_ptp_ts_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_sync_tx_cpl_ts,
output wire [PORT_COUNT*TX_TAG_WIDTH-1:0] m_axis_sync_tx_cpl_tag,
output wire [PORT_COUNT-1:0] m_axis_sync_tx_cpl_valid,
input wire [PORT_COUNT-1:0] m_axis_sync_tx_cpl_ready,
input wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] s_axis_sync_rx_tdata,
input wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_sync_rx_tkeep,
@ -408,15 +412,15 @@ module mqnic_app_block #
output wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] m_axis_if_tx_tdest,
output wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] m_axis_if_tx_tuser,
input wire [IF_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_ptp_ts,
input wire [IF_COUNT*PTP_TAG_WIDTH-1:0] s_axis_if_tx_ptp_ts_tag,
input wire [IF_COUNT-1:0] s_axis_if_tx_ptp_ts_valid,
output wire [IF_COUNT-1:0] s_axis_if_tx_ptp_ts_ready,
input wire [IF_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_cpl_ts,
input wire [IF_COUNT*TX_TAG_WIDTH-1:0] s_axis_if_tx_cpl_tag,
input wire [IF_COUNT-1:0] s_axis_if_tx_cpl_valid,
output wire [IF_COUNT-1:0] s_axis_if_tx_cpl_ready,
output wire [IF_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts,
output wire [IF_COUNT*PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag,
output wire [IF_COUNT-1:0] m_axis_if_tx_ptp_ts_valid,
input wire [IF_COUNT-1:0] m_axis_if_tx_ptp_ts_ready,
output wire [IF_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_cpl_ts,
output wire [IF_COUNT*TX_TAG_WIDTH-1:0] m_axis_if_tx_cpl_tag,
output wire [IF_COUNT-1:0] m_axis_if_tx_cpl_valid,
input wire [IF_COUNT-1:0] m_axis_if_tx_cpl_ready,
input wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_rx_tdata,
input wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_rx_tkeep,
@ -526,10 +530,10 @@ assign s_axis_direct_tx_tready = m_axis_direct_tx_tready;
assign m_axis_direct_tx_tlast = s_axis_direct_tx_tlast;
assign m_axis_direct_tx_tuser = s_axis_direct_tx_tuser;
assign m_axis_direct_tx_ptp_ts = s_axis_direct_tx_ptp_ts;
assign m_axis_direct_tx_ptp_ts_tag = s_axis_direct_tx_ptp_ts_tag;
assign m_axis_direct_tx_ptp_ts_valid = s_axis_direct_tx_ptp_ts_valid;
assign s_axis_direct_tx_ptp_ts_ready = m_axis_direct_tx_ptp_ts_ready;
assign m_axis_direct_tx_cpl_ts = s_axis_direct_tx_cpl_ts;
assign m_axis_direct_tx_cpl_tag = s_axis_direct_tx_cpl_tag;
assign m_axis_direct_tx_cpl_valid = s_axis_direct_tx_cpl_valid;
assign s_axis_direct_tx_cpl_ready = m_axis_direct_tx_cpl_ready;
assign m_axis_direct_rx_tdata = s_axis_direct_rx_tdata;
assign m_axis_direct_rx_tkeep = s_axis_direct_rx_tkeep;
@ -548,10 +552,10 @@ assign s_axis_sync_tx_tready = m_axis_sync_tx_tready;
assign m_axis_sync_tx_tlast = s_axis_sync_tx_tlast;
assign m_axis_sync_tx_tuser = s_axis_sync_tx_tuser;
assign m_axis_sync_tx_ptp_ts = s_axis_sync_tx_ptp_ts;
assign m_axis_sync_tx_ptp_ts_tag = s_axis_sync_tx_ptp_ts_tag;
assign m_axis_sync_tx_ptp_ts_valid = s_axis_sync_tx_ptp_ts_valid;
assign s_axis_sync_tx_ptp_ts_ready = m_axis_sync_tx_ptp_ts_ready;
assign m_axis_sync_tx_cpl_ts = s_axis_sync_tx_cpl_ts;
assign m_axis_sync_tx_cpl_tag = s_axis_sync_tx_cpl_tag;
assign m_axis_sync_tx_cpl_valid = s_axis_sync_tx_cpl_valid;
assign s_axis_sync_tx_cpl_ready = m_axis_sync_tx_cpl_ready;
assign m_axis_sync_rx_tdata = s_axis_sync_rx_tdata;
assign m_axis_sync_rx_tkeep = s_axis_sync_rx_tkeep;
@ -572,10 +576,10 @@ assign m_axis_if_tx_tid = s_axis_if_tx_tid;
assign m_axis_if_tx_tdest = s_axis_if_tx_tdest;
assign m_axis_if_tx_tuser = s_axis_if_tx_tuser;
assign m_axis_if_tx_ptp_ts = s_axis_if_tx_ptp_ts;
assign m_axis_if_tx_ptp_ts_tag = s_axis_if_tx_ptp_ts_tag;
assign m_axis_if_tx_ptp_ts_valid = s_axis_if_tx_ptp_ts_valid;
assign s_axis_if_tx_ptp_ts_ready = m_axis_if_tx_ptp_ts_ready;
assign m_axis_if_tx_cpl_ts = s_axis_if_tx_cpl_ts;
assign m_axis_if_tx_cpl_tag = s_axis_if_tx_cpl_tag;
assign m_axis_if_tx_cpl_valid = s_axis_if_tx_cpl_valid;
assign s_axis_if_tx_cpl_ready = m_axis_if_tx_cpl_ready;
assign m_axis_if_rx_tdata = s_axis_if_rx_tdata;
assign m_axis_if_rx_tkeep = s_axis_if_rx_tkeep;

25
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -142,7 +142,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -159,21 +159,20 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -275,8 +274,9 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -368,8 +368,9 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

46
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -301,14 +301,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
@ -637,17 +637,18 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
@pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
"axis_eth_data_width", "axis_eth_sync_data_width"), [
(1, 1, 256, 64, 64),
(2, 1, 256, 64, 64),
(1, 2, 256, 64, 64),
(1, 1, 256, 64, 128),
(1, 1, 512, 64, 64),
(1, 1, 512, 64, 128),
(1, 1, 512, 512, 512),
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
(1, 1, 256, 64, 64, 1),
(1, 1, 256, 64, 64, 0),
(2, 1, 256, 64, 64, 1),
(1, 2, 256, 64, 64, 1),
(1, 1, 256, 64, 128, 1),
(1, 1, 512, 64, 64, 1),
(1, 1, 512, 64, 128, 1),
(1, 1, 512, 512, 512, 1),
])
def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
axis_eth_data_width, axis_eth_sync_data_width):
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
dut = "mqnic_core_pcie_us"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
@ -758,7 +759,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -775,21 +776,20 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

251
fpga/common/rtl/mqnic_core.v
View File

@ -61,7 +61,6 @@ module mqnic_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module mqnic_core #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,20 @@ module mqnic_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -165,7 +163,7 @@ module mqnic_core #
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
parameter AXIS_TX_PIPELINE = 0,
@ -355,10 +353,10 @@ module mqnic_core #
output wire [PORT_COUNT-1:0] m_axis_tx_tlast,
output wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst,
@ -2070,15 +2068,15 @@ wire [PORT_COUNT-1:0] app_m_axis_direct_tx_tready;
wire [PORT_COUNT-1:0] app_m_axis_direct_tx_tlast;
wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] app_m_axis_direct_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_direct_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_s_axis_direct_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] app_s_axis_direct_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] app_s_axis_direct_tx_ptp_ts_ready;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_direct_tx_cpl_ts;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] app_s_axis_direct_tx_cpl_tag;
wire [PORT_COUNT-1:0] app_s_axis_direct_tx_cpl_valid;
wire [PORT_COUNT-1:0] app_s_axis_direct_tx_cpl_ready;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_direct_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_direct_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] app_m_axis_direct_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] app_m_axis_direct_tx_ptp_ts_ready;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_direct_tx_cpl_ts;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] app_m_axis_direct_tx_cpl_tag;
wire [PORT_COUNT-1:0] app_m_axis_direct_tx_cpl_valid;
wire [PORT_COUNT-1:0] app_m_axis_direct_tx_cpl_ready;
wire [PORT_COUNT-1:0] app_direct_rx_clk;
wire [PORT_COUNT-1:0] app_direct_rx_rst;
@ -2111,15 +2109,15 @@ wire [PORT_COUNT-1:0] app_m_axis_sync_tx_tready;
wire [PORT_COUNT-1:0] app_m_axis_sync_tx_tlast;
wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] app_m_axis_sync_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_sync_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_s_axis_sync_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] app_s_axis_sync_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] app_s_axis_sync_tx_ptp_ts_ready;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_sync_tx_cpl_ts;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] app_s_axis_sync_tx_cpl_tag;
wire [PORT_COUNT-1:0] app_s_axis_sync_tx_cpl_valid;
wire [PORT_COUNT-1:0] app_s_axis_sync_tx_cpl_ready;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_sync_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_sync_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] app_m_axis_sync_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] app_m_axis_sync_tx_ptp_ts_ready;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_sync_tx_cpl_ts;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] app_m_axis_sync_tx_cpl_tag;
wire [PORT_COUNT-1:0] app_m_axis_sync_tx_cpl_valid;
wire [PORT_COUNT-1:0] app_m_axis_sync_tx_cpl_ready;
wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] app_s_axis_sync_rx_tdata;
wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] app_s_axis_sync_rx_tkeep;
@ -2153,15 +2151,15 @@ wire [IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0] app_m_axis_if_tx_tid;
wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] app_m_axis_if_tx_tdest;
wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] app_m_axis_if_tx_tuser;
wire [IF_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_if_tx_ptp_ts;
wire [IF_COUNT*PTP_TAG_WIDTH-1:0] app_s_axis_if_tx_ptp_ts_tag;
wire [IF_COUNT-1:0] app_s_axis_if_tx_ptp_ts_valid;
wire [IF_COUNT-1:0] app_s_axis_if_tx_ptp_ts_ready;
wire [IF_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_if_tx_cpl_ts;
wire [IF_COUNT*TX_TAG_WIDTH-1:0] app_s_axis_if_tx_cpl_tag;
wire [IF_COUNT-1:0] app_s_axis_if_tx_cpl_valid;
wire [IF_COUNT-1:0] app_s_axis_if_tx_cpl_ready;
wire [IF_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_if_tx_ptp_ts;
wire [IF_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_if_tx_ptp_ts_tag;
wire [IF_COUNT-1:0] app_m_axis_if_tx_ptp_ts_valid;
wire [IF_COUNT-1:0] app_m_axis_if_tx_ptp_ts_ready;
wire [IF_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_if_tx_cpl_ts;
wire [IF_COUNT*TX_TAG_WIDTH-1:0] app_m_axis_if_tx_cpl_tag;
wire [IF_COUNT-1:0] app_m_axis_if_tx_cpl_valid;
wire [IF_COUNT-1:0] app_m_axis_if_tx_cpl_ready;
wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_s_axis_if_rx_tdata;
wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_s_axis_if_rx_tkeep;
@ -2199,9 +2197,8 @@ generate
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -2227,20 +2224,20 @@ generate
.RX_MAX_DESC_REQ(16),
.RX_DESC_FIFO_SIZE(16*8),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -2489,15 +2486,15 @@ generate
.s_axis_app_if_tx_tdest(app_m_axis_if_tx_tdest[n*AXIS_IF_TX_DEST_WIDTH +: AXIS_IF_TX_DEST_WIDTH]),
.s_axis_app_if_tx_tuser(app_m_axis_if_tx_tuser[n*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH]),
.m_axis_app_if_tx_ptp_ts(app_s_axis_if_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_app_if_tx_ptp_ts_tag(app_s_axis_if_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.m_axis_app_if_tx_ptp_ts_valid(app_s_axis_if_tx_ptp_ts_valid[n +: 1]),
.m_axis_app_if_tx_ptp_ts_ready(app_s_axis_if_tx_ptp_ts_ready[n +: 1]),
.m_axis_app_if_tx_cpl_ts(app_s_axis_if_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_app_if_tx_cpl_tag(app_s_axis_if_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.m_axis_app_if_tx_cpl_valid(app_s_axis_if_tx_cpl_valid[n +: 1]),
.m_axis_app_if_tx_cpl_ready(app_s_axis_if_tx_cpl_ready[n +: 1]),
.s_axis_app_if_tx_ptp_ts(app_m_axis_if_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_app_if_tx_ptp_ts_tag(app_m_axis_if_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.s_axis_app_if_tx_ptp_ts_valid(app_m_axis_if_tx_ptp_ts_valid[n +: 1]),
.s_axis_app_if_tx_ptp_ts_ready(app_m_axis_if_tx_ptp_ts_ready[n +: 1]),
.s_axis_app_if_tx_cpl_ts(app_m_axis_if_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_app_if_tx_cpl_tag(app_m_axis_if_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.s_axis_app_if_tx_cpl_valid(app_m_axis_if_tx_cpl_valid[n +: 1]),
.s_axis_app_if_tx_cpl_ready(app_m_axis_if_tx_cpl_ready[n +: 1]),
.m_axis_app_if_rx_tdata(app_s_axis_if_rx_tdata[n*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH]),
.m_axis_app_if_rx_tkeep(app_s_axis_if_rx_tkeep[n*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH]),
@ -2534,15 +2531,15 @@ generate
.s_axis_app_sync_tx_tlast(app_m_axis_sync_tx_tlast[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_sync_tx_tuser(app_m_axis_sync_tx_tuser[n*PORTS_PER_IF*AXIS_TX_USER_WIDTH +: PORTS_PER_IF*AXIS_TX_USER_WIDTH]),
.m_axis_app_sync_tx_ptp_ts(app_s_axis_sync_tx_ptp_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.m_axis_app_sync_tx_ptp_ts_tag(app_s_axis_sync_tx_ptp_ts_tag[n*PORTS_PER_IF*PTP_TAG_WIDTH +: PORTS_PER_IF*PTP_TAG_WIDTH]),
.m_axis_app_sync_tx_ptp_ts_valid(app_s_axis_sync_tx_ptp_ts_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_app_sync_tx_ptp_ts_ready(app_s_axis_sync_tx_ptp_ts_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_app_sync_tx_cpl_ts(app_s_axis_sync_tx_cpl_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.m_axis_app_sync_tx_cpl_tag(app_s_axis_sync_tx_cpl_tag[n*PORTS_PER_IF*TX_TAG_WIDTH +: PORTS_PER_IF*TX_TAG_WIDTH]),
.m_axis_app_sync_tx_cpl_valid(app_s_axis_sync_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_app_sync_tx_cpl_ready(app_s_axis_sync_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_sync_tx_ptp_ts(app_m_axis_sync_tx_ptp_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.s_axis_app_sync_tx_ptp_ts_tag(app_m_axis_sync_tx_ptp_ts_tag[n*PORTS_PER_IF*PTP_TAG_WIDTH +: PORTS_PER_IF*PTP_TAG_WIDTH]),
.s_axis_app_sync_tx_ptp_ts_valid(app_m_axis_sync_tx_ptp_ts_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_sync_tx_ptp_ts_ready(app_m_axis_sync_tx_ptp_ts_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_sync_tx_cpl_ts(app_m_axis_sync_tx_cpl_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.s_axis_app_sync_tx_cpl_tag(app_m_axis_sync_tx_cpl_tag[n*PORTS_PER_IF*TX_TAG_WIDTH +: PORTS_PER_IF*TX_TAG_WIDTH]),
.s_axis_app_sync_tx_cpl_valid(app_m_axis_sync_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_sync_tx_cpl_ready(app_m_axis_sync_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_app_sync_rx_tdata(app_s_axis_sync_rx_tdata[n*PORTS_PER_IF*AXIS_SYNC_DATA_WIDTH +: PORTS_PER_IF*AXIS_SYNC_DATA_WIDTH]),
.m_axis_app_sync_rx_tkeep(app_s_axis_sync_rx_tkeep[n*PORTS_PER_IF*AXIS_SYNC_KEEP_WIDTH +: PORTS_PER_IF*AXIS_SYNC_KEEP_WIDTH]),
@ -2575,15 +2572,15 @@ generate
.s_axis_app_direct_tx_tlast(app_m_axis_direct_tx_tlast[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_direct_tx_tuser(app_m_axis_direct_tx_tuser[n*PORTS_PER_IF*AXIS_TX_USER_WIDTH +: PORTS_PER_IF*AXIS_TX_USER_WIDTH]),
.m_axis_app_direct_tx_ptp_ts(app_s_axis_direct_tx_ptp_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.m_axis_app_direct_tx_ptp_ts_tag(app_s_axis_direct_tx_ptp_ts_tag[n*PORTS_PER_IF*PTP_TAG_WIDTH +: PORTS_PER_IF*PTP_TAG_WIDTH]),
.m_axis_app_direct_tx_ptp_ts_valid(app_s_axis_direct_tx_ptp_ts_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_app_direct_tx_ptp_ts_ready(app_s_axis_direct_tx_ptp_ts_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_app_direct_tx_cpl_ts(app_s_axis_direct_tx_cpl_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.m_axis_app_direct_tx_cpl_tag(app_s_axis_direct_tx_cpl_tag[n*PORTS_PER_IF*TX_TAG_WIDTH +: PORTS_PER_IF*TX_TAG_WIDTH]),
.m_axis_app_direct_tx_cpl_valid(app_s_axis_direct_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_app_direct_tx_cpl_ready(app_s_axis_direct_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_direct_tx_ptp_ts(app_m_axis_direct_tx_ptp_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.s_axis_app_direct_tx_ptp_ts_tag(app_m_axis_direct_tx_ptp_ts_tag[n*PORTS_PER_IF*PTP_TAG_WIDTH +: PORTS_PER_IF*PTP_TAG_WIDTH]),
.s_axis_app_direct_tx_ptp_ts_valid(app_m_axis_direct_tx_ptp_ts_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_direct_tx_ptp_ts_ready(app_m_axis_direct_tx_ptp_ts_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_direct_tx_cpl_ts(app_m_axis_direct_tx_cpl_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.s_axis_app_direct_tx_cpl_tag(app_m_axis_direct_tx_cpl_tag[n*PORTS_PER_IF*TX_TAG_WIDTH +: PORTS_PER_IF*TX_TAG_WIDTH]),
.s_axis_app_direct_tx_cpl_valid(app_m_axis_direct_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_app_direct_tx_cpl_ready(app_m_axis_direct_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_app_direct_rx_tdata(app_s_axis_direct_rx_tdata[n*PORTS_PER_IF*AXIS_DATA_WIDTH +: PORTS_PER_IF*AXIS_DATA_WIDTH]),
.m_axis_app_direct_rx_tkeep(app_s_axis_direct_rx_tkeep[n*PORTS_PER_IF*AXIS_KEEP_WIDTH +: PORTS_PER_IF*AXIS_KEEP_WIDTH]),
@ -2612,10 +2609,10 @@ generate
.m_axis_tx_tlast(m_axis_tx_tlast[n*PORTS_PER_IF +: PORTS_PER_IF]),
.m_axis_tx_tuser(m_axis_tx_tuser[n*PORTS_PER_IF*AXIS_TX_USER_WIDTH +: PORTS_PER_IF*AXIS_TX_USER_WIDTH]),
.s_axis_tx_ptp_ts(s_axis_tx_ptp_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag[n*PORTS_PER_IF*PTP_TAG_WIDTH +: PORTS_PER_IF*PTP_TAG_WIDTH]),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts[n*PORTS_PER_IF*PTP_TS_WIDTH +: PORTS_PER_IF*PTP_TS_WIDTH]),
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag[n*PORTS_PER_IF*TX_TAG_WIDTH +: PORTS_PER_IF*TX_TAG_WIDTH]),
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
/*
* Receive data input
@ -2665,6 +2662,12 @@ generate
assign app_direct_rx_clk[n*PORTS_PER_IF+m] = port_rx_clk;
assign app_direct_rx_rst[n*PORTS_PER_IF+m] = port_rx_rst;
wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_96;
wire port_rx_ptp_ts_step;
wire [PTP_TS_WIDTH-1:0] port_tx_ptp_ts_96;
wire port_tx_ptp_ts_step;
if (PTP_TS_ENABLE) begin: ptp
// PTP CDC logic
@ -2683,8 +2686,8 @@ generate
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(tx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.output_ts_step(tx_ptp_ts_step[n*PORTS_PER_IF+m]),
.output_ts(port_tx_ptp_ts_96),
.output_ts_step(port_tx_ptp_ts_step),
.output_pps(),
.locked()
);
@ -2704,22 +2707,28 @@ generate
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(rx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.output_ts_step(rx_ptp_ts_step[n*PORTS_PER_IF+m]),
.output_ts(port_rx_ptp_ts_96),
.output_ts_step(port_rx_ptp_ts_step),
.output_pps(),
.locked()
);
end else begin
assign tx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}};
assign tx_ptp_ts_step[n*PORTS_PER_IF+m] = 1'b0;
assign port_tx_ptp_ts_96 = 0;
assign port_tx_ptp_ts_step = 1'b0;
assign rx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}};
assign rx_ptp_ts_step[n*PORTS_PER_IF+m] = 1'b0;
assign port_rx_ptp_ts_96 = 0;
assign port_rx_ptp_ts_step = 1'b0;
end
assign tx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_tx_ptp_ts_96;
assign tx_ptp_ts_step[n*PORTS_PER_IF+m] = port_tx_ptp_ts_step;
assign rx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_rx_ptp_ts_96;
assign rx_ptp_ts_step[n*PORTS_PER_IF+m] = port_rx_ptp_ts_step;
end
end
@ -2740,7 +2749,6 @@ if (APP_ENABLE) begin : app
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -2750,7 +2758,12 @@ if (APP_ENABLE) begin : app
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
// Application configuration
.APP_ID(APP_ID),
@ -3006,15 +3019,15 @@ if (APP_ENABLE) begin : app
.m_axis_direct_tx_tlast(app_m_axis_direct_tx_tlast),
.m_axis_direct_tx_tuser(app_m_axis_direct_tx_tuser),
.s_axis_direct_tx_ptp_ts(app_s_axis_direct_tx_ptp_ts),
.s_axis_direct_tx_ptp_ts_tag(app_s_axis_direct_tx_ptp_ts_tag),
.s_axis_direct_tx_ptp_ts_valid(app_s_axis_direct_tx_ptp_ts_valid),
.s_axis_direct_tx_ptp_ts_ready(app_s_axis_direct_tx_ptp_ts_ready),
.s_axis_direct_tx_cpl_ts(app_s_axis_direct_tx_cpl_ts),
.s_axis_direct_tx_cpl_tag(app_s_axis_direct_tx_cpl_tag),
.s_axis_direct_tx_cpl_valid(app_s_axis_direct_tx_cpl_valid),
.s_axis_direct_tx_cpl_ready(app_s_axis_direct_tx_cpl_ready),
.m_axis_direct_tx_ptp_ts(app_m_axis_direct_tx_ptp_ts),
.m_axis_direct_tx_ptp_ts_tag(app_m_axis_direct_tx_ptp_ts_tag),
.m_axis_direct_tx_ptp_ts_valid(app_m_axis_direct_tx_ptp_ts_valid),
.m_axis_direct_tx_ptp_ts_ready(app_m_axis_direct_tx_ptp_ts_ready),
.m_axis_direct_tx_cpl_ts(app_m_axis_direct_tx_cpl_ts),
.m_axis_direct_tx_cpl_tag(app_m_axis_direct_tx_cpl_tag),
.m_axis_direct_tx_cpl_valid(app_m_axis_direct_tx_cpl_valid),
.m_axis_direct_tx_cpl_ready(app_m_axis_direct_tx_cpl_ready),
.direct_rx_clk(app_direct_rx_clk),
.direct_rx_rst(app_direct_rx_rst),
@ -3050,15 +3063,15 @@ if (APP_ENABLE) begin : app
.m_axis_sync_tx_tlast(app_m_axis_sync_tx_tlast),
.m_axis_sync_tx_tuser(app_m_axis_sync_tx_tuser),
.s_axis_sync_tx_ptp_ts(app_s_axis_sync_tx_ptp_ts),
.s_axis_sync_tx_ptp_ts_tag(app_s_axis_sync_tx_ptp_ts_tag),
.s_axis_sync_tx_ptp_ts_valid(app_s_axis_sync_tx_ptp_ts_valid),
.s_axis_sync_tx_ptp_ts_ready(app_s_axis_sync_tx_ptp_ts_ready),
.s_axis_sync_tx_cpl_ts(app_s_axis_sync_tx_cpl_ts),
.s_axis_sync_tx_cpl_tag(app_s_axis_sync_tx_cpl_tag),
.s_axis_sync_tx_cpl_valid(app_s_axis_sync_tx_cpl_valid),
.s_axis_sync_tx_cpl_ready(app_s_axis_sync_tx_cpl_ready),
.m_axis_sync_tx_ptp_ts(app_m_axis_sync_tx_ptp_ts),
.m_axis_sync_tx_ptp_ts_tag(app_m_axis_sync_tx_ptp_ts_tag),
.m_axis_sync_tx_ptp_ts_valid(app_m_axis_sync_tx_ptp_ts_valid),
.m_axis_sync_tx_ptp_ts_ready(app_m_axis_sync_tx_ptp_ts_ready),
.m_axis_sync_tx_cpl_ts(app_m_axis_sync_tx_cpl_ts),
.m_axis_sync_tx_cpl_tag(app_m_axis_sync_tx_cpl_tag),
.m_axis_sync_tx_cpl_valid(app_m_axis_sync_tx_cpl_valid),
.m_axis_sync_tx_cpl_ready(app_m_axis_sync_tx_cpl_ready),
.s_axis_sync_rx_tdata(app_s_axis_sync_rx_tdata),
.s_axis_sync_rx_tkeep(app_s_axis_sync_rx_tkeep),
@ -3095,15 +3108,15 @@ if (APP_ENABLE) begin : app
.m_axis_if_tx_tdest(app_m_axis_if_tx_tdest),
.m_axis_if_tx_tuser(app_m_axis_if_tx_tuser),
.s_axis_if_tx_ptp_ts(app_s_axis_if_tx_ptp_ts),
.s_axis_if_tx_ptp_ts_tag(app_s_axis_if_tx_ptp_ts_tag),
.s_axis_if_tx_ptp_ts_valid(app_s_axis_if_tx_ptp_ts_valid),
.s_axis_if_tx_ptp_ts_ready(app_s_axis_if_tx_ptp_ts_ready),
.s_axis_if_tx_cpl_ts(app_s_axis_if_tx_cpl_ts),
.s_axis_if_tx_cpl_tag(app_s_axis_if_tx_cpl_tag),
.s_axis_if_tx_cpl_valid(app_s_axis_if_tx_cpl_valid),
.s_axis_if_tx_cpl_ready(app_s_axis_if_tx_cpl_ready),
.m_axis_if_tx_ptp_ts(app_m_axis_if_tx_ptp_ts),
.m_axis_if_tx_ptp_ts_tag(app_m_axis_if_tx_ptp_ts_tag),
.m_axis_if_tx_ptp_ts_valid(app_m_axis_if_tx_ptp_ts_valid),
.m_axis_if_tx_ptp_ts_ready(app_m_axis_if_tx_ptp_ts_ready),
.m_axis_if_tx_cpl_ts(app_m_axis_if_tx_cpl_ts),
.m_axis_if_tx_cpl_tag(app_m_axis_if_tx_cpl_tag),
.m_axis_if_tx_cpl_valid(app_m_axis_if_tx_cpl_valid),
.m_axis_if_tx_cpl_ready(app_m_axis_if_tx_cpl_ready),
.s_axis_if_rx_tdata(app_s_axis_if_rx_tdata),
.s_axis_if_rx_tkeep(app_s_axis_if_rx_tkeep),
@ -3221,11 +3234,11 @@ end else begin
assign app_m_axis_direct_tx_tlast = 0;
assign app_m_axis_direct_tx_tuser = 0;
assign app_s_axis_direct_tx_ptp_ts_ready = 0;
assign app_s_axis_direct_tx_cpl_ready = 0;
assign app_m_axis_direct_tx_ptp_ts = 0;
assign app_m_axis_direct_tx_ptp_ts_tag = 0;
assign app_m_axis_direct_tx_ptp_ts_valid = 0;
assign app_m_axis_direct_tx_cpl_ts = 0;
assign app_m_axis_direct_tx_cpl_tag = 0;
assign app_m_axis_direct_tx_cpl_valid = 0;
assign app_s_axis_direct_rx_tready = 0;
@ -3243,11 +3256,11 @@ end else begin
assign app_m_axis_sync_tx_tlast = 0;
assign app_m_axis_sync_tx_tuser = 0;
assign app_s_axis_sync_tx_ptp_ts_ready = 0;
assign app_s_axis_sync_tx_cpl_ready = 0;
assign app_m_axis_sync_tx_ptp_ts = 0;
assign app_m_axis_sync_tx_ptp_ts_tag = 0;
assign app_m_axis_sync_tx_ptp_ts_valid = 0;
assign app_m_axis_sync_tx_cpl_ts = 0;
assign app_m_axis_sync_tx_cpl_tag = 0;
assign app_m_axis_sync_tx_cpl_valid = 0;
assign app_s_axis_sync_rx_tready = 0;
@ -3267,11 +3280,11 @@ end else begin
assign app_m_axis_if_tx_tdest = 0;
assign app_m_axis_if_tx_tuser = 0;
assign app_s_axis_if_tx_ptp_ts_ready = 0;
assign app_s_axis_if_tx_cpl_ready = 0;
assign app_m_axis_if_tx_ptp_ts = 0;
assign app_m_axis_if_tx_ptp_ts_tag = 0;
assign app_m_axis_if_tx_ptp_ts_valid = 0;
assign app_m_axis_if_tx_cpl_ts = 0;
assign app_m_axis_if_tx_cpl_tag = 0;
assign app_m_axis_if_tx_cpl_valid = 0;
assign app_s_axis_if_rx_tready = 0;

50
fpga/common/rtl/mqnic_core_axi.v
View File

@ -61,7 +61,6 @@ module mqnic_core_axi #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module mqnic_core_axi #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,20 @@ module mqnic_core_axi #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -170,7 +168,7 @@ module mqnic_core_axi #
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
parameter AXIS_TX_PIPELINE = 0,
@ -345,10 +343,10 @@ module mqnic_core_axi #
output wire [PORT_COUNT-1:0] m_axis_tx_tlast,
output wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst,
@ -792,7 +790,6 @@ mqnic_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -805,7 +802,7 @@ mqnic_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -822,21 +819,20 @@ mqnic_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1084,10 +1080,10 @@ core_inst (
.m_axis_tx_tlast(m_axis_tx_tlast),
.m_axis_tx_tuser(m_axis_tx_tuser),
.s_axis_tx_ptp_ts(s_axis_tx_ptp_ts),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts),
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag),
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
.rx_clk(rx_clk),
.rx_rst(rx_rst),

50
fpga/common/rtl/mqnic_core_pcie.v
View File

@ -61,7 +61,6 @@ module mqnic_core_pcie #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module mqnic_core_pcie #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,20 @@ module mqnic_core_pcie #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -177,7 +175,7 @@ module mqnic_core_pcie #
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
parameter AXIS_TX_PIPELINE = 0,
@ -356,10 +354,10 @@ module mqnic_core_pcie #
output wire [PORT_COUNT-1:0] m_axis_tx_tlast,
output wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst,
@ -1343,7 +1341,6 @@ mqnic_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1356,7 +1353,7 @@ mqnic_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1373,21 +1370,20 @@ mqnic_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1635,10 +1631,10 @@ core_inst (
.m_axis_tx_tlast(m_axis_tx_tlast),
.m_axis_tx_tuser(m_axis_tx_tuser),
.s_axis_tx_ptp_ts(s_axis_tx_ptp_ts),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts),
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag),
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
.rx_clk(rx_clk),
.rx_rst(rx_rst),

50
fpga/common/rtl/mqnic_core_pcie_s10.v
View File

@ -61,7 +61,6 @@ module mqnic_core_pcie_s10 #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module mqnic_core_pcie_s10 #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,20 @@ module mqnic_core_pcie_s10 #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -174,7 +172,7 @@ module mqnic_core_pcie_s10 #
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_IF_DATA_WIDTH = AXIS_ETH_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_RX_USE_READY = 0,
parameter AXIS_ETH_TX_PIPELINE = 0,
@ -313,10 +311,10 @@ module mqnic_core_pcie_s10 #
output wire [PORT_COUNT-1:0] m_axis_eth_tx_tlast,
output wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] m_axis_eth_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_eth_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_eth_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_eth_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_eth_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_eth_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready,
input wire [PORT_COUNT-1:0] eth_rx_clk,
input wire [PORT_COUNT-1:0] eth_rx_rst,
@ -607,7 +605,6 @@ mqnic_core_pcie #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -620,7 +617,7 @@ mqnic_core_pcie #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -637,21 +634,20 @@ mqnic_core_pcie #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -900,10 +896,10 @@ core_pcie_inst (
.m_axis_tx_tlast(m_axis_eth_tx_tlast),
.m_axis_tx_tuser(m_axis_eth_tx_tuser),
.s_axis_tx_ptp_ts(s_axis_eth_tx_ptp_ts),
.s_axis_tx_ptp_ts_tag(s_axis_eth_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_eth_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_eth_tx_ptp_ts_ready),
.s_axis_tx_cpl_ts(s_axis_eth_tx_cpl_ts),
.s_axis_tx_cpl_tag(s_axis_eth_tx_cpl_tag),
.s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),

50
fpga/common/rtl/mqnic_core_pcie_us.v
View File

@ -61,7 +61,6 @@ module mqnic_core_pcie_us #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module mqnic_core_pcie_us #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,20 @@ module mqnic_core_pcie_us #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -175,7 +173,7 @@ module mqnic_core_pcie_us #
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_IF_DATA_WIDTH = AXIS_ETH_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_RX_USE_READY = 0,
parameter AXIS_ETH_TX_PIPELINE = 0,
@ -364,10 +362,10 @@ module mqnic_core_pcie_us #
output wire [PORT_COUNT-1:0] m_axis_eth_tx_tlast,
output wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] m_axis_eth_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_eth_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_eth_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_eth_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_ptp_ts_ready,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_eth_tx_cpl_ts,
input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_eth_tx_cpl_tag,
input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready,
input wire [PORT_COUNT-1:0] eth_rx_clk,
input wire [PORT_COUNT-1:0] eth_rx_rst,
@ -697,7 +695,6 @@ mqnic_core_pcie #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -710,7 +707,7 @@ mqnic_core_pcie #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -727,21 +724,20 @@ mqnic_core_pcie #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -990,10 +986,10 @@ core_pcie_inst (
.m_axis_tx_tlast(m_axis_eth_tx_tlast),
.m_axis_tx_tuser(m_axis_eth_tx_tuser),
.s_axis_tx_ptp_ts(s_axis_eth_tx_ptp_ts),
.s_axis_tx_ptp_ts_tag(s_axis_eth_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_eth_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_eth_tx_ptp_ts_ready),
.s_axis_tx_cpl_ts(s_axis_eth_tx_cpl_ts),
.s_axis_tx_cpl_tag(s_axis_eth_tx_cpl_tag),
.s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),

337
fpga/common/rtl/mqnic_interface.v
View File

@ -48,7 +48,6 @@ module mqnic_interface #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
// Queue manager configuration (interface)
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
@ -76,20 +75,20 @@ module mqnic_interface #
parameter RX_MAX_DESC_REQ = 16,
parameter RX_DESC_FIFO_SIZE = RX_MAX_DESC_REQ*8,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -130,7 +129,7 @@ module mqnic_interface #
// Streaming interface configuration (direct, async)
parameter AXIS_DATA_WIDTH = 512,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
parameter AXIS_TX_PIPELINE = 0,
@ -338,15 +337,15 @@ module mqnic_interface #
input wire [AXIS_IF_TX_DEST_WIDTH-1:0] s_axis_app_if_tx_tdest,
input wire [AXIS_IF_TX_USER_WIDTH-1:0] s_axis_app_if_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_if_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_app_if_tx_ptp_ts_tag,
output wire m_axis_app_if_tx_ptp_ts_valid,
input wire m_axis_app_if_tx_ptp_ts_ready,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_if_tx_cpl_ts,
output wire [TX_TAG_WIDTH-1:0] m_axis_app_if_tx_cpl_tag,
output wire m_axis_app_if_tx_cpl_valid,
input wire m_axis_app_if_tx_cpl_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_if_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_app_if_tx_ptp_ts_tag,
input wire s_axis_app_if_tx_ptp_ts_valid,
output wire s_axis_app_if_tx_ptp_ts_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_if_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_app_if_tx_cpl_tag,
input wire s_axis_app_if_tx_cpl_valid,
output wire s_axis_app_if_tx_cpl_ready,
output wire [AXIS_IF_DATA_WIDTH-1:0] m_axis_app_if_rx_tdata,
output wire [AXIS_IF_KEEP_WIDTH-1:0] m_axis_app_if_rx_tkeep,
@ -383,15 +382,15 @@ module mqnic_interface #
input wire [PORTS-1:0] s_axis_app_sync_tx_tlast,
input wire [PORTS*AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_app_sync_tx_tuser,
output wire [PORTS*PTP_TS_WIDTH-1:0] m_axis_app_sync_tx_ptp_ts,
output wire [PORTS*PTP_TAG_WIDTH-1:0] m_axis_app_sync_tx_ptp_ts_tag,
output wire [PORTS-1:0] m_axis_app_sync_tx_ptp_ts_valid,
input wire [PORTS-1:0] m_axis_app_sync_tx_ptp_ts_ready,
output wire [PORTS*PTP_TS_WIDTH-1:0] m_axis_app_sync_tx_cpl_ts,
output wire [PORTS*TX_TAG_WIDTH-1:0] m_axis_app_sync_tx_cpl_tag,
output wire [PORTS-1:0] m_axis_app_sync_tx_cpl_valid,
input wire [PORTS-1:0] m_axis_app_sync_tx_cpl_ready,
input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_app_sync_tx_ptp_ts,
input wire [PORTS*PTP_TAG_WIDTH-1:0] s_axis_app_sync_tx_ptp_ts_tag,
input wire [PORTS-1:0] s_axis_app_sync_tx_ptp_ts_valid,
output wire [PORTS-1:0] s_axis_app_sync_tx_ptp_ts_ready,
input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_app_sync_tx_cpl_ts,
input wire [PORTS*TX_TAG_WIDTH-1:0] s_axis_app_sync_tx_cpl_tag,
input wire [PORTS-1:0] s_axis_app_sync_tx_cpl_valid,
output wire [PORTS-1:0] s_axis_app_sync_tx_cpl_ready,
output wire [PORTS*AXIS_SYNC_DATA_WIDTH-1:0] m_axis_app_sync_rx_tdata,
output wire [PORTS*AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_app_sync_rx_tkeep,
@ -424,15 +423,15 @@ module mqnic_interface #
input wire [PORTS-1:0] s_axis_app_direct_tx_tlast,
input wire [PORTS*AXIS_TX_USER_WIDTH-1:0] s_axis_app_direct_tx_tuser,
output wire [PORTS*PTP_TS_WIDTH-1:0] m_axis_app_direct_tx_ptp_ts,
output wire [PORTS*PTP_TAG_WIDTH-1:0] m_axis_app_direct_tx_ptp_ts_tag,
output wire [PORTS-1:0] m_axis_app_direct_tx_ptp_ts_valid,
input wire [PORTS-1:0] m_axis_app_direct_tx_ptp_ts_ready,
output wire [PORTS*PTP_TS_WIDTH-1:0] m_axis_app_direct_tx_cpl_ts,
output wire [PORTS*TX_TAG_WIDTH-1:0] m_axis_app_direct_tx_cpl_tag,
output wire [PORTS-1:0] m_axis_app_direct_tx_cpl_valid,
input wire [PORTS-1:0] m_axis_app_direct_tx_cpl_ready,
input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_app_direct_tx_ptp_ts,
input wire [PORTS*PTP_TAG_WIDTH-1:0] s_axis_app_direct_tx_ptp_ts_tag,
input wire [PORTS-1:0] s_axis_app_direct_tx_ptp_ts_valid,
output wire [PORTS-1:0] s_axis_app_direct_tx_ptp_ts_ready,
input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_app_direct_tx_cpl_ts,
input wire [PORTS*TX_TAG_WIDTH-1:0] s_axis_app_direct_tx_cpl_tag,
input wire [PORTS-1:0] s_axis_app_direct_tx_cpl_valid,
output wire [PORTS-1:0] s_axis_app_direct_tx_cpl_ready,
output wire [PORTS*AXIS_DATA_WIDTH-1:0] m_axis_app_direct_rx_tdata,
output wire [PORTS*AXIS_KEEP_WIDTH-1:0] m_axis_app_direct_rx_tkeep,
@ -461,10 +460,10 @@ module mqnic_interface #
output wire [PORTS-1:0] m_axis_tx_tlast,
output wire [PORTS*AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PORTS*PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire [PORTS-1:0] s_axis_tx_ptp_ts_valid,
output wire [PORTS-1:0] s_axis_tx_ptp_ts_ready,
input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire [PORTS*TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire [PORTS-1:0] s_axis_tx_cpl_valid,
output wire [PORTS-1:0] s_axis_tx_cpl_ready,
/*
* Receive data input
@ -2317,10 +2316,10 @@ wire [AXIS_IF_TX_ID_WIDTH-1:0] if_tx_axis_tid;
wire [AXIS_IF_TX_DEST_WIDTH-1:0] if_tx_axis_tdest;
wire [AXIS_IF_TX_USER_WIDTH-1:0] if_tx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] if_tx_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] if_tx_ptp_ts_tag;
wire if_tx_ptp_ts_valid;
wire if_tx_ptp_ts_ready;
wire [PTP_TS_WIDTH-1:0] if_tx_cpl_ts;
wire [TX_TAG_WIDTH-1:0] if_tx_cpl_tag;
wire if_tx_cpl_valid;
wire if_tx_cpl_ready;
mqnic_interface_tx #(
// Structural configuration
@ -2328,9 +2327,8 @@ mqnic_interface_tx #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
// Queue manager configuration (interface)
// Queue manager configuration
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
@ -2351,17 +2349,14 @@ mqnic_interface_tx #(
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
@ -2490,12 +2485,12 @@ interface_tx_inst (
.m_axis_tx_tuser(if_tx_axis_tuser),
/*
* Transmit timestamp input
* Transmit completion input
*/
.s_axis_tx_ptp_ts(if_tx_ptp_ts),
.s_axis_tx_ptp_ts_tag(if_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(if_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(if_tx_ptp_ts_ready),
.s_axis_tx_cpl_ts(if_tx_cpl_ts),
.s_axis_tx_cpl_tag(if_tx_cpl_tag),
.s_axis_tx_cpl_valid(if_tx_cpl_valid),
.s_axis_tx_cpl_ready(if_tx_cpl_ready),
/*
* Configuration
@ -2522,9 +2517,8 @@ mqnic_interface_rx #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
// Queue manager configuration (interface)
// Queue manager configuration
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
@ -2544,18 +2538,15 @@ mqnic_interface_rx #(
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
// Interface configuration (port)
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_RX_SIZE(MAX_RX_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE),
@ -2701,106 +2692,90 @@ assign m_axis_data_dma_write_desc_imm_en = 0;
generate
wire [PORTS*PTP_TS_WIDTH-1:0] axis_if_tx_ptp_ts;
wire [PORTS*PTP_TAG_WIDTH-1:0] axis_if_tx_ptp_ts_tag;
wire [PORTS-1:0] axis_if_tx_ptp_ts_valid;
wire [PORTS-1:0] axis_if_tx_ptp_ts_ready;
wire [PORTS*PTP_TS_WIDTH-1:0] axis_if_tx_cpl_ts;
wire [PORTS*TX_TAG_WIDTH-1:0] axis_if_tx_cpl_tag;
wire [PORTS-1:0] axis_if_tx_cpl_valid;
wire [PORTS-1:0] axis_if_tx_cpl_ready;
if (PTP_TS_ENABLE) begin: ptp
wire [PTP_TS_WIDTH-1:0] axis_tx_cpl_ts;
wire [TX_TAG_WIDTH-1:0] axis_tx_cpl_tag;
wire axis_tx_cpl_valid;
wire axis_tx_cpl_ready;
wire [PTP_TS_WIDTH-1:0] axis_tx_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] axis_tx_ptp_ts_tag;
wire axis_tx_ptp_ts_valid;
wire axis_tx_ptp_ts_ready;
if (PORTS > 1) begin
if (PORTS > 1) begin
axis_arb_mux #(
.S_COUNT(PORTS),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.ID_ENABLE(1),
.S_ID_WIDTH(TX_TAG_WIDTH),
.M_ID_WIDTH(TX_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.LAST_ENABLE(0),
.UPDATE_TID(0),
.ARB_TYPE_ROUND_ROBIN(1'b1),
.ARB_LSB_HIGH_PRIORITY(1'b1)
)
tx_cpl_mux_inst (
.clk(clk),
.rst(rst),
axis_arb_mux #(
.S_COUNT(PORTS),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.ID_ENABLE(1),
.S_ID_WIDTH(PTP_TAG_WIDTH),
.M_ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.LAST_ENABLE(0),
.UPDATE_TID(0),
.ARB_TYPE_ROUND_ROBIN(1'b1),
.ARB_LSB_HIGH_PRIORITY(1'b1)
)
tx_ptp_ts_mux_inst (
.clk(clk),
.rst(rst),
// AXI Stream inputs
.s_axis_tkeep(0),
.s_axis_tdata(PTP_TS_ENABLE ? axis_if_tx_cpl_ts : 0),
.s_axis_tvalid(axis_if_tx_cpl_valid),
.s_axis_tready(axis_if_tx_cpl_ready),
.s_axis_tlast(0),
.s_axis_tdest(0),
.s_axis_tid(axis_if_tx_cpl_tag),
.s_axis_tuser(0),
// AXI Stream inputs
.s_axis_tdata(axis_if_tx_ptp_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_if_tx_ptp_ts_valid),
.s_axis_tready(axis_if_tx_ptp_ts_ready),
.s_axis_tlast(0),
.s_axis_tid(axis_if_tx_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI Stream output
.m_axis_tdata(axis_tx_ptp_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_ptp_ts_valid),
.m_axis_tready(axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(axis_tx_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser()
);
end else begin
assign axis_tx_ptp_ts = axis_if_tx_ptp_ts;
assign axis_tx_ptp_ts_tag = axis_if_tx_ptp_ts_tag;
assign axis_tx_ptp_ts_valid = axis_if_tx_ptp_ts_valid;
assign axis_if_tx_ptp_ts_ready = axis_tx_ptp_ts_ready;
end
if (APP_AXIS_IF_ENABLE) begin
assign m_axis_app_if_tx_ptp_ts = axis_tx_ptp_ts;
assign m_axis_app_if_tx_ptp_ts_tag = axis_tx_ptp_ts_tag;
assign m_axis_app_if_tx_ptp_ts_valid = axis_tx_ptp_ts_valid;
assign axis_tx_ptp_ts_ready = m_axis_app_if_tx_ptp_ts_ready;
assign if_tx_ptp_ts = s_axis_app_if_tx_ptp_ts;
assign if_tx_ptp_ts_tag = s_axis_app_if_tx_ptp_ts_tag;
assign if_tx_ptp_ts_valid = s_axis_app_if_tx_ptp_ts_valid;
assign s_axis_app_if_tx_ptp_ts_ready = if_tx_ptp_ts_ready;
end else begin
assign m_axis_app_if_tx_ptp_ts = 0;
assign m_axis_app_if_tx_ptp_ts_tag = 0;
assign m_axis_app_if_tx_ptp_ts_valid = 0;
assign s_axis_app_if_tx_ptp_ts_ready = 0;
assign if_tx_ptp_ts = axis_tx_ptp_ts;
assign if_tx_ptp_ts_tag = axis_tx_ptp_ts_tag;
assign if_tx_ptp_ts_valid = axis_tx_ptp_ts_valid;
assign axis_tx_ptp_ts_ready = if_tx_ptp_ts_ready;
end
// AXI Stream output
.m_axis_tdata(axis_tx_cpl_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_cpl_valid),
.m_axis_tready(axis_tx_cpl_ready),
.m_axis_tlast(),
.m_axis_tid(axis_tx_cpl_tag),
.m_axis_tdest(),
.m_axis_tuser()
);
end else begin
assign if_tx_ptp_ts = 0;
assign if_tx_ptp_ts_tag = 0;
assign if_tx_ptp_ts_valid = 0;
assign axis_tx_cpl_ts = PTP_TS_ENABLE ? axis_if_tx_cpl_ts : 0;
assign axis_tx_cpl_tag = axis_if_tx_cpl_tag;
assign axis_tx_cpl_valid = axis_if_tx_cpl_valid;
assign axis_if_tx_cpl_ready = axis_tx_cpl_ready;
assign m_axis_app_if_tx_ptp_ts = 0;
assign m_axis_app_if_tx_ptp_ts_tag = 0;
assign m_axis_app_if_tx_ptp_ts_valid = 0;
end
assign s_axis_app_if_tx_ptp_ts_ready = 0;
if (APP_AXIS_IF_ENABLE) begin
assign m_axis_app_if_tx_cpl_ts = PTP_TS_ENABLE ? axis_tx_cpl_ts : 0;
assign m_axis_app_if_tx_cpl_tag = axis_tx_cpl_tag;
assign m_axis_app_if_tx_cpl_valid = axis_tx_cpl_valid;
assign axis_tx_cpl_ready = m_axis_app_if_tx_cpl_ready;
assign if_tx_cpl_ts = PTP_TS_ENABLE ? s_axis_app_if_tx_cpl_ts : 0;
assign if_tx_cpl_tag = s_axis_app_if_tx_cpl_tag;
assign if_tx_cpl_valid = s_axis_app_if_tx_cpl_valid;
assign s_axis_app_if_tx_cpl_ready = if_tx_cpl_ready;
end else begin
assign m_axis_app_if_tx_cpl_ts = 0;
assign m_axis_app_if_tx_cpl_tag = 0;
assign m_axis_app_if_tx_cpl_valid = 0;
assign s_axis_app_if_tx_cpl_ready = 0;
assign if_tx_cpl_ts = PTP_TS_ENABLE ? axis_tx_cpl_ts : 0;
assign if_tx_cpl_tag = axis_tx_cpl_tag;
assign if_tx_cpl_valid = axis_tx_cpl_valid;
assign axis_tx_cpl_ready = if_tx_cpl_ready;
end
@ -3036,13 +3011,12 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
mqnic_port_tx #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
// Application block configuration
@ -3074,10 +3048,10 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_if_tx_tlast(axis_if_tx_fifo_tlast[n +: 1]),
.s_axis_if_tx_tuser(axis_if_tx_fifo_tuser[n*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]),
.m_axis_if_tx_ptp_ts(axis_if_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_if_tx_ptp_ts_tag(axis_if_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.m_axis_if_tx_ptp_ts_valid(axis_if_tx_ptp_ts_valid[n +: 1]),
.m_axis_if_tx_ptp_ts_ready(axis_if_tx_ptp_ts_ready[n +: 1]),
.m_axis_if_tx_cpl_ts(axis_if_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_if_tx_cpl_tag(axis_if_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.m_axis_if_tx_cpl_valid(axis_if_tx_cpl_valid[n +: 1]),
.m_axis_if_tx_cpl_ready(axis_if_tx_cpl_ready[n +: 1]),
/*
* Application section datapath interface (synchronous MAC interface)
@ -3096,15 +3070,15 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_app_sync_tx_tlast(s_axis_app_sync_tx_tlast[n +: 1]),
.s_axis_app_sync_tx_tuser(s_axis_app_sync_tx_tuser[n*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]),
.m_axis_app_sync_tx_ptp_ts(m_axis_app_sync_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_app_sync_tx_ptp_ts_tag(m_axis_app_sync_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.m_axis_app_sync_tx_ptp_ts_valid(m_axis_app_sync_tx_ptp_ts_valid[n +: 1]),
.m_axis_app_sync_tx_ptp_ts_ready(m_axis_app_sync_tx_ptp_ts_ready[n +: 1]),
.m_axis_app_sync_tx_cpl_ts(m_axis_app_sync_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_app_sync_tx_cpl_tag(m_axis_app_sync_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.m_axis_app_sync_tx_cpl_valid(m_axis_app_sync_tx_cpl_valid[n +: 1]),
.m_axis_app_sync_tx_cpl_ready(m_axis_app_sync_tx_cpl_ready[n +: 1]),
.s_axis_app_sync_tx_ptp_ts(s_axis_app_sync_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_app_sync_tx_ptp_ts_tag(s_axis_app_sync_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.s_axis_app_sync_tx_ptp_ts_valid(s_axis_app_sync_tx_ptp_ts_valid[n +: 1]),
.s_axis_app_sync_tx_ptp_ts_ready(s_axis_app_sync_tx_ptp_ts_ready[n +: 1]),
.s_axis_app_sync_tx_cpl_ts(s_axis_app_sync_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_app_sync_tx_cpl_tag(s_axis_app_sync_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.s_axis_app_sync_tx_cpl_valid(s_axis_app_sync_tx_cpl_valid[n +: 1]),
.s_axis_app_sync_tx_cpl_ready(s_axis_app_sync_tx_cpl_ready[n +: 1]),
/*
* Application section datapath interface (direct MAC interface)
@ -3123,15 +3097,15 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_app_direct_tx_tlast(s_axis_app_direct_tx_tlast[n +: 1]),
.s_axis_app_direct_tx_tuser(s_axis_app_direct_tx_tuser[n*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]),
.m_axis_app_direct_tx_ptp_ts(m_axis_app_direct_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_app_direct_tx_ptp_ts_tag(m_axis_app_direct_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.m_axis_app_direct_tx_ptp_ts_valid(m_axis_app_direct_tx_ptp_ts_valid[n +: 1]),
.m_axis_app_direct_tx_ptp_ts_ready(m_axis_app_direct_tx_ptp_ts_ready[n +: 1]),
.m_axis_app_direct_tx_cpl_ts(m_axis_app_direct_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_app_direct_tx_cpl_tag(m_axis_app_direct_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.m_axis_app_direct_tx_cpl_valid(m_axis_app_direct_tx_cpl_valid[n +: 1]),
.m_axis_app_direct_tx_cpl_ready(m_axis_app_direct_tx_cpl_ready[n +: 1]),
.s_axis_app_direct_tx_ptp_ts(s_axis_app_direct_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_app_direct_tx_ptp_ts_tag(s_axis_app_direct_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.s_axis_app_direct_tx_ptp_ts_valid(s_axis_app_direct_tx_ptp_ts_valid[n +: 1]),
.s_axis_app_direct_tx_ptp_ts_ready(s_axis_app_direct_tx_ptp_ts_ready[n +: 1]),
.s_axis_app_direct_tx_cpl_ts(s_axis_app_direct_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_app_direct_tx_cpl_tag(s_axis_app_direct_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.s_axis_app_direct_tx_cpl_valid(s_axis_app_direct_tx_cpl_valid[n +: 1]),
.s_axis_app_direct_tx_cpl_ready(s_axis_app_direct_tx_cpl_ready[n +: 1]),
/*
* Transmit data output
@ -3146,21 +3120,18 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.m_axis_tx_tlast(m_axis_tx_tlast[n +: 1]),
.m_axis_tx_tuser(m_axis_tx_tuser[n*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]),
.s_axis_tx_ptp_ts(s_axis_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid[n +: 1]),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready[n +: 1])
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n +: 1]),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n +: 1])
);
mqnic_port_rx #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
// Interface configuration (port)
.MAX_RX_SIZE(MAX_RX_SIZE),
// Application block configuration

8
fpga/common/rtl/mqnic_interface_rx.v
View File

@ -47,7 +47,6 @@ module mqnic_interface_rx #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
// Queue manager configuration (interface)
parameter RX_QUEUE_INDEX_WIDTH = 8,
@ -69,18 +68,15 @@ module mqnic_interface_rx #
parameter QUEUE_REQ_TAG_WIDTH = 8,
parameter QUEUE_OP_TAG_WIDTH = 8,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter RX_DESC_TABLE_SIZE = 32,
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
// Interface configuration (port)
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_RX_SIZE = 9214,
parameter RX_RAM_SIZE = 32768,

36
fpga/common/rtl/mqnic_interface_tx.v
View File

@ -47,9 +47,8 @@ module mqnic_interface_tx #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
// Queue manager configuration (interface)
// Queue manager configuration
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
@ -70,17 +69,14 @@ module mqnic_interface_tx #
parameter QUEUE_REQ_TAG_WIDTH = 8,
parameter QUEUE_OP_TAG_WIDTH = 8,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
parameter TX_RAM_SIZE = 32768,
@ -100,7 +96,7 @@ module mqnic_interface_tx #
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1
)
(
input wire clk,
@ -209,12 +205,12 @@ module mqnic_interface_tx #
output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
/*
* Transmit timestamp input
* Transmit completion input
*/
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire s_axis_tx_cpl_valid,
output wire s_axis_tx_cpl_ready,
/*
* Configuration
@ -321,7 +317,7 @@ tx_engine #(
.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.AXIS_TX_ID_WIDTH(AXIS_TX_ID_WIDTH),
.AXIS_TX_DEST_WIDTH(AXIS_TX_DEST_WIDTH),
@ -440,12 +436,12 @@ tx_engine_inst (
.m_axis_tx_csum_cmd_ready(tx_csum_cmd_ready),
/*
* Transmit timestamp input
* Transmit completion input
*/
.s_axis_tx_ptp_ts(s_axis_tx_ptp_ts),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts),
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag),
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
/*
* Configuration

5
fpga/common/rtl/mqnic_port_rx.v
View File

@ -44,12 +44,9 @@ module mqnic_port_rx #
(
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
// Interface configuration (port)
parameter MAX_RX_SIZE = 9214,
// Application block configuration

370
fpga/common/rtl/mqnic_port_tx.v
View File

@ -44,13 +44,12 @@ module mqnic_port_tx #
(
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
// Timestamping configuration (port)
// Port configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter MAX_TX_SIZE = 9214,
// Application block configuration
@ -60,7 +59,7 @@ module mqnic_port_tx #
// Streaming interface configuration
parameter AXIS_DATA_WIDTH = 256,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_TX_PIPELINE = 0,
parameter AXIS_TX_FIFO_PIPELINE = 2,
parameter AXIS_TX_TS_PIPELINE = 0,
@ -82,10 +81,10 @@ module mqnic_port_tx #
input wire s_axis_if_tx_tlast,
input wire [AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag,
output wire m_axis_if_tx_ptp_ts_valid,
input wire m_axis_if_tx_ptp_ts_ready,
output wire [PTP_TS_WIDTH-1:0] m_axis_if_tx_cpl_ts,
output wire [TX_TAG_WIDTH-1:0] m_axis_if_tx_cpl_tag,
output wire m_axis_if_tx_cpl_valid,
input wire m_axis_if_tx_cpl_ready,
/*
* Application section datapath interface (synchronous MAC interface)
@ -104,15 +103,15 @@ module mqnic_port_tx #
input wire s_axis_app_sync_tx_tlast,
input wire [AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_app_sync_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_sync_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_app_sync_tx_ptp_ts_tag,
output wire m_axis_app_sync_tx_ptp_ts_valid,
input wire m_axis_app_sync_tx_ptp_ts_ready,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_sync_tx_cpl_ts,
output wire [TX_TAG_WIDTH-1:0] m_axis_app_sync_tx_cpl_tag,
output wire m_axis_app_sync_tx_cpl_valid,
input wire m_axis_app_sync_tx_cpl_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_sync_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_app_sync_tx_ptp_ts_tag,
input wire s_axis_app_sync_tx_ptp_ts_valid,
output wire s_axis_app_sync_tx_ptp_ts_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_sync_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_app_sync_tx_cpl_tag,
input wire s_axis_app_sync_tx_cpl_valid,
output wire s_axis_app_sync_tx_cpl_ready,
/*
* Application section datapath interface (direct MAC interface)
@ -131,15 +130,15 @@ module mqnic_port_tx #
input wire s_axis_app_direct_tx_tlast,
input wire [AXIS_TX_USER_WIDTH-1:0] s_axis_app_direct_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_direct_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_app_direct_tx_ptp_ts_tag,
output wire m_axis_app_direct_tx_ptp_ts_valid,
input wire m_axis_app_direct_tx_ptp_ts_ready,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_direct_tx_cpl_ts,
output wire [TX_TAG_WIDTH-1:0] m_axis_app_direct_tx_cpl_tag,
output wire m_axis_app_direct_tx_cpl_valid,
input wire m_axis_app_direct_tx_cpl_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_direct_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_app_direct_tx_ptp_ts_tag,
input wire s_axis_app_direct_tx_ptp_ts_valid,
output wire s_axis_app_direct_tx_ptp_ts_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_direct_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_app_direct_tx_cpl_tag,
input wire s_axis_app_direct_tx_cpl_valid,
output wire s_axis_app_direct_tx_cpl_ready,
/*
* Transmit data output
@ -154,183 +153,192 @@ module mqnic_port_tx #
output wire m_axis_tx_tlast,
output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire s_axis_tx_cpl_valid,
output wire s_axis_tx_cpl_ready
);
initial begin
if (PTP_TS_ENABLE) begin
if (!TX_CPL_ENABLE) begin
$error("Error: PTP timestamping requires TX completions to be enabled (instance %m)");
$finish;
end
end
end
generate
if (PTP_TS_ENABLE) begin: ptp
// TX completion FIFO
wire [PTP_TS_WIDTH-1:0] axis_tx_in_cpl_ts;
wire [TX_TAG_WIDTH-1:0] axis_tx_in_cpl_tag;
wire axis_tx_in_cpl_valid;
wire axis_tx_in_cpl_ready;
// PTP TS FIFO (TX)
wire [PTP_TS_WIDTH-1:0] axis_tx_in_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] axis_tx_in_ptp_ts_tag;
wire axis_tx_in_ptp_ts_valid;
wire axis_tx_in_ptp_ts_ready;
wire [PTP_TS_WIDTH-1:0] axis_tx_fifo_cpl_ts;
wire [TX_TAG_WIDTH-1:0] axis_tx_fifo_cpl_tag;
wire axis_tx_fifo_cpl_valid;
wire axis_tx_fifo_cpl_ready;
wire [PTP_TS_WIDTH-1:0] axis_tx_fifo_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] axis_tx_fifo_ptp_ts_tag;
wire axis_tx_fifo_ptp_ts_valid;
wire axis_tx_fifo_ptp_ts_ready;
wire [PTP_TS_WIDTH-1:0] axis_tx_pipe_cpl_ts;
wire [TX_TAG_WIDTH-1:0] axis_tx_pipe_cpl_tag;
wire axis_tx_pipe_cpl_valid;
wire axis_tx_pipe_cpl_ready;
wire [PTP_TS_WIDTH-1:0] axis_tx_pipe_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] axis_tx_pipe_ptp_ts_tag;
wire axis_tx_pipe_ptp_ts_valid;
wire axis_tx_pipe_ptp_ts_ready;
if (APP_AXIS_DIRECT_ENABLE) begin
if (APP_AXIS_DIRECT_ENABLE) begin
if (TX_CPL_ENABLE) begin
assign m_axis_app_direct_tx_ptp_ts = s_axis_tx_ptp_ts;
assign m_axis_app_direct_tx_ptp_ts_tag = s_axis_tx_ptp_ts_tag;
assign m_axis_app_direct_tx_ptp_ts_valid = s_axis_tx_ptp_ts_valid;
assign s_axis_tx_ptp_ts_ready = m_axis_app_direct_tx_ptp_ts_ready;
assign axis_tx_in_ptp_ts = s_axis_app_direct_tx_ptp_ts;
assign axis_tx_in_ptp_ts_tag = s_axis_app_direct_tx_ptp_ts_tag;
assign axis_tx_in_ptp_ts_valid = s_axis_app_direct_tx_ptp_ts_valid;
assign s_axis_app_direct_tx_ptp_ts_ready = axis_tx_in_ptp_ts_ready;
assign m_axis_app_direct_tx_cpl_ts = PTP_TS_ENABLE ? s_axis_tx_cpl_ts : 0;
assign m_axis_app_direct_tx_cpl_tag = s_axis_tx_cpl_tag;
assign m_axis_app_direct_tx_cpl_valid = s_axis_tx_cpl_valid;
assign s_axis_tx_cpl_ready = m_axis_app_direct_tx_cpl_ready;
end else begin
assign m_axis_app_direct_tx_ptp_ts = 0;
assign m_axis_app_direct_tx_ptp_ts_tag = 0;
assign m_axis_app_direct_tx_ptp_ts_valid = 0;
assign s_axis_app_direct_tx_ptp_ts_ready = 0;
assign axis_tx_in_ptp_ts = s_axis_tx_ptp_ts;
assign axis_tx_in_ptp_ts_tag = s_axis_tx_ptp_ts_tag;
assign axis_tx_in_ptp_ts_valid = s_axis_tx_ptp_ts_valid;
assign s_axis_tx_ptp_ts_ready = axis_tx_in_ptp_ts_ready;
assign m_axis_app_direct_tx_cpl_ts = 0;
assign m_axis_app_direct_tx_cpl_tag = m_axis_tx_tuser[1 +: TX_TAG_WIDTH];
assign m_axis_app_direct_tx_cpl_valid = m_axis_tx_tvalid && m_axis_tx_tready && m_axis_tx_tlast;
assign s_axis_tx_cpl_ready = 1'b1;
end
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(1),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo_inst (
// AXI input
.s_clk(tx_clk),
.s_rst(tx_rst),
.s_axis_tdata(axis_tx_in_ptp_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_tx_in_ptp_ts_valid),
.s_axis_tready(axis_tx_in_ptp_ts_ready),
.s_axis_tlast(0),
.s_axis_tid(axis_tx_in_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(clk),
.m_rst(rst),
.m_axis_tdata(axis_tx_fifo_ptp_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_fifo_ptp_ts_valid),
.m_axis_tready(axis_tx_fifo_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(axis_tx_fifo_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_pipeline_fifo #(
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(1),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.LENGTH(AXIS_TX_TS_PIPELINE)
)
tx_ptp_ts_pipeline_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(axis_tx_fifo_ptp_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_tx_fifo_ptp_ts_valid),
.s_axis_tready(axis_tx_fifo_ptp_ts_ready),
.s_axis_tlast(0),
.s_axis_tid(axis_tx_fifo_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(axis_tx_pipe_ptp_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_pipe_ptp_ts_valid),
.m_axis_tready(axis_tx_pipe_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(axis_tx_pipe_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser()
);
if (APP_AXIS_SYNC_ENABLE) begin
assign m_axis_app_sync_tx_ptp_ts = axis_tx_pipe_ptp_ts;
assign m_axis_app_sync_tx_ptp_ts_tag = axis_tx_pipe_ptp_ts_tag;
assign m_axis_app_sync_tx_ptp_ts_valid = axis_tx_pipe_ptp_ts_valid;
assign axis_tx_pipe_ptp_ts_ready = m_axis_app_sync_tx_ptp_ts_ready;
assign m_axis_if_tx_ptp_ts = s_axis_app_sync_tx_ptp_ts;
assign m_axis_if_tx_ptp_ts_tag = s_axis_app_sync_tx_ptp_ts_tag;
assign m_axis_if_tx_ptp_ts_valid = s_axis_app_sync_tx_ptp_ts_valid;
assign s_axis_app_sync_tx_ptp_ts_ready = m_axis_if_tx_ptp_ts_ready;
end else begin
assign m_axis_app_sync_tx_ptp_ts = 0;
assign m_axis_app_sync_tx_ptp_ts_tag = 0;
assign m_axis_app_sync_tx_ptp_ts_valid = 0;
assign s_axis_app_sync_tx_ptp_ts_ready = 0;
assign m_axis_if_tx_ptp_ts = axis_tx_pipe_ptp_ts;
assign m_axis_if_tx_ptp_ts_tag = axis_tx_pipe_ptp_ts_tag;
assign m_axis_if_tx_ptp_ts_valid = axis_tx_pipe_ptp_ts_valid;
assign axis_tx_pipe_ptp_ts_ready = m_axis_if_tx_ptp_ts_ready;
end
assign axis_tx_in_cpl_ts = PTP_TS_ENABLE ? s_axis_app_direct_tx_cpl_ts : 0;
assign axis_tx_in_cpl_tag = s_axis_app_direct_tx_cpl_tag;
assign axis_tx_in_cpl_valid = s_axis_app_direct_tx_cpl_valid;
assign s_axis_app_direct_tx_cpl_ready = axis_tx_in_cpl_ready;
end else begin
assign m_axis_app_direct_tx_ptp_ts = 0;
assign m_axis_app_direct_tx_ptp_ts_tag = 0;
assign m_axis_app_direct_tx_ptp_ts_valid = 0;
assign m_axis_app_direct_tx_cpl_ts = 0;
assign m_axis_app_direct_tx_cpl_tag = 0;
assign m_axis_app_direct_tx_cpl_valid = 0;
assign s_axis_app_direct_tx_ptp_ts_ready = 0;
assign s_axis_app_direct_tx_cpl_ready = 0;
assign m_axis_app_sync_tx_ptp_ts = 0;
assign m_axis_app_sync_tx_ptp_ts_tag = 0;
assign m_axis_app_sync_tx_ptp_ts_valid = 0;
if (TX_CPL_ENABLE) begin
assign s_axis_app_sync_tx_ptp_ts_ready = 0;
assign axis_tx_in_cpl_ts = PTP_TS_ENABLE ? s_axis_tx_cpl_ts : 0;
assign axis_tx_in_cpl_tag = s_axis_tx_cpl_tag;
assign axis_tx_in_cpl_valid = s_axis_tx_cpl_valid;
assign s_axis_tx_cpl_ready = axis_tx_in_cpl_ready;
end else begin
assign m_axis_if_tx_ptp_ts = 0;
assign m_axis_if_tx_ptp_ts_tag = 0;
assign m_axis_if_tx_ptp_ts_valid[m] = 0;
assign axis_tx_in_cpl_ts = 0;
assign axis_tx_in_cpl_tag = m_axis_tx_tuser[1 +: TX_TAG_WIDTH];
assign axis_tx_in_cpl_valid = m_axis_tx_tvalid && m_axis_tx_tready && m_axis_tx_tlast;
assign s_axis_tx_cpl_ready = 1'b1;
end
end
axis_async_fifo #(
.DEPTH(TX_CPL_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(1),
.ID_WIDTH(TX_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_cpl_fifo_inst (
// AXI input
.s_clk(tx_clk),
.s_rst(tx_rst),
.s_axis_tdata(axis_tx_in_cpl_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_tx_in_cpl_valid),
.s_axis_tready(axis_tx_in_cpl_ready),
.s_axis_tlast(0),
.s_axis_tid(axis_tx_in_cpl_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(clk),
.m_rst(rst),
.m_axis_tdata(axis_tx_fifo_cpl_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_fifo_cpl_valid),
.m_axis_tready(axis_tx_fifo_cpl_ready),
.m_axis_tlast(),
.m_axis_tid(axis_tx_fifo_cpl_tag),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_pipeline_fifo #(
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(1),
.ID_WIDTH(TX_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.LENGTH(AXIS_TX_TS_PIPELINE)
)
tx_cpl_pipeline_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(axis_tx_fifo_cpl_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_tx_fifo_cpl_valid),
.s_axis_tready(axis_tx_fifo_cpl_ready),
.s_axis_tlast(0),
.s_axis_tid(axis_tx_fifo_cpl_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(axis_tx_pipe_cpl_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_pipe_cpl_valid),
.m_axis_tready(axis_tx_pipe_cpl_ready),
.m_axis_tlast(),
.m_axis_tid(axis_tx_pipe_cpl_tag),
.m_axis_tdest(),
.m_axis_tuser()
);
if (APP_AXIS_SYNC_ENABLE) begin
assign m_axis_app_sync_tx_cpl_ts = PTP_TS_ENABLE ? axis_tx_pipe_cpl_ts : 0;
assign m_axis_app_sync_tx_cpl_tag = axis_tx_pipe_cpl_tag;
assign m_axis_app_sync_tx_cpl_valid = axis_tx_pipe_cpl_valid;
assign axis_tx_pipe_cpl_ready = m_axis_app_sync_tx_cpl_ready;
assign m_axis_if_tx_cpl_ts = PTP_TS_ENABLE ? s_axis_app_sync_tx_cpl_ts : 0;
assign m_axis_if_tx_cpl_tag = s_axis_app_sync_tx_cpl_tag;
assign m_axis_if_tx_cpl_valid = s_axis_app_sync_tx_cpl_valid;
assign s_axis_app_sync_tx_cpl_ready = m_axis_if_tx_cpl_ready;
end else begin
assign m_axis_app_sync_tx_cpl_ts = 0;
assign m_axis_app_sync_tx_cpl_tag = 0;
assign m_axis_app_sync_tx_cpl_valid = 0;
assign s_axis_app_sync_tx_cpl_ready = 0;
assign m_axis_if_tx_cpl_ts = PTP_TS_ENABLE ? axis_tx_pipe_cpl_ts : 0;
assign m_axis_if_tx_cpl_tag = axis_tx_pipe_cpl_tag;
assign m_axis_if_tx_cpl_valid = axis_tx_pipe_cpl_valid;
assign axis_tx_pipe_cpl_ready = m_axis_if_tx_cpl_ready;
end

71
fpga/common/rtl/tx_engine.v
View File

@ -96,8 +96,8 @@ module tx_engine #
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// PTP tag width
parameter PTP_TAG_WIDTH = 16,
// Transmit tag width
parameter TX_TAG_WIDTH = 16,
// Enable TX checksum offload
parameter TX_CHECKSUM_ENABLE = 1,
// AXI stream tid signal width
@ -105,7 +105,7 @@ module tx_engine #
// AXI stream tdest signal width
parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
// AXI stream tuser signal width
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1
)
(
input wire clk,
@ -220,12 +220,12 @@ module tx_engine #
input wire m_axis_tx_csum_cmd_ready,
/*
* Transmit timestamp input
* Transmit completion input
*/
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
input wire [TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire s_axis_tx_cpl_valid,
output wire s_axis_tx_cpl_ready,
/*
* Configuration
@ -275,6 +275,11 @@ initial begin
$error("Error: RAM_ADDR_WIDTH insufficient for buffer size (instance %m)");
$finish;
end
if (TX_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
$error("Error: TX_TAG_WIDTH insufficient for requested descriptor table size (instance %m)");
$finish;
end
end
reg s_axis_tx_req_ready_reg = 1'b0, s_axis_tx_req_ready_next;
@ -313,7 +318,7 @@ reg [7:0] m_axis_tx_csum_cmd_csum_start_reg = 7'd0, m_axis_tx_csum_cmd_csum_star
reg [7:0] m_axis_tx_csum_cmd_csum_offset_reg = 7'd0, m_axis_tx_csum_cmd_csum_offset_next;
reg m_axis_tx_csum_cmd_valid_reg = 1'b0, m_axis_tx_csum_cmd_valid_next;
reg s_axis_tx_ptp_ts_ready_reg = 1'b0, s_axis_tx_ptp_ts_ready_next;
reg s_axis_tx_cpl_ready_reg = 1'b0, s_axis_tx_cpl_ready_next;
reg [CL_TX_BUFFER_SIZE+1-1:0] buf_wr_ptr_reg = 0, buf_wr_ptr_next;
reg [CL_TX_BUFFER_SIZE+1-1:0] buf_rd_ptr_reg = 0, buf_rd_ptr_next;
@ -395,11 +400,11 @@ reg [CL_DESC_TABLE_SIZE-1:0] desc_table_data_fetched_ptr;
reg desc_table_data_fetched_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_tx_start_ptr_reg = 0;
reg desc_table_tx_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_tx_dma_finish_ptr;
reg desc_table_tx_dma_finish_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_tx_finish_ptr;
reg [PTP_TS_WIDTH-1:0] desc_table_tx_finish_ts;
reg desc_table_tx_finish_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_store_ptp_ts_ptr;
reg [PTP_TS_WIDTH-1:0] desc_table_store_ptp_ts;
reg desc_table_store_ptp_ts_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_cpl_enqueue_start_ptr_reg = 0;
reg desc_table_cpl_enqueue_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done_ptr;
@ -449,7 +454,7 @@ assign m_axis_tx_csum_cmd_csum_start = m_axis_tx_csum_cmd_csum_start_reg;
assign m_axis_tx_csum_cmd_csum_offset = m_axis_tx_csum_cmd_csum_offset_reg;
assign m_axis_tx_csum_cmd_valid = m_axis_tx_csum_cmd_valid_reg;
assign s_axis_tx_ptp_ts_ready = s_axis_tx_ptp_ts_ready_reg;
assign s_axis_tx_cpl_ready = s_axis_tx_cpl_ready_reg;
// reg [15:0] stall_cnt = 0;
// wire stalled = stall_cnt[12];
@ -546,7 +551,7 @@ always @* begin
m_axis_tx_csum_cmd_csum_offset_next = m_axis_tx_csum_cmd_csum_offset_reg;
m_axis_tx_csum_cmd_valid_next = m_axis_tx_csum_cmd_valid_reg && !m_axis_tx_csum_cmd_ready;
s_axis_tx_ptp_ts_ready_next = 1'b0;
s_axis_tx_cpl_ready_next = 1'b0;
buf_wr_ptr_next = buf_wr_ptr_reg;
buf_rd_ptr_next = buf_rd_ptr_reg;
@ -593,11 +598,11 @@ always @* begin
desc_table_data_fetched_ptr = s_axis_dma_read_desc_status_tag & DESC_PTR_MASK;
desc_table_data_fetched_en = 1'b0;
desc_table_tx_start_en = 1'b0;
desc_table_tx_finish_ptr = s_axis_tx_desc_status_tag;
desc_table_tx_dma_finish_ptr = s_axis_tx_desc_status_tag;
desc_table_tx_dma_finish_en = 1'b0;
desc_table_tx_finish_ptr = s_axis_tx_cpl_tag;
desc_table_tx_finish_ts = s_axis_tx_cpl_ts;
desc_table_tx_finish_en = 1'b0;
desc_table_store_ptp_ts_ptr = s_axis_tx_ptp_ts_tag;
desc_table_store_ptp_ts = s_axis_tx_ptp_ts;
desc_table_store_ptp_ts_en = 1'b0;
desc_table_cpl_enqueue_start_en = 1'b0;
desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
desc_table_cpl_write_done_en = 1'b0;
@ -754,8 +759,8 @@ always @* begin
m_axis_tx_desc_id_next = desc_table_queue[desc_table_tx_start_ptr_reg & DESC_PTR_MASK];
m_axis_tx_desc_dest_next = desc_table_dest[desc_table_tx_start_ptr_reg & DESC_PTR_MASK];
m_axis_tx_desc_user_next = 0;
m_axis_tx_desc_user_next[1+PTP_TAG_WIDTH-1 +: 1] = 1'b1;
m_axis_tx_desc_user_next[1 +: PTP_TAG_WIDTH-1] = desc_table_tx_start_ptr_reg & DESC_PTR_MASK;
m_axis_tx_desc_user_next[1+TX_TAG_WIDTH-1 +: 1] = 1'b1;
m_axis_tx_desc_user_next[1 +: TX_TAG_WIDTH-1] = desc_table_tx_start_ptr_reg & DESC_PTR_MASK;
m_axis_tx_desc_user_next[0 +: 1] = 1'b0;
m_axis_tx_desc_valid_next = 1'b1;
@ -773,8 +778,8 @@ always @* begin
// wait for transmit DMA completion; free buffer space
if (s_axis_tx_desc_status_valid) begin
// update entry in descriptor table
desc_table_tx_finish_ptr = s_axis_tx_desc_status_tag;
desc_table_tx_finish_en = 1'b1;
desc_table_tx_dma_finish_ptr = s_axis_tx_desc_status_tag;
desc_table_tx_dma_finish_en = 1'b1;
// update read pointer
buf_rd_ptr_next = (desc_table_buf_ptr[s_axis_tx_desc_status_tag & DESC_PTR_MASK] + desc_table_len[s_axis_tx_desc_status_tag & DESC_PTR_MASK] + TX_BUFFER_PTR_MASK_LOWER) & ~TX_BUFFER_PTR_MASK_LOWER;
@ -786,11 +791,11 @@ always @* begin
// transmit done
// wait for transmit completion; store PTP timestamp
s_axis_tx_ptp_ts_ready_next = 1'b1;
if (s_axis_tx_ptp_ts_valid && s_axis_tx_ptp_ts_tag[PTP_TAG_WIDTH-1]) begin
desc_table_store_ptp_ts_ptr = s_axis_tx_ptp_ts_tag;
desc_table_store_ptp_ts = s_axis_tx_ptp_ts;
desc_table_store_ptp_ts_en = 1'b1;
s_axis_tx_cpl_ready_next = 1'b1;
if (s_axis_tx_cpl_valid && s_axis_tx_cpl_tag[TX_TAG_WIDTH-1]) begin
desc_table_tx_finish_ptr = s_axis_tx_cpl_tag;
desc_table_tx_finish_ts = s_axis_tx_cpl_ts;
desc_table_tx_finish_en = 1'b1;
end
// finish transmit; start completion enqueue
@ -888,7 +893,7 @@ always @(posedge clk) begin
m_axis_tx_desc_user_reg <= m_axis_tx_desc_user_next;
m_axis_tx_desc_valid_reg <= m_axis_tx_desc_valid_next;
s_axis_tx_ptp_ts_ready_reg <= s_axis_tx_ptp_ts_ready_next;
s_axis_tx_cpl_ready_reg <= s_axis_tx_cpl_ready_next;
m_axis_tx_csum_cmd_csum_enable_reg <= m_axis_tx_csum_cmd_csum_enable_next;
m_axis_tx_csum_cmd_csum_start_reg <= m_axis_tx_csum_cmd_csum_start_next;
@ -954,9 +959,11 @@ always @(posedge clk) begin
desc_table_tx_start_ptr_reg <= desc_table_tx_start_ptr_reg + 1;
end
if (desc_table_store_ptp_ts_en) begin
desc_table_ptp_ts[desc_table_store_ptp_ts_ptr] <= desc_table_store_ptp_ts;
desc_table_tx_done_b[desc_table_store_ptp_ts_ptr] <= !desc_table_tx_done_a[desc_table_store_ptp_ts_ptr];
if (desc_table_tx_finish_en) begin
if (PTP_TS_ENABLE) begin
desc_table_ptp_ts[desc_table_tx_finish_ptr] <= desc_table_tx_finish_ts;
end
desc_table_tx_done_b[desc_table_tx_finish_ptr] <= !desc_table_tx_done_a[desc_table_tx_finish_ptr];
end
if (desc_table_cpl_enqueue_start_en) begin
@ -998,7 +1005,7 @@ always @(posedge clk) begin
m_axis_cpl_req_valid_reg <= 1'b0;
m_axis_dma_read_desc_valid_reg <= 1'b0;
m_axis_tx_desc_valid_reg <= 1'b0;
s_axis_tx_ptp_ts_ready_reg <= 1'b0;
s_axis_tx_cpl_ready_reg <= 1'b0;
m_axis_tx_csum_cmd_valid_reg <= 1'b0;
buf_wr_ptr_reg <= 0;

25
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -128,7 +128,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -145,21 +145,20 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -261,8 +260,9 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -352,8 +352,9 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

40
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -117,14 +117,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
@ -445,14 +445,15 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
@pytest.mark.parametrize(("if_count", "ports_per_if", "axi_data_width",
"axis_data_width", "axis_sync_data_width"), [
(1, 1, 128, 64, 64),
(2, 1, 128, 64, 64),
(1, 2, 128, 64, 64),
(1, 1, 128, 64, 128),
"axis_data_width", "axis_sync_data_width", "ptp_ts_enable"), [
(1, 1, 128, 64, 64, 1),
(1, 1, 128, 64, 64, 0),
(2, 1, 128, 64, 64, 1),
(1, 2, 128, 64, 64, 1),
(1, 1, 128, 64, 128, 1),
])
def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
axis_data_width, axis_sync_data_width):
axis_data_width, axis_sync_data_width, ptp_ts_enable):
dut = "mqnic_core_axi"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
@ -549,7 +550,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -566,21 +567,20 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

25
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -138,7 +138,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -155,21 +155,20 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -276,8 +275,9 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -374,8 +374,9 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

46
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -226,14 +226,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
@ -556,17 +556,18 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
@pytest.mark.parametrize(("if_count", "ports_per_if", "pcie_data_width",
"axis_eth_data_width", "axis_eth_sync_data_width"), [
(1, 1, 256, 64, 64),
(2, 1, 256, 64, 64),
(1, 2, 256, 64, 64),
(1, 1, 256, 64, 128),
# (1, 1, 512, 64, 64),
# (1, 1, 512, 64, 128),
# (1, 1, 512, 512, 512),
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
(1, 1, 256, 64, 64, 1),
(1, 1, 256, 64, 64, 0),
(2, 1, 256, 64, 64, 1),
(1, 2, 256, 64, 64, 1),
(1, 1, 256, 64, 128, 1),
# (1, 1, 512, 64, 64, 1),
# (1, 1, 512, 64, 128, 1),
# (1, 1, 512, 512, 512, 1),
])
def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
axis_eth_data_width, axis_eth_sync_data_width):
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
dut = "mqnic_core_pcie_s10"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
@ -673,7 +674,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -690,21 +691,20 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

25
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -140,7 +140,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -157,21 +157,20 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -273,8 +272,9 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -366,8 +366,9 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

46
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -301,14 +301,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
@ -631,17 +631,18 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
@pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
"axis_eth_data_width", "axis_eth_sync_data_width"), [
(1, 1, 256, 64, 64),
(2, 1, 256, 64, 64),
(1, 2, 256, 64, 64),
(1, 1, 256, 64, 128),
(1, 1, 512, 64, 64),
(1, 1, 512, 64, 128),
(1, 1, 512, 512, 512),
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
(1, 1, 256, 64, 64, 1),
(1, 1, 256, 64, 64, 0),
(2, 1, 256, 64, 64, 1),
(1, 2, 256, 64, 64, 1),
(1, 1, 256, 64, 128, 1),
(1, 1, 512, 64, 64, 1),
(1, 1, 512, 64, 128, 1),
(1, 1, 512, 512, 512, 1),
])
def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
axis_eth_data_width, axis_eth_sync_data_width):
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
dut = "mqnic_core_pcie_us"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
@ -750,7 +751,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -767,21 +768,20 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

25
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -142,7 +142,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -159,21 +159,20 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -275,8 +274,9 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -368,8 +368,9 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

46
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -301,14 +301,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
@ -684,17 +684,18 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
@pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
"axis_eth_data_width", "axis_eth_sync_data_width"), [
(1, 1, 256, 64, 64),
(2, 1, 256, 64, 64),
(1, 2, 256, 64, 64),
(1, 1, 256, 64, 128),
(1, 1, 512, 64, 64),
(1, 1, 512, 64, 128),
(1, 1, 512, 512, 512),
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
(1, 1, 256, 64, 64, 1),
(1, 1, 256, 64, 64, 0),
(2, 1, 256, 64, 64, 1),
(1, 2, 256, 64, 64, 1),
(1, 1, 256, 64, 128, 1),
(1, 1, 512, 64, 64, 1),
(1, 1, 512, 64, 128, 1),
(1, 1, 512, 512, 512, 1),
])
def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
axis_eth_data_width, axis_eth_sync_data_width):
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
dut = "mqnic_core_pcie_us"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
@ -805,7 +806,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -822,21 +823,20 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -261,6 +258,9 @@ parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -268,7 +268,7 @@ parameter MSI_COUNT = 32;
parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1688,7 +1688,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1701,7 +1700,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1718,21 +1717,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

45
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -73,7 +72,7 @@ module fpga_core #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -90,21 +89,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -165,7 +162,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
@ -683,7 +680,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -723,7 +720,7 @@ mqnic_port_map_mac_axis #(
.PORT_COUNT(PORT_COUNT),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_TAG_WIDTH(TX_TAG_WIDTH),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -819,7 +816,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -832,7 +828,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -849,21 +845,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1121,10 +1116,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -144,7 +144,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -161,21 +161,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -273,8 +270,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -362,8 +358,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -680,7 +680,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -697,21 +697,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -263,6 +260,9 @@ parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h2;
parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -272,7 +272,7 @@ parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1);
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1351,7 +1351,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1363,7 +1362,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1380,21 +1379,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

47
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module fpga_core #
parameter IF_PTP_PERIOD_NS = 6'h2,
parameter IF_PTP_PERIOD_FNS = 16'h8F5C,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -171,7 +168,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
@ -909,7 +906,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -994,7 +991,7 @@ generate
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -1027,7 +1024,7 @@ generate
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
.tx_error_underflow(),
@ -1061,7 +1058,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1074,7 +1070,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1091,21 +1087,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1363,10 +1358,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -151,7 +151,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -168,21 +168,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -279,8 +276,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -367,8 +363,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -739,7 +739,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -756,21 +756,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -263,6 +260,9 @@ parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -270,7 +270,7 @@ parameter MSI_COUNT = 32;
parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1822,7 +1822,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1835,7 +1834,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1852,21 +1851,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

45
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -73,7 +72,7 @@ module fpga_core #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -90,21 +89,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -165,7 +162,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 4,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
@ -691,7 +688,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -731,7 +728,7 @@ mqnic_port_map_mac_axis #(
.PORT_COUNT(PORT_COUNT),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_TAG_WIDTH(TX_TAG_WIDTH),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -827,7 +824,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -840,7 +836,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -857,21 +853,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1129,10 +1124,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -144,7 +144,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -161,21 +161,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -273,8 +270,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -362,8 +358,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -680,7 +680,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -697,21 +697,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -265,6 +262,9 @@ parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -274,7 +274,7 @@ parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1);
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1484,7 +1484,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1496,7 +1495,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1513,21 +1512,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

47
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module fpga_core #
parameter IF_PTP_PERIOD_NS = 6'h6,
parameter IF_PTP_PERIOD_FNS = 16'h6666,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -171,7 +168,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 4,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
@ -918,7 +915,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -1003,7 +1000,7 @@ generate
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -1036,7 +1033,7 @@ generate
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
.tx_error_underflow(),
@ -1070,7 +1067,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1083,7 +1079,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1100,21 +1096,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1372,10 +1367,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -151,7 +151,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -168,21 +168,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -279,8 +276,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -367,8 +363,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -739,7 +739,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -756,21 +756,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -263,6 +260,9 @@ parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -270,7 +270,7 @@ parameter MSI_COUNT = 32;
parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1822,7 +1822,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1835,7 +1834,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1852,21 +1851,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

45
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -73,7 +72,7 @@ module fpga_core #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -90,21 +89,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -165,7 +162,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 4,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
@ -691,7 +688,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -731,7 +728,7 @@ mqnic_port_map_mac_axis #(
.PORT_COUNT(PORT_COUNT),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_TAG_WIDTH(TX_TAG_WIDTH),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -827,7 +824,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -840,7 +836,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -857,21 +853,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1129,10 +1124,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -144,7 +144,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -161,21 +161,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -273,8 +270,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -362,8 +358,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -680,7 +680,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -697,21 +697,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -265,6 +262,9 @@ parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -274,7 +274,7 @@ parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1);
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1484,7 +1484,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1496,7 +1495,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1513,21 +1512,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

47
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module fpga_core #
parameter IF_PTP_PERIOD_NS = 6'h6,
parameter IF_PTP_PERIOD_FNS = 16'h6666,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -171,7 +168,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 4,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
@ -918,7 +915,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -1003,7 +1000,7 @@ generate
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -1036,7 +1033,7 @@ generate
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
.tx_error_underflow(),
@ -1070,7 +1067,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1083,7 +1079,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1100,21 +1096,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1372,10 +1367,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -151,7 +151,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -168,21 +168,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -279,8 +276,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -367,8 +363,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -739,7 +739,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -756,21 +756,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

34
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -237,7 +234,6 @@ module fpga #
// PTP configuration
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
@ -246,6 +242,9 @@ parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -253,7 +252,7 @@ parameter MSI_COUNT = 32;
parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1719,7 +1718,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1732,7 +1730,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1749,21 +1747,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

45
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -73,7 +72,7 @@ module fpga_core #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -90,21 +89,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -165,7 +162,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 4,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
@ -567,7 +564,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -607,7 +604,7 @@ mqnic_port_map_mac_axis #(
.PORT_COUNT(PORT_COUNT),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_TAG_WIDTH(TX_TAG_WIDTH),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -703,7 +700,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -716,7 +712,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -733,21 +729,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1005,10 +1000,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -144,7 +144,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 1
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -161,21 +161,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -273,8 +270,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -362,8 +358,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -669,7 +669,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -686,21 +686,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -248,6 +245,9 @@ parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -257,7 +257,7 @@ parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1);
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1387,7 +1387,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1401,7 +1400,7 @@ fpga_core #(
.IF_PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
.IF_PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1418,21 +1417,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

47
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module fpga_core #
parameter IF_PTP_PERIOD_NS = 6'h6,
parameter IF_PTP_PERIOD_FNS = 16'h6666,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -171,7 +168,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 4,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
@ -794,7 +791,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -879,7 +876,7 @@ generate
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -912,7 +909,7 @@ generate
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
.tx_error_underflow(),
@ -946,7 +943,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -959,7 +955,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -976,21 +972,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1248,10 +1243,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -151,7 +151,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 1
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -168,21 +168,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -279,8 +276,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -367,8 +363,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -728,7 +728,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -745,21 +745,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -224,6 +221,9 @@ parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -231,7 +231,7 @@ parameter MSI_COUNT = 32;
parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1321,7 +1321,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1334,7 +1333,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1351,21 +1350,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

45
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -73,7 +72,7 @@ module fpga_core #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -90,21 +89,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -165,7 +162,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 4,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
@ -563,7 +560,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -599,7 +596,7 @@ mqnic_port_map_mac_axis #(
.PORT_COUNT(PORT_COUNT),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_TAG_WIDTH(TX_TAG_WIDTH),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -695,7 +692,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -708,7 +704,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -725,21 +721,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -997,10 +992,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -144,7 +144,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 1
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -161,21 +161,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -273,8 +270,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -362,8 +358,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -630,7 +630,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -647,21 +647,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -229,6 +226,9 @@ parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -238,7 +238,7 @@ parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1);
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1157,7 +1157,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1169,7 +1168,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1186,21 +1185,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

47
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module fpga_core #
parameter IF_PTP_PERIOD_NS = 6'h6,
parameter IF_PTP_PERIOD_FNS = 16'h6666,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -171,7 +168,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 4,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
@ -715,7 +712,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -800,7 +797,7 @@ generate
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -833,7 +830,7 @@ generate
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
.tx_error_underflow(),
@ -867,7 +864,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -880,7 +876,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -897,21 +893,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1169,10 +1164,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -151,7 +151,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 1
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -168,21 +168,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -279,8 +276,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -367,8 +363,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -653,7 +653,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -670,21 +670,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -273,6 +270,9 @@ parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -282,7 +282,7 @@ parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1);
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1343,7 +1343,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1355,7 +1354,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1372,21 +1371,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

47
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module fpga_core #
parameter IF_PTP_PERIOD_NS = 6'h6,
parameter IF_PTP_PERIOD_FNS = 16'h6666,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -171,7 +168,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
@ -940,7 +937,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -1025,7 +1022,7 @@ generate
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -1058,7 +1055,7 @@ generate
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
.tx_error_underflow(),
@ -1092,7 +1089,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1105,7 +1101,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1122,21 +1118,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1394,10 +1389,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
View File

@ -151,7 +151,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 1
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -168,21 +168,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -279,8 +276,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -367,8 +363,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -723,7 +723,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -740,21 +740,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/ExaNIC_X10/fpga/fpga/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -249,6 +246,9 @@ parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -258,7 +258,7 @@ parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1031,7 +1031,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1043,7 +1042,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1060,21 +1059,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

47
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module fpga_core #
parameter IF_PTP_PERIOD_NS = 6'h6,
parameter IF_PTP_PERIOD_FNS = 16'h6666,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -171,7 +168,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
@ -732,7 +729,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -817,7 +814,7 @@ generate
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -850,7 +847,7 @@ generate
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
.tx_error_underflow(),
@ -884,7 +881,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -897,7 +893,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -914,21 +910,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1186,10 +1181,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
View File

@ -151,7 +151,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 1
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -168,21 +168,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -279,8 +276,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -367,8 +363,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -641,7 +641,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -658,21 +658,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

13
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl
View File

@ -101,7 +101,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -118,21 +118,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

33
fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
View File

@ -64,7 +64,7 @@ module fpga #
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -81,21 +81,18 @@ module fpga #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -243,6 +240,9 @@ parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h2;
parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
// Interface configuration
parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
@ -252,7 +252,7 @@ parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1);
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
@ -1060,7 +1060,6 @@ fpga_core #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -1072,7 +1071,7 @@ fpga_core #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -1089,21 +1088,19 @@ fpga_core #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),

47
fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
View File

@ -60,7 +60,6 @@ module fpga_core #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
@ -74,7 +73,7 @@ module fpga_core #
parameter IF_PTP_PERIOD_NS = 6'h2,
parameter IF_PTP_PERIOD_FNS = 16'h8F5C,
// Queue manager configuration (interface)
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
@ -91,21 +90,19 @@ module fpga_core #
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
@ -171,7 +168,7 @@ module fpga_core #
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2,
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
@ -809,7 +806,7 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
@ -894,7 +891,7 @@ generate
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_PTP_TAG_WIDTH(TX_TAG_WIDTH),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
@ -927,7 +924,7 @@ generate
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
.tx_error_underflow(),
@ -961,7 +958,6 @@ mqnic_core_pcie_us #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
@ -974,7 +970,7 @@ mqnic_core_pcie_us #(
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
@ -991,21 +987,20 @@ mqnic_core_pcie_us #(
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
@ -1263,10 +1258,10 @@ core_inst (
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),

19
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
View File

@ -151,7 +151,7 @@ export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 1
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
@ -168,21 +168,18 @@ export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QU
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
# Interface configuration
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
@ -279,8 +276,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
@ -367,8 +363,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)

13
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -650,7 +650,7 @@ def test_fpga_core(request):
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
@ -667,21 +667,18 @@ def test_fpga_core(request):
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1

13
fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
View File

@ -92,7 +92,7 @@ dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration (interface)
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
@ -109,21 +109,18 @@ dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDT
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration (port)
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
# Scheduler configuration (port)
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Timestamping configuration (port)
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_PTP_TS_FIFO_DEPTH "32"
dict set params RX_PTP_TS_FIFO_DEPTH "32"
# Interface configuration (port)
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_RSS_ENABLE "1"
dict set params RX_HASH_ENABLE "1"

Some files were not shown because too many files have changed in this diff Show More