diff --git a/example/520N_MX/fpga_10g/README.md b/example/520N_MX/fpga_10g/README.md new file mode 100644 index 000000000..1e088b36b --- /dev/null +++ b/example/520N_MX/fpga_10g/README.md @@ -0,0 +1,30 @@ +# Verilog Ethernet BittWare 520N-MX Example Design + +## Introduction + +This example design targets the BittWare 520N-MX board. + +The design by default listens to UDP port 1234 at IP address 192.168.1.128 and +will echo back any packets received. The design will also respond correctly +to ARP requests. + +* FPGA: 1SM21CHU2F53E2VG +* PHY: Transceiver in 10G BASE-R native mode + +## How to build + +Run make to build. Ensure that the Intel Quartus Prime Pro toolchain +components are in PATH. + +## How to test + +Run make program to program the board with the Intel software. Then run + + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/520N_MX/fpga_10g/common/quartus_pro.mk b/example/520N_MX/fpga_10g/common/quartus_pro.mk new file mode 100644 index 000000000..1fc1b6fe8 --- /dev/null +++ b/example/520N_MX/fpga_10g/common/quartus_pro.mk @@ -0,0 +1,179 @@ +################################################################### +# +# Makefile for Intel Quartus Prime Pro +# +# Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX) +# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG) +# SYN_FILES - space-separated list of source files +# IP_FILES - space-separated list of IP files +# IP_TCL_FILES - space-separated list of TCL files for qsys-script +# QSF_FILES - space-separated list of settings files +# SDC_FILES - space-separated list of timing constraint files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = "Stratix 10 DX" +# FPGA_DEVICE = 1SD280PT2F55E1VG +# SYN_FILES = rtl/fpga.v +# QSF_FILES = fpga.qsf +# SDC_FILES = fpga.sdc +# include ../common/quartus_pro.mk +# +################################################################### + +# phony targets +.PHONY: clean fpga + +# output files to hang on to +.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt +.SECONDARY: + +# any project specific settings +CONFIG ?= config.mk +-include ../$(CONFIG) + +SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) + +IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES)) +IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES))) + +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES))) +IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES))) + +ifdef QSF_FILES + QSF_FILES_REL = $(patsubst %, ../%, $(QSF_FILES)) +else + QSF_FILES_REL = ../$(FPGA_TOP).qsf +endif + +SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES)) + +ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and database +################################################################### + +all: fpga + +fpga: $(FPGA_TOP).sof + +quartus: $(FPGA_TOP).qpf + quartus $(FPGA_TOP).qpf + +tmpclean: + -rm -rf defines.v + -rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp + -rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit + +clean: tmpclean + -rm -rf *.sof *.pof *.jdi *.jic *.map + +distclean: clean + -rm -rf rev + +syn: smart.log output_files/$(PROJECT).syn.rpt +fit: smart.log output_files/$(PROJECT).fit.rpt +asm: smart.log output_files/$(PROJECT).asm.rpt +sta: smart.log output_files/$(PROJECT).sta.rpt +smart: smart.log + +################################################################### +# Executable Configuration +################################################################### + +IP_ARGS = --run_default_mode_op +SYN_ARGS = --read_settings_files=on --write_settings_files=off +FIT_ARGS = --read_settings_files=on --write_settings_files=off +ASM_ARGS = --read_settings_files=on --write_settings_files=off +STA_ARGS = + +################################################################### +# Target implementations +################################################################### + +STAMP = echo done > + +define COPY_IP_RULE +$(patsubst %, ip/%, $(notdir $(1))): $(1) + @mkdir -p ip + @cp -pv $(1) ip/ +endef +$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l)))) + +define TCL_IP_GEN_RULE +$(patsubst %.tcl, %.ip, $(1)): $(1) + cd ip && qsys-script --script=$(notdir $(1)) +endef +$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l)))) + +%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) + quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP) + +%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL) + quartus_syn $(SYN_ARGS) $(FPGA_TOP) + +%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL) + quartus_fit $(FIT_ARGS) $(FPGA_TOP) + +%.sta.rpt: sta.chg %.fit.rpt + quartus_sta $(STA_ARGS) $(FPGA_TOP) + +%.asm.rpt: asm.chg %.sta.rpt + quartus_asm $(ASM_ARGS) $(FPGA_TOP) + mkdir -p rev + EXT=sof; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do let COUNT=COUNT+1; done; \ + cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_rev$$COUNT.$$EXT"; + +%.sof: smart.log %.asm.rpt + + +smart.log: $(ASSIGNMENT_FILES) + quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log + +################################################################### +# Project initialization +################################################################### + +$(ASSIGNMENT_FILES): $(QSF_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) + rm -f $(FPGA_TOP).qsf + quartus_sh --prepare -f $(FPGA_FAMILY) -d $(FPGA_DEVICE) -t $(FPGA_TOP) $(FPGA_TOP) + echo >> $(FPGA_TOP).qsf + echo >> $(FPGA_TOP).qsf + echo "# Source files" >> $(FPGA_TOP).qsf + for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \ + case $${x##*.} in \ + v|V) echo set_global_assignment -name VERILOG_FILE $$x >> $(FPGA_TOP).qsf ;;\ + vhd|VHD) echo set_global_assignment -name VHDL_FILE $$x >> $(FPGA_TOP).qsf ;;\ + qip|QIP) echo set_global_assignment -name QIP_FILE $$x >> $(FPGA_TOP).qsf ;;\ + ip|IP) echo set_global_assignment -name IP_FILE $$x >> $(FPGA_TOP).qsf ;;\ + *) echo set_global_assignment -name SOURCE_FILE $$x >> $(FPGA_TOP).qsf ;;\ + esac; \ + done + echo >> $(FPGA_TOP).qsf + echo "# SDC files" >> $(FPGA_TOP).qsf + for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE $$x >> $(FPGA_TOP).qsf; done + for x in $(QSF_FILES_REL); do printf "\n#\n# Included QSF file $$x\n#\n" >> $(FPGA_TOP).qsf; cat $$x >> $(FPGA_TOP).qsf; done + +syn.chg: + $(STAMP) syn.chg +fit.chg: + $(STAMP) fit.chg +sta.chg: + $(STAMP) sta.chg +asm.chg: + $(STAMP) asm.chg diff --git a/example/520N_MX/fpga_10g/fpga.qsf b/example/520N_MX/fpga_10g/fpga.qsf new file mode 100644 index 000000000..ba92c8db0 --- /dev/null +++ b/example/520N_MX/fpga_10g/fpga.qsf @@ -0,0 +1,1033 @@ +# I/O constraints for the BittWare 520N-MX FPGA development board +# part: 1SM21CHU2F53E2VG + +set_global_assignment -name USE_CONF_DONE SDM_IO16 +set_global_assignment -name USE_INIT_DONE SDM_IO0 + +set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 +set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 +set_global_assignment -name USE_PWRMGT_ALERT SDM_IO12 +set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 01 +set_global_assignment -name VID_OPERATION_MODE "PMBUS SLAVE" + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X16" +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V +set_global_assignment -name USE_CHECKSUM_AS_USERCODE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name ENABLE_ED_CRC_CHECK ON +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name MINIMUM_SEU_INTERVAL 0 + +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON + +# Clock and reset +set_location_assignment PIN_BB20 -to "config_clk" + +set_location_assignment PIN_BE17 -to "usr_refclk0" +set_location_assignment PIN_BD17 -to "usr_refclk0(n)" + +set_location_assignment PIN_A24 -to "usr_refclk1" +set_location_assignment PIN_B23 -to "usr_refclk1(n)" + +set_location_assignment PIN_AW31 -to "mem0_refclk" +set_location_assignment PIN_AY31 -to "mem0_refclk(n)" + +set_location_assignment PIN_A42 -to "mem1_refclk" +set_location_assignment PIN_B41 -to "mem1_refclk(n)" + +set_location_assignment PIN_AU31 -to "esram_0_refclk" +set_location_assignment PIN_AU32 -to "esram_0_refclk(n)" + +set_location_assignment PIN_V31 -to "esram_1_refclk" +set_location_assignment PIN_U31 -to "esram_1_refclk(n)" + +set_location_assignment PIN_AR26 -to "hbm_bottom_refclk" +set_location_assignment PIN_AP26 -to "hbm_bottom_refclk(n)" + +set_location_assignment PIN_P27 -to "hbm_top_refclk" +set_location_assignment PIN_R27 -to "hbm_top_refclk(n)" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "config_clk" + +set_instance_assignment -name IO_STANDARD LVDS -to "usr_refclk0" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "usr_refclk0" + +set_instance_assignment -name IO_STANDARD LVDS -to "usr_refclk1" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "usr_refclk1" + +set_instance_assignment -name IO_STANDARD LVDS -to "esram_0_refclk" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "esram_0_refclk" + +set_instance_assignment -name IO_STANDARD LVDS -to "esram_1_refclk" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "esram_1_refclk" + +set_instance_assignment -name IO_STANDARD LVDS -to "hbm_bottom_refclk" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "hbm_bottom_refclk" + +set_instance_assignment -name IO_STANDARD LVDS -to "hbm_top_refclk" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "hbm_top_refclk" + +# LEDs +set_location_assignment PIN_AA39 -to "led_user_grn[0]" +set_location_assignment PIN_AL38 -to "led_user_grn[1]" + +set_location_assignment PIN_AA38 -to "led_user_red[0]" +set_location_assignment PIN_AL39 -to "led_user_red[1]" + +set_location_assignment PIN_AH39 -to "led_qsfp[0]" +set_location_assignment PIN_AJ39 -to "led_qsfp[1]" +set_location_assignment PIN_AK39 -to "led_qsfp[2]" +set_location_assignment PIN_AM38 -to "led_qsfp[3]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "led_user_red[*]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "led_user_grn[*]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "led_qsfp[*]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "led_user_red[*]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "led_user_grn[*]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "led_qsfp[*]" + +# UART +set_location_assignment PIN_BD12 -to "uart_tx" +set_location_assignment PIN_BE12 -to "uart_rx" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "uart_tx" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "uart_rx" + +# I2C +set_location_assignment PIN_BJ17 -to "fpga_i2c_sda" +set_location_assignment PIN_BJ18 -to "fpga_i2c_scl" +set_location_assignment PIN_BK17 -to "fpga_i2c_req_l" +set_location_assignment PIN_BK16 -to "fpga_i2c_mux_gnt" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_i2c_sda" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_i2c_scl" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_i2c_req_l" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_i2c_mux_gnt" + +# BMC SPI +set_location_assignment PIN_BK15 -to "bmc_spi_mosi" +set_location_assignment PIN_BF18 -to "bmc_spi_nss" +set_location_assignment PIN_BF19 -to "bmc_spi_sclk" +set_location_assignment PIN_BL15 -to "bmc_spi_miso" + +set_location_assignment PIN_BH20 -to "bmc_irq" + +set_location_assignment PIN_BH19 -to "fpga_gpio_1" +set_location_assignment PIN_BG20 -to "fpga_rst_n" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_spi_mosi" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_spi_nss" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_spi_sclk" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_spi_miso" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_irq" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_gpio_1" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_rst_n" + +# PCIe banks 1K 1L 1M +set_location_assignment PIN_AE51 -to "pcie_tx[0]" +set_location_assignment PIN_AE50 -to "pcie_tx[0](n)" +set_location_assignment PIN_AC47 -to "pcie_rx[0]" +set_location_assignment PIN_AC46 -to "pcie_rx[0](n)" +set_location_assignment PIN_AD49 -to "pcie_tx[1]" +set_location_assignment PIN_AD48 -to "pcie_tx[1](n)" +set_location_assignment PIN_AD45 -to "pcie_rx[1]" +set_location_assignment PIN_AD44 -to "pcie_rx[1](n)" +set_location_assignment PIN_AC51 -to "pcie_tx[2]" +set_location_assignment PIN_AC50 -to "pcie_tx[2](n)" +set_location_assignment PIN_AA47 -to "pcie_rx[2]" +set_location_assignment PIN_AA46 -to "pcie_rx[2](n)" +set_location_assignment PIN_AB49 -to "pcie_tx[3]" +set_location_assignment PIN_AB48 -to "pcie_tx[3](n)" +set_location_assignment PIN_AB45 -to "pcie_rx[3]" +set_location_assignment PIN_AB44 -to "pcie_rx[3](n)" +set_location_assignment PIN_AA51 -to "pcie_tx[4]" +set_location_assignment PIN_AA50 -to "pcie_tx[4](n)" +set_location_assignment PIN_W47 -to "pcie_rx[4]" +set_location_assignment PIN_W46 -to "pcie_rx[4](n)" +set_location_assignment PIN_Y49 -to "pcie_tx[5]" +set_location_assignment PIN_Y48 -to "pcie_tx[5](n)" +set_location_assignment PIN_Y45 -to "pcie_rx[5]" +set_location_assignment PIN_Y44 -to "pcie_rx[5](n)" +set_location_assignment PIN_W51 -to "pcie_tx[6]" +set_location_assignment PIN_W50 -to "pcie_tx[6](n)" +set_location_assignment PIN_U47 -to "pcie_rx[6]" +set_location_assignment PIN_U46 -to "pcie_rx[6](n)" +set_location_assignment PIN_V49 -to "pcie_tx[7]" +set_location_assignment PIN_V48 -to "pcie_tx[7](n)" +set_location_assignment PIN_V45 -to "pcie_rx[7]" +set_location_assignment PIN_V44 -to "pcie_rx[7](n)" +set_location_assignment PIN_U51 -to "pcie_tx[8]" +set_location_assignment PIN_U50 -to "pcie_tx[8](n)" +set_location_assignment PIN_R47 -to "pcie_rx[8]" +set_location_assignment PIN_R46 -to "pcie_rx[8](n)" +set_location_assignment PIN_T49 -to "pcie_tx[9]" +set_location_assignment PIN_T48 -to "pcie_tx[9](n)" +set_location_assignment PIN_T45 -to "pcie_rx[9]" +set_location_assignment PIN_T44 -to "pcie_rx[9](n)" +set_location_assignment PIN_R51 -to "pcie_tx[10]" +set_location_assignment PIN_R50 -to "pcie_tx[10](n)" +set_location_assignment PIN_N47 -to "pcie_rx[10]" +set_location_assignment PIN_N46 -to "pcie_rx[10](n)" +set_location_assignment PIN_P49 -to "pcie_tx[11]" +set_location_assignment PIN_P48 -to "pcie_tx[11](n)" +set_location_assignment PIN_P45 -to "pcie_rx[11]" +set_location_assignment PIN_P44 -to "pcie_rx[11](n)" +set_location_assignment PIN_N51 -to "pcie_tx[12]" +set_location_assignment PIN_N50 -to "pcie_tx[12](n)" +set_location_assignment PIN_L47 -to "pcie_rx[12]" +set_location_assignment PIN_L46 -to "pcie_rx[12](n)" +set_location_assignment PIN_M49 -to "pcie_tx[13]" +set_location_assignment PIN_M48 -to "pcie_tx[13](n)" +set_location_assignment PIN_M45 -to "pcie_rx[13]" +set_location_assignment PIN_M44 -to "pcie_rx[13](n)" +set_location_assignment PIN_L51 -to "pcie_tx[14]" +set_location_assignment PIN_L50 -to "pcie_tx[14](n)" +set_location_assignment PIN_J47 -to "pcie_rx[14]" +set_location_assignment PIN_J46 -to "pcie_rx[14](n)" +set_location_assignment PIN_K49 -to "pcie_tx[15]" +set_location_assignment PIN_K48 -to "pcie_tx[15](n)" +set_location_assignment PIN_K45 -to "pcie_rx[15]" +set_location_assignment PIN_K44 -to "pcie_rx[15](n)" + +set_location_assignment PIN_AC43 -to "pcie_refclk" +set_location_assignment PIN_AC42 -to "pcie_refclk(n)" + +set_location_assignment PIN_Y39 -to "pcie_perstn" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "pcie_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "pcie_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "pcie_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "pcie_rx[*]" + +set_instance_assignment -name IO_STANDARD "HCSL" -to "pcie_refclk" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "pcie_perstn" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "pcie_perstn" + +# QSFP + +# QSFP0 (bank 1D) +set_location_assignment PIN_BD49 -to "qsfp0_tx[0]" +set_location_assignment PIN_BD48 -to "qsfp0_tx[0](n)" +set_location_assignment PIN_BB45 -to "qsfp0_rx[0]" +set_location_assignment PIN_BB44 -to "qsfp0_rx[0](n)" +set_location_assignment PIN_BC51 -to "qsfp0_tx[1]" +set_location_assignment PIN_BC50 -to "qsfp0_tx[1](n)" +set_location_assignment PIN_BC47 -to "qsfp0_rx[1]" +set_location_assignment PIN_BC46 -to "qsfp0_rx[1](n)" +set_location_assignment PIN_BA51 -to "qsfp0_tx[2]" +set_location_assignment PIN_BA50 -to "qsfp0_tx[2](n)" +set_location_assignment PIN_AY45 -to "qsfp0_rx[2]" +set_location_assignment PIN_AY44 -to "qsfp0_rx[2](n)" +set_location_assignment PIN_AY49 -to "qsfp0_tx[3]" +set_location_assignment PIN_AY48 -to "qsfp0_tx[3](n)" +set_location_assignment PIN_AW47 -to "qsfp0_rx[3]" +set_location_assignment PIN_AW46 -to "qsfp0_rx[3](n)" +set_location_assignment PIN_AU43 -to "qsfp0_refclk" +set_location_assignment PIN_AU42 -to "qsfp0_refclk(n)" +set_location_assignment PIN_AR43 -to "qsfp0_rcvrd_refclk" +set_location_assignment PIN_AR42 -to "qsfp0_rcvrd_refclk(n)" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp0_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp0_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp0_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp0_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp0_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp0_refclk" +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp0_rcvrd_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp0_rcvrd_refclk" + +# QSFP1 (bank 1E) +set_location_assignment PIN_AV49 -to "qsfp1_tx[0]" +set_location_assignment PIN_AV48 -to "qsfp1_tx[0](n)" +set_location_assignment PIN_AU47 -to "qsfp1_rx[0]" +set_location_assignment PIN_AU46 -to "qsfp1_rx[0](n)" +set_location_assignment PIN_AU51 -to "qsfp1_tx[1]" +set_location_assignment PIN_AU50 -to "qsfp1_tx[1](n)" +set_location_assignment PIN_AT45 -to "qsfp1_rx[1]" +set_location_assignment PIN_AT44 -to "qsfp1_rx[1](n)" +set_location_assignment PIN_AR51 -to "qsfp1_tx[2]" +set_location_assignment PIN_AR50 -to "qsfp1_tx[2](n)" +set_location_assignment PIN_AP45 -to "qsfp1_rx[2]" +set_location_assignment PIN_AP44 -to "qsfp1_rx[2](n)" +set_location_assignment PIN_AM49 -to "qsfp1_tx[3]" +set_location_assignment PIN_AM48 -to "qsfp1_tx[3](n)" +set_location_assignment PIN_AL47 -to "qsfp1_rx[3]" +set_location_assignment PIN_AL46 -to "qsfp1_rx[3](n)" +set_location_assignment PIN_AN43 -to "qsfp1_refclk" +set_location_assignment PIN_AN42 -to "qsfp1_refclk(n)" +set_location_assignment PIN_AL43 -to "qsfp1_rcvrd_refclk" +set_location_assignment PIN_AL42 -to "qsfp1_rcvrd_refclk(n)" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp1_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp1_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp1_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp1_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp1_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp1_refclk" +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp1_rcvrd_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp1_rcvrd_refclk" + +# QSFP2 (bank 1F, hard 100G MAC) +set_location_assignment PIN_AN51 -to "qsfp2_tx[0]" +set_location_assignment PIN_AN50 -to "qsfp2_tx[0](n)" +set_location_assignment PIN_AM45 -to "qsfp2_rx[0]" +set_location_assignment PIN_AM44 -to "qsfp2_rx[0](n)" +set_location_assignment PIN_AL51 -to "qsfp2_tx[1]" +set_location_assignment PIN_AL50 -to "qsfp2_tx[1](n)" +set_location_assignment PIN_AK45 -to "qsfp2_rx[1]" +set_location_assignment PIN_AK44 -to "qsfp2_rx[1](n)" +set_location_assignment PIN_AJ51 -to "qsfp2_tx[2]" +set_location_assignment PIN_AJ50 -to "qsfp2_tx[2](n)" +set_location_assignment PIN_AH45 -to "qsfp2_rx[2]" +set_location_assignment PIN_AH44 -to "qsfp2_rx[2](n)" +set_location_assignment PIN_AG51 -to "qsfp2_tx[3]" +set_location_assignment PIN_AG50 -to "qsfp2_tx[3](n)" +set_location_assignment PIN_AF45 -to "qsfp2_rx[3]" +set_location_assignment PIN_AF44 -to "qsfp2_rx[3](n)" +set_location_assignment PIN_AJ43 -to "qsfp2_refclk" +set_location_assignment PIN_AJ42 -to "qsfp2_refclk(n)" +set_location_assignment PIN_AG43 -to "qsfp2_rcvrd_refclk" +set_location_assignment PIN_AG42 -to "qsfp2_rcvrd_refclk(n)" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp2_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp2_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp2_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp2_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp2_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp2_refclk" +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp2_rcvrd_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp2_rcvrd_refclk" + +# QSFP3 (bank 1N, hard 100G MAC) +set_location_assignment PIN_J51 -to "qsfp3_tx[0]" +set_location_assignment PIN_J50 -to "qsfp3_tx[0](n)" +set_location_assignment PIN_H45 -to "qsfp3_rx[0]" +set_location_assignment PIN_H44 -to "qsfp3_rx[0](n)" +set_location_assignment PIN_G51 -to "qsfp3_tx[1]" +set_location_assignment PIN_G50 -to "qsfp3_tx[1](n)" +set_location_assignment PIN_F45 -to "qsfp3_rx[1]" +set_location_assignment PIN_F44 -to "qsfp3_rx[1](n)" +set_location_assignment PIN_E51 -to "qsfp3_tx[2]" +set_location_assignment PIN_D51 -to "qsfp3_tx[2](n)" +set_location_assignment PIN_D45 -to "qsfp3_rx[2]" +set_location_assignment PIN_D44 -to "qsfp3_rx[2](n)" +set_location_assignment PIN_C50 -to "qsfp3_tx[3]" +set_location_assignment PIN_B50 -to "qsfp3_tx[3](n)" +set_location_assignment PIN_B44 -to "qsfp3_rx[3]" +set_location_assignment PIN_A44 -to "qsfp3_rx[3](n)" +set_location_assignment PIN_N43 -to "qsfp3_refclk" +set_location_assignment PIN_N42 -to "qsfp3_refclk(n)" +set_location_assignment PIN_L43 -to "qsfp3_rcvrd_refclk" +set_location_assignment PIN_L42 -to "qsfp3_rcvrd_refclk(n)" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp3_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp3_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp3_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp3_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp3_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp3_refclk" +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp3_rcvrd_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp3_rcvrd_refclk" + +set_location_assignment PIN_H19 -to "qsfp_irq_n[0]" +set_location_assignment PIN_H18 -to "qsfp_irq_n[1]" +set_location_assignment PIN_A22 -to "qsfp_irq_n[2]" +set_location_assignment PIN_C23 -to "qsfp_irq_n[3]" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp_irq_n[*]" + +# OCuLink + +# OCuLink 0 (J26, PCIe, banks 4C, 4D) +set_location_assignment PIN_BL5 -to "oc0_tx[0]" +set_location_assignment PIN_BL6 -to "oc0_tx[0](n)" +set_location_assignment PIN_BH7 -to "oc0_rx[0]" +set_location_assignment PIN_BH8 -to "oc0_rx[0](n)" +set_location_assignment PIN_BK3 -to "oc0_tx[1]" +set_location_assignment PIN_BK4 -to "oc0_tx[1](n)" +set_location_assignment PIN_BJ5 -to "oc0_rx[1]" +set_location_assignment PIN_BJ6 -to "oc0_rx[1](n)" +set_location_assignment PIN_BH3 -to "oc0_tx[2]" +set_location_assignment PIN_BH4 -to "oc0_tx[2](n)" +set_location_assignment PIN_BG5 -to "oc0_rx[2]" +set_location_assignment PIN_BG6 -to "oc0_rx[2](n)" +set_location_assignment PIN_BG1 -to "oc0_tx[3]" +set_location_assignment PIN_BG2 -to "oc0_tx[3](n)" +set_location_assignment PIN_BF7 -to "oc0_rx[3]" +set_location_assignment PIN_BF8 -to "oc0_rx[3](n)" +set_location_assignment PIN_BF3 -to "oc0_tx[4]" +set_location_assignment PIN_BF4 -to "oc0_tx[4](n)" +set_location_assignment PIN_BE5 -to "oc0_rx[4]" +set_location_assignment PIN_BE6 -to "oc0_rx[4](n)" +set_location_assignment PIN_BE1 -to "oc0_tx[5]" +set_location_assignment PIN_BE2 -to "oc0_tx[5](n)" +set_location_assignment PIN_BD7 -to "oc0_rx[5]" +set_location_assignment PIN_BD8 -to "oc0_rx[5](n)" +set_location_assignment PIN_BD3 -to "oc0_tx[6]" +set_location_assignment PIN_BD4 -to "oc0_tx[6](n)" +set_location_assignment PIN_BB7 -to "oc0_rx[6]" +set_location_assignment PIN_BB8 -to "oc0_rx[6](n)" +set_location_assignment PIN_BC1 -to "oc0_tx[7]" +set_location_assignment PIN_BC2 -to "oc0_tx[7](n)" +set_location_assignment PIN_BC5 -to "oc0_rx[7]" +set_location_assignment PIN_BC6 -to "oc0_rx[7](n)" +set_location_assignment PIN_AW9 -to "oc0_refclk_1" +set_location_assignment PIN_AW10 -to "oc0_refclk_1(n)" +set_location_assignment PIN_BA9 -to "oc0_refclk_2" +set_location_assignment PIN_BA10 -to "oc0_refclk_2(n)" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc0_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc0_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc0_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc0_rx[*]" + +set_instance_assignment -name IO_STANDARD "HCSL" -to "oc0_refclk_1" +set_instance_assignment -name IO_STANDARD "HCSL" -to "oc0_refclk_2" + +set_location_assignment PIN_BL10 -to "oc0_gpio[0]" +set_location_assignment PIN_BH10 -to "oc0_gpio[1]" +set_location_assignment PIN_BG10 -to "oc0_gpio[2]" +set_location_assignment PIN_BF10 -to "oc0_gpio[3]" +set_location_assignment PIN_AT15 -to "oc0_gpio[4]" +set_location_assignment PIN_AR15 -to "oc0_gpio[5]" +set_location_assignment PIN_AV15 -to "oc0_gpio[6]" +set_location_assignment PIN_AU15 -to "oc0_gpio[7]" +set_location_assignment PIN_AW14 -to "oc0_gpio[8]" +set_location_assignment PIN_AV14 -to "oc0_gpio[9]" +set_location_assignment PIN_AY14 -to "oc0_gpio[10]" +set_location_assignment PIN_BA14 -to "oc0_gpio[11]" +set_location_assignment PIN_BB15 -to "oc0_gpio[12]" +set_location_assignment PIN_BA15 -to "oc0_gpio[13]" +set_location_assignment PIN_BC14 -to "oc0_gpio[14]" +set_location_assignment PIN_BC15 -to "oc0_gpio[15]" + +set_location_assignment PIN_BE10 -to "oc0_gpio_dir[0]" +set_location_assignment PIN_BD10 -to "oc0_gpio_dir[1]" +set_location_assignment PIN_BC10 -to "oc0_gpio_dir[2]" +set_location_assignment PIN_AP39 -to "oc0_gpio_dir[3]" +set_location_assignment PIN_BF14 -to "oc0_gpio_dir[4]" +set_location_assignment PIN_BF13 -to "oc0_gpio_dir[5]" +set_location_assignment PIN_BH13 -to "oc0_gpio_dir[6]" +set_location_assignment PIN_BG13 -to "oc0_gpio_dir[7]" +set_location_assignment PIN_BJ13 -to "oc0_gpio_dir[8]" +set_location_assignment PIN_BJ12 -to "oc0_gpio_dir[9]" +set_location_assignment PIN_BJ14 -to "oc0_gpio_dir[10]" +set_location_assignment PIN_BK14 -to "oc0_gpio_dir[11]" +set_location_assignment PIN_BL14 -to "oc0_gpio_dir[12]" +set_location_assignment PIN_BL13 -to "oc0_gpio_dir[13]" +set_location_assignment PIN_AU17 -to "oc0_gpio_dir[14]" +set_location_assignment PIN_AU16 -to "oc0_gpio_dir[15]" + +set_location_assignment PIN_AW17 -to "oc0_buff_en_n[0]" +set_location_assignment PIN_AY17 -to "oc0_buff_en_n[1]" +set_location_assignment PIN_AW16 -to "oc0_buff_en_n[2]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio[0]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio[1]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio[2]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio[3]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio[0]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio[1]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio[2]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio[3]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[4]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[5]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[6]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[7]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[8]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[9]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[10]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[11]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[12]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[13]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[14]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[15]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio_dir[0]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio_dir[1]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio_dir[2]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio_dir[3]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio_dir[0]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio_dir[1]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio_dir[2]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio_dir[3]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[4]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[5]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[6]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[7]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[8]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[9]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[10]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[11]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[12]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[13]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[14]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[15]" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_buff_en_n[*]" + +# OCuLink 1 (J27, PCIe, banks 4K, 4L) +set_location_assignment PIN_AF3 -to "oc1_tx[0]" +set_location_assignment PIN_AF4 -to "oc1_tx[0](n)" +set_location_assignment PIN_AE5 -to "oc1_rx[0]" +set_location_assignment PIN_AE6 -to "oc1_rx[0](n)" +set_location_assignment PIN_AE1 -to "oc1_tx[1]" +set_location_assignment PIN_AE2 -to "oc1_tx[1](n)" +set_location_assignment PIN_AD7 -to "oc1_rx[1]" +set_location_assignment PIN_AD8 -to "oc1_rx[1](n)" +set_location_assignment PIN_AD3 -to "oc1_tx[2]" +set_location_assignment PIN_AD4 -to "oc1_tx[2](n)" +set_location_assignment PIN_AC5 -to "oc1_rx[2]" +set_location_assignment PIN_AC6 -to "oc1_rx[2](n)" +set_location_assignment PIN_AC1 -to "oc1_tx[3]" +set_location_assignment PIN_AC2 -to "oc1_tx[3](n)" +set_location_assignment PIN_AB7 -to "oc1_rx[3]" +set_location_assignment PIN_AB8 -to "oc1_rx[3](n)" +set_location_assignment PIN_AB3 -to "oc1_tx[4]" +set_location_assignment PIN_AB4 -to "oc1_tx[4](n)" +set_location_assignment PIN_AA5 -to "oc1_rx[4]" +set_location_assignment PIN_AA6 -to "oc1_rx[4](n)" +set_location_assignment PIN_AA1 -to "oc1_tx[5]" +set_location_assignment PIN_AA2 -to "oc1_tx[5](n)" +set_location_assignment PIN_Y7 -to "oc1_rx[5]" +set_location_assignment PIN_Y8 -to "oc1_rx[5](n)" +set_location_assignment PIN_Y3 -to "oc1_tx[6]" +set_location_assignment PIN_Y4 -to "oc1_tx[6](n)" +set_location_assignment PIN_W5 -to "oc1_rx[6]" +set_location_assignment PIN_W6 -to "oc1_rx[6](n)" +set_location_assignment PIN_W1 -to "oc1_tx[7]" +set_location_assignment PIN_W2 -to "oc1_tx[7](n)" +set_location_assignment PIN_V7 -to "oc1_rx[7]" +set_location_assignment PIN_V8 -to "oc1_rx[7](n)" +set_location_assignment PIN_AC9 -to "oc1_refclk_1" +set_location_assignment PIN_AC10 -to "oc1_refclk_1(n)" +set_location_assignment PIN_AE9 -to "oc1_refclk_2" +set_location_assignment PIN_AE10 -to "oc1_refclk_2(n)" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc1_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc1_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc1_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc1_rx[*]" + +set_instance_assignment -name IO_STANDARD "HCSL" -to "oc1_refclk_1" +set_instance_assignment -name IO_STANDARD "HCSL" -to "oc1_refclk_2" + +set_location_assignment PIN_AG13 -to "oc1_gpio[0]" +set_location_assignment PIN_AL13 -to "oc1_gpio[1]" +set_location_assignment PIN_AM13 -to "oc1_gpio[2]" +set_location_assignment PIN_AN13 -to "oc1_gpio[3]" +set_location_assignment PIN_C16 -to "oc1_gpio[4]" +set_location_assignment PIN_D16 -to "oc1_gpio[5]" +set_location_assignment PIN_B15 -to "oc1_gpio[6]" +set_location_assignment PIN_B16 -to "oc1_gpio[7]" +set_location_assignment PIN_C14 -to "oc1_gpio[8]" +set_location_assignment PIN_C15 -to "oc1_gpio[9]" +set_location_assignment PIN_A14 -to "oc1_gpio[10]" +set_location_assignment PIN_A15 -to "oc1_gpio[11]" +set_location_assignment PIN_E15 -to "oc1_gpio[12]" +set_location_assignment PIN_F15 -to "oc1_gpio[13]" +set_location_assignment PIN_H15 -to "oc1_gpio[14]" +set_location_assignment PIN_G15 -to "oc1_gpio[15]" + +set_location_assignment PIN_AH13 -to "oc1_gpio_dir[0]" +set_location_assignment PIN_AP13 -to "oc1_gpio_dir[1]" +set_location_assignment PIN_AF13 -to "oc1_gpio_dir[2]" +set_location_assignment PIN_AC38 -to "oc1_gpio_dir[3]" +set_location_assignment PIN_J16 -to "oc1_gpio_dir[4]" +set_location_assignment PIN_K16 -to "oc1_gpio_dir[5]" +set_location_assignment PIN_L15 -to "oc1_gpio_dir[6]" +set_location_assignment PIN_K15 -to "oc1_gpio_dir[7]" +set_location_assignment PIN_M15 -to "oc1_gpio_dir[8]" +set_location_assignment PIN_N15 -to "oc1_gpio_dir[9]" +set_location_assignment PIN_M16 -to "oc1_gpio_dir[10]" +set_location_assignment PIN_N16 -to "oc1_gpio_dir[11]" +set_location_assignment PIN_P16 -to "oc1_gpio_dir[12]" +set_location_assignment PIN_R16 -to "oc1_gpio_dir[13]" +set_location_assignment PIN_A13 -to "oc1_gpio_dir[14]" +set_location_assignment PIN_A12 -to "oc1_gpio_dir[15]" + +set_location_assignment PIN_B13 -to "oc1_buff_en_n[0]" +set_location_assignment PIN_C13 -to "oc1_buff_en_n[1]" +set_location_assignment PIN_B12 -to "oc1_buff_en_n[2]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio[0]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio[1]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio[2]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio[3]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio[0]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio[1]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio[2]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio[3]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[4]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[5]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[6]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[7]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[8]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[9]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[10]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[11]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[12]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[13]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[14]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[15]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio_dir[0]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio_dir[1]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio_dir[2]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio_dir[3]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio_dir[0]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio_dir[1]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio_dir[2]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio_dir[3]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[4]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[5]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[6]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[7]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[8]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[9]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[10]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[11]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[12]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[13]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[14]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[15]" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_buff_en_n[*]" + +# OCuLink 2 (J22, 25G, banks 4N, 4M) +set_location_assignment PIN_P3 -to "oc2_tx[0]" +set_location_assignment PIN_P4 -to "oc2_tx[0](n)" +set_location_assignment PIN_N5 -to "oc2_rx[0]" +set_location_assignment PIN_N6 -to "oc2_rx[0](n)" +set_location_assignment PIN_N1 -to "oc2_tx[1]" +set_location_assignment PIN_N2 -to "oc2_tx[1](n)" +set_location_assignment PIN_M7 -to "oc2_rx[1]" +set_location_assignment PIN_M8 -to "oc2_rx[1](n)" +set_location_assignment PIN_L1 -to "oc2_tx[2]" +set_location_assignment PIN_L2 -to "oc2_tx[2](n)" +set_location_assignment PIN_K7 -to "oc2_rx[2]" +set_location_assignment PIN_K8 -to "oc2_rx[2](n)" +set_location_assignment PIN_K3 -to "oc2_tx[3]" +set_location_assignment PIN_K4 -to "oc2_tx[3](n)" +set_location_assignment PIN_J5 -to "oc2_rx[3]" +set_location_assignment PIN_J6 -to "oc2_rx[3](n)" +set_location_assignment PIN_H3 -to "oc2_tx[4]" +set_location_assignment PIN_H4 -to "oc2_tx[4](n)" +set_location_assignment PIN_G5 -to "oc2_rx[4]" +set_location_assignment PIN_G6 -to "oc2_rx[4](n)" +set_location_assignment PIN_G1 -to "oc2_tx[5]" +set_location_assignment PIN_G2 -to "oc2_tx[5](n)" +set_location_assignment PIN_F7 -to "oc2_rx[5]" +set_location_assignment PIN_F8 -to "oc2_rx[5](n)" +set_location_assignment PIN_E1 -to "oc2_tx[6]" +set_location_assignment PIN_E2 -to "oc2_tx[6](n)" +set_location_assignment PIN_D7 -to "oc2_rx[6]" +set_location_assignment PIN_D8 -to "oc2_rx[6](n)" +set_location_assignment PIN_D3 -to "oc2_tx[7]" +set_location_assignment PIN_D4 -to "oc2_tx[7](n)" +set_location_assignment PIN_C5 -to "oc2_rx[7]" +set_location_assignment PIN_C6 -to "oc2_rx[7](n)" +set_location_assignment PIN_R9 -to "oc2_refclk_1" +set_location_assignment PIN_R10 -to "oc2_refclk_1(n)" +set_location_assignment PIN_L9 -to "oc2_refclk_2" +set_location_assignment PIN_L10 -to "oc2_refclk_2(n)" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc2_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc2_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc2_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc2_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "oc2_refclk_1" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "oc2_refclk_1" +set_instance_assignment -name IO_STANDARD LVDS -to "oc2_refclk_2" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "oc2_refclk_2" + +set_location_assignment PIN_AJ13 -to "oc2_perst_n" +set_location_assignment PIN_AC39 -to "oc2_buff_in_sel" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc2_perst_n" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc2_perst_n" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc2_buff_in_sel" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc2_buff_in_sel" + +# OCuLink 3 (J23, 25G, banks 4E, 4F) +set_location_assignment PIN_AV3 -to "oc3_tx[0]" +set_location_assignment PIN_AV4 -to "oc3_tx[0](n)" +set_location_assignment PIN_AU5 -to "oc3_rx[0]" +set_location_assignment PIN_AU6 -to "oc3_rx[0](n)" +set_location_assignment PIN_AU1 -to "oc3_tx[1]" +set_location_assignment PIN_AU2 -to "oc3_tx[1](n)" +set_location_assignment PIN_AT7 -to "oc3_rx[1]" +set_location_assignment PIN_AT8 -to "oc3_rx[1](n)" +set_location_assignment PIN_AR1 -to "oc3_tx[2]" +set_location_assignment PIN_AR2 -to "oc3_tx[2](n)" +set_location_assignment PIN_AP7 -to "oc3_rx[2]" +set_location_assignment PIN_AP8 -to "oc3_rx[2](n)" +set_location_assignment PIN_AP3 -to "oc3_tx[3]" +set_location_assignment PIN_AP4 -to "oc3_tx[3](n)" +set_location_assignment PIN_AN5 -to "oc3_rx[3]" +set_location_assignment PIN_AN6 -to "oc3_rx[3](n)" +set_location_assignment PIN_AM3 -to "oc3_tx[4]" +set_location_assignment PIN_AM4 -to "oc3_tx[4](n)" +set_location_assignment PIN_AL5 -to "oc3_rx[4]" +set_location_assignment PIN_AL6 -to "oc3_rx[4](n)" +set_location_assignment PIN_AL1 -to "oc3_tx[5]" +set_location_assignment PIN_AL2 -to "oc3_tx[5](n)" +set_location_assignment PIN_AK7 -to "oc3_rx[5]" +set_location_assignment PIN_AK8 -to "oc3_rx[5](n)" +set_location_assignment PIN_AJ1 -to "oc3_tx[6]" +set_location_assignment PIN_AJ2 -to "oc3_tx[6](n)" +set_location_assignment PIN_AH7 -to "oc3_rx[6]" +set_location_assignment PIN_AH8 -to "oc3_rx[6](n)" +set_location_assignment PIN_AH3 -to "oc3_tx[7]" +set_location_assignment PIN_AH4 -to "oc3_tx[7](n)" +set_location_assignment PIN_AG5 -to "oc3_rx[7]" +set_location_assignment PIN_AG6 -to "oc3_rx[7](n)" +set_location_assignment PIN_AL9 -to "oc3_refclk_1" +set_location_assignment PIN_AL10 -to "oc3_refclk_1(n)" +set_location_assignment PIN_AG9 -to "oc3_refclk_2" +set_location_assignment PIN_AG10 -to "oc3_refclk_2(n)" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc3_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc3_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc3_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc3_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "oc3_refclk_1" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "oc3_refclk_1" +set_instance_assignment -name IO_STANDARD LVDS -to "oc3_refclk_2" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "oc3_refclk_2" + +set_location_assignment PIN_BK10 -to "oc3_perst_n" +set_location_assignment PIN_AN39 -to "oc3_buff_in_sel" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc3_perst_n" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc3_perst_n" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc3_buff_in_sel" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc3_buff_in_sel" + +# DDR4 module 0 +set_location_assignment PIN_BA33 -to "mem0_rzq" + +set_location_assignment PIN_BC31 -to "mem0_alert_n" +set_location_assignment PIN_AW33 -to "mem0_reset_n" +set_location_assignment PIN_BH35 -to "mem0_par" + +set_location_assignment PIN_BL34 -to "mem0_a[0]" +set_location_assignment PIN_BK34 -to "mem0_a[1]" +set_location_assignment PIN_BJ34 -to "mem0_a[2]" +set_location_assignment PIN_BH34 -to "mem0_a[3]" +set_location_assignment PIN_BH33 -to "mem0_a[4]" +set_location_assignment PIN_BJ33 -to "mem0_a[5]" +set_location_assignment PIN_BK35 -to "mem0_a[6]" +set_location_assignment PIN_BL35 -to "mem0_a[7]" +set_location_assignment PIN_BD33 -to "mem0_a[8]" +set_location_assignment PIN_BC33 -to "mem0_a[9]" +set_location_assignment PIN_BG33 -to "mem0_a[10]" +set_location_assignment PIN_BF33 -to "mem0_a[11]" +set_location_assignment PIN_BB33 -to "mem0_a[12]" +set_location_assignment PIN_BB32 -to "mem0_a[13]" +set_location_assignment PIN_BA32 -to "mem0_a[14]" +set_location_assignment PIN_AW32 -to "mem0_a[15]" +set_location_assignment PIN_AY32 -to "mem0_a[16]" +set_location_assignment PIN_BD32 -to "mem0_bg[0]" +set_location_assignment PIN_AV33 -to "mem0_bg[1]" +set_location_assignment PIN_AV34 -to "mem0_act_n" +set_location_assignment PIN_BA34 -to "mem0_odt[0]" +set_location_assignment PIN_AY34 -to "mem0_odt[1]" +set_location_assignment PIN_BF34 -to "mem0_ck_p[0]" +set_location_assignment PIN_BE34 -to "mem0_ck_n[0]" +set_location_assignment PIN_AW34 -to "mem0_cs_n[0]" +set_location_assignment PIN_BG35 -to "mem0_cs_n[1]" +set_location_assignment PIN_BD34 -to "mem0_cke[0]" +set_location_assignment PIN_BC34 -to "mem0_cke[1]" +set_location_assignment PIN_BF32 -to "mem0_ba[0]" +set_location_assignment PIN_BE32 -to "mem0_ba[1]" + +set_location_assignment PIN_BF23 -to "mem0_dqs_p[0]" +set_location_assignment PIN_BG23 -to "mem0_dqs_n[0]" +set_location_assignment PIN_BJ22 -to "mem0_dqs_p[1]" +set_location_assignment PIN_BK22 -to "mem0_dqs_n[1]" +set_location_assignment PIN_BC26 -to "mem0_dqs_p[2]" +set_location_assignment PIN_BD26 -to "mem0_dqs_n[2]" +set_location_assignment PIN_BG25 -to "mem0_dqs_p[3]" +set_location_assignment PIN_BF25 -to "mem0_dqs_n[3]" +set_location_assignment PIN_BK26 -to "mem0_dqs_p[4]" +set_location_assignment PIN_BK25 -to "mem0_dqs_n[4]" +set_location_assignment PIN_BK24 -to "mem0_dqs_p[5]" +set_location_assignment PIN_BJ24 -to "mem0_dqs_n[5]" +set_location_assignment PIN_BJ28 -to "mem0_dqs_p[6]" +set_location_assignment PIN_BH28 -to "mem0_dqs_n[6]" +set_location_assignment PIN_BK27 -to "mem0_dqs_p[7]" +set_location_assignment PIN_BJ27 -to "mem0_dqs_n[7]" +set_location_assignment PIN_BF29 -to "mem0_dqs_p[8]" +set_location_assignment PIN_BE29 -to "mem0_dqs_n[8]" +set_location_assignment PIN_BA28 -to "mem0_dqs_p[9]" +set_location_assignment PIN_BA29 -to "mem0_dqs_n[9]" +set_location_assignment PIN_BB30 -to "mem0_dqs_p[10]" +set_location_assignment PIN_BC30 -to "mem0_dqs_n[10]" +set_location_assignment PIN_BH30 -to "mem0_dqs_p[11]" +set_location_assignment PIN_BG30 -to "mem0_dqs_n[11]" +set_location_assignment PIN_BK39 -to "mem0_dqs_p[12]" +set_location_assignment PIN_BL39 -to "mem0_dqs_n[12]" +set_location_assignment PIN_BG40 -to "mem0_dqs_p[13]" +set_location_assignment PIN_BH40 -to "mem0_dqs_n[13]" +set_location_assignment PIN_BH38 -to "mem0_dqs_p[14]" +set_location_assignment PIN_BJ38 -to "mem0_dqs_n[14]" +set_location_assignment PIN_BC38 -to "mem0_dqs_p[15]" +set_location_assignment PIN_BD38 -to "mem0_dqs_n[15]" +set_location_assignment PIN_BA37 -to "mem0_dqs_p[16]" +set_location_assignment PIN_BB37 -to "mem0_dqs_n[16]" +set_location_assignment PIN_BG37 -to "mem0_dqs_p[17]" +set_location_assignment PIN_BF37 -to "mem0_dqs_n[17]" + +set_location_assignment PIN_BE24 -to "mem0_dq[0]" +set_location_assignment PIN_BF24 -to "mem0_dq[1]" +set_location_assignment PIN_BH24 -to "mem0_dq[2]" +set_location_assignment PIN_BH25 -to "mem0_dq[3]" +set_location_assignment PIN_BL23 -to "mem0_dq[4]" +set_location_assignment PIN_BL22 -to "mem0_dq[5]" +set_location_assignment PIN_BJ23 -to "mem0_dq[6]" +set_location_assignment PIN_BH23 -to "mem0_dq[7]" +set_location_assignment PIN_AW28 -to "mem0_dq[8]" +set_location_assignment PIN_AW27 -to "mem0_dq[9]" +set_location_assignment PIN_AY27 -to "mem0_dq[10]" +set_location_assignment PIN_BA27 -to "mem0_dq[11]" +set_location_assignment PIN_BE26 -to "mem0_dq[12]" +set_location_assignment PIN_BE25 -to "mem0_dq[13]" +set_location_assignment PIN_BB26 -to "mem0_dq[14]" +set_location_assignment PIN_BB27 -to "mem0_dq[15]" +set_location_assignment PIN_BE27 -to "mem0_dq[16]" +set_location_assignment PIN_BF27 -to "mem0_dq[17]" +set_location_assignment PIN_BG26 -to "mem0_dq[18]" +set_location_assignment PIN_BG27 -to "mem0_dq[19]" +set_location_assignment PIN_BL25 -to "mem0_dq[20]" +set_location_assignment PIN_BL24 -to "mem0_dq[21]" +set_location_assignment PIN_BJ26 -to "mem0_dq[22]" +set_location_assignment PIN_BH26 -to "mem0_dq[23]" +set_location_assignment PIN_BC28 -to "mem0_dq[24]" +set_location_assignment PIN_BB28 -to "mem0_dq[25]" +set_location_assignment PIN_BD28 -to "mem0_dq[26]" +set_location_assignment PIN_BD27 -to "mem0_dq[27]" +set_location_assignment PIN_BL28 -to "mem0_dq[28]" +set_location_assignment PIN_BL27 -to "mem0_dq[29]" +set_location_assignment PIN_BG28 -to "mem0_dq[30]" +set_location_assignment PIN_BF28 -to "mem0_dq[31]" +set_location_assignment PIN_BK30 -to "mem0_dq[32]" +set_location_assignment PIN_BL30 -to "mem0_dq[33]" +set_location_assignment PIN_BK29 -to "mem0_dq[34]" +set_location_assignment PIN_BL29 -to "mem0_dq[35]" +set_location_assignment PIN_BD29 -to "mem0_dq[36]" +set_location_assignment PIN_BC29 -to "mem0_dq[37]" +set_location_assignment PIN_BJ29 -to "mem0_dq[38]" +set_location_assignment PIN_BH29 -to "mem0_dq[39]" +set_location_assignment PIN_AV30 -to "mem0_dq[40]" +set_location_assignment PIN_AV29 -to "mem0_dq[41]" +set_location_assignment PIN_AW29 -to "mem0_dq[42]" +set_location_assignment PIN_AY29 -to "mem0_dq[43]" +set_location_assignment PIN_BF30 -to "mem0_dq[44]" +set_location_assignment PIN_BE30 -to "mem0_dq[45]" +set_location_assignment PIN_AY30 -to "mem0_dq[46]" +set_location_assignment PIN_BA30 -to "mem0_dq[47]" +set_location_assignment PIN_BJ39 -to "mem0_dq[48]" +set_location_assignment PIN_BH39 -to "mem0_dq[49]" +set_location_assignment PIN_BF39 -to "mem0_dq[50]" +set_location_assignment PIN_BE39 -to "mem0_dq[51]" +set_location_assignment PIN_BE40 -to "mem0_dq[52]" +set_location_assignment PIN_BF40 -to "mem0_dq[53]" +set_location_assignment PIN_BK40 -to "mem0_dq[54]" +set_location_assignment PIN_BL40 -to "mem0_dq[55]" +set_location_assignment PIN_BL37 -to "mem0_dq[56]" +set_location_assignment PIN_BL38 -to "mem0_dq[57]" +set_location_assignment PIN_BJ37 -to "mem0_dq[58]" +set_location_assignment PIN_BK37 -to "mem0_dq[59]" +set_location_assignment PIN_BC39 -to "mem0_dq[60]" +set_location_assignment PIN_BD39 -to "mem0_dq[61]" +set_location_assignment PIN_BF38 -to "mem0_dq[62]" +set_location_assignment PIN_BG38 -to "mem0_dq[63]" +set_location_assignment PIN_BC36 -to "mem0_dq[64]" +set_location_assignment PIN_BB36 -to "mem0_dq[65]" +set_location_assignment PIN_AY36 -to "mem0_dq[66]" +set_location_assignment PIN_AW36 -to "mem0_dq[67]" +set_location_assignment PIN_BD37 -to "mem0_dq[68]" +set_location_assignment PIN_BE37 -to "mem0_dq[69]" +set_location_assignment PIN_AW37 -to "mem0_dq[70]" +set_location_assignment PIN_AY37 -to "mem0_dq[71]" + +# DDR4 module 1 +set_location_assignment PIN_A40 -to "mem1_rzq" + +set_location_assignment PIN_P36 -to "mem1_alert_n" +set_location_assignment PIN_F35 -to "mem1_reset_n" +set_location_assignment PIN_A39 -to "mem1_par" + +set_location_assignment PIN_H34 -to "mem1_a[0]" +set_location_assignment PIN_J34 -to "mem1_a[1]" +set_location_assignment PIN_G35 -to "mem1_a[2]" +set_location_assignment PIN_H35 -to "mem1_a[3]" +set_location_assignment PIN_L35 -to "mem1_a[4]" +set_location_assignment PIN_K35 -to "mem1_a[5]" +set_location_assignment PIN_L34 -to "mem1_a[6]" +set_location_assignment PIN_K34 -to "mem1_a[7]" +set_location_assignment PIN_N34 -to "mem1_a[8]" +set_location_assignment PIN_P34 -to "mem1_a[9]" +set_location_assignment PIN_M35 -to "mem1_a[10]" +set_location_assignment PIN_N35 -to "mem1_a[11]" +set_location_assignment PIN_B40 -to "mem1_a[12]" +set_location_assignment PIN_C39 -to "mem1_a[13]" +set_location_assignment PIN_D39 -to "mem1_a[14]" +set_location_assignment PIN_D38 -to "mem1_a[15]" +set_location_assignment PIN_C38 -to "mem1_a[16]" +set_location_assignment PIN_G37 -to "mem1_bg[0]" +set_location_assignment PIN_F34 -to "mem1_bg[1]" +set_location_assignment PIN_E35 -to "mem1_act_n" +set_location_assignment PIN_C36 -to "mem1_odt[0]" +set_location_assignment PIN_D36 -to "mem1_odt[1]" +set_location_assignment PIN_B37 -to "mem1_ck_p[0]" +set_location_assignment PIN_B38 -to "mem1_ck_n[0]" +set_location_assignment PIN_E36 -to "mem1_cs_n[0]" +set_location_assignment PIN_A38 -to "mem1_cs_n[1]" +set_location_assignment PIN_B36 -to "mem1_cke[0]" +set_location_assignment PIN_A37 -to "mem1_cke[1]" +set_location_assignment PIN_D37 -to "mem1_ba[0]" +set_location_assignment PIN_F37 -to "mem1_ba[1]" + +set_location_assignment PIN_K29 -to "mem1_dqs_p[0]" +set_location_assignment PIN_L29 -to "mem1_dqs_n[0]" +set_location_assignment PIN_R30 -to "mem1_dqs_p[1]" +set_location_assignment PIN_R29 -to "mem1_dqs_n[1]" +set_location_assignment PIN_E29 -to "mem1_dqs_p[2]" +set_location_assignment PIN_F29 -to "mem1_dqs_n[2]" +set_location_assignment PIN_G30 -to "mem1_dqs_p[3]" +set_location_assignment PIN_H30 -to "mem1_dqs_n[3]" +set_location_assignment PIN_M31 -to "mem1_dqs_p[4]" +set_location_assignment PIN_N31 -to "mem1_dqs_n[4]" +set_location_assignment PIN_P32 -to "mem1_dqs_p[5]" +set_location_assignment PIN_R32 -to "mem1_dqs_n[5]" +set_location_assignment PIN_G33 -to "mem1_dqs_p[6]" +set_location_assignment PIN_F33 -to "mem1_dqs_n[6]" +set_location_assignment PIN_K32 -to "mem1_dqs_p[7]" +set_location_assignment PIN_J32 -to "mem1_dqs_n[7]" +set_location_assignment PIN_D32 -to "mem1_dqs_p[8]" +set_location_assignment PIN_E32 -to "mem1_dqs_n[8]" +set_location_assignment PIN_G31 -to "mem1_dqs_p[9]" +set_location_assignment PIN_H31 -to "mem1_dqs_n[9]" +set_location_assignment PIN_B31 -to "mem1_dqs_p[10]" +set_location_assignment PIN_A32 -to "mem1_dqs_n[10]" +set_location_assignment PIN_A35 -to "mem1_dqs_p[11]" +set_location_assignment PIN_B35 -to "mem1_dqs_n[11]" +set_location_assignment PIN_E41 -to "mem1_dqs_p[12]" +set_location_assignment PIN_E40 -to "mem1_dqs_n[12]" +set_location_assignment PIN_C42 -to "mem1_dqs_p[13]" +set_location_assignment PIN_B42 -to "mem1_dqs_n[13]" +set_location_assignment PIN_H38 -to "mem1_dqs_p[14]" +set_location_assignment PIN_J38 -to "mem1_dqs_n[14]" +set_location_assignment PIN_H39 -to "mem1_dqs_p[15]" +set_location_assignment PIN_G38 -to "mem1_dqs_n[15]" +set_location_assignment PIN_E42 -to "mem1_dqs_p[16]" +set_location_assignment PIN_F42 -to "mem1_dqs_n[16]" +set_location_assignment PIN_L38 -to "mem1_dqs_p[17]" +set_location_assignment PIN_L39 -to "mem1_dqs_n[17]" + +set_location_assignment PIN_H29 -to "mem1_dq[0]" +set_location_assignment PIN_J29 -to "mem1_dq[1]" +set_location_assignment PIN_M30 -to "mem1_dq[2]" +set_location_assignment PIN_N30 -to "mem1_dq[3]" +set_location_assignment PIN_N29 -to "mem1_dq[4]" +set_location_assignment PIN_P29 -to "mem1_dq[5]" +set_location_assignment PIN_K30 -to "mem1_dq[6]" +set_location_assignment PIN_L30 -to "mem1_dq[7]" +set_location_assignment PIN_A28 -to "mem1_dq[8]" +set_location_assignment PIN_A29 -to "mem1_dq[9]" +set_location_assignment PIN_C28 -to "mem1_dq[10]" +set_location_assignment PIN_B28 -to "mem1_dq[11]" +set_location_assignment PIN_E30 -to "mem1_dq[12]" +set_location_assignment PIN_F30 -to "mem1_dq[13]" +set_location_assignment PIN_C29 -to "mem1_dq[14]" +set_location_assignment PIN_D29 -to "mem1_dq[15]" +set_location_assignment PIN_N33 -to "mem1_dq[16]" +set_location_assignment PIN_P33 -to "mem1_dq[17]" +set_location_assignment PIN_L33 -to "mem1_dq[18]" +set_location_assignment PIN_M33 -to "mem1_dq[19]" +set_location_assignment PIN_P31 -to "mem1_dq[20]" +set_location_assignment PIN_R31 -to "mem1_dq[21]" +set_location_assignment PIN_T33 -to "mem1_dq[22]" +set_location_assignment PIN_T32 -to "mem1_dq[23]" +set_location_assignment PIN_C34 -to "mem1_dq[24]" +set_location_assignment PIN_C35 -to "mem1_dq[25]" +set_location_assignment PIN_D34 -to "mem1_dq[26]" +set_location_assignment PIN_E34 -to "mem1_dq[27]" +set_location_assignment PIN_M32 -to "mem1_dq[28]" +set_location_assignment PIN_L32 -to "mem1_dq[29]" +set_location_assignment PIN_H33 -to "mem1_dq[30]" +set_location_assignment PIN_J33 -to "mem1_dq[31]" +set_location_assignment PIN_J31 -to "mem1_dq[32]" +set_location_assignment PIN_K31 -to "mem1_dq[33]" +set_location_assignment PIN_B33 -to "mem1_dq[34]" +set_location_assignment PIN_B32 -to "mem1_dq[35]" +set_location_assignment PIN_F32 -to "mem1_dq[36]" +set_location_assignment PIN_G32 -to "mem1_dq[37]" +set_location_assignment PIN_D33 -to "mem1_dq[38]" +set_location_assignment PIN_C33 -to "mem1_dq[39]" +set_location_assignment PIN_B30 -to "mem1_dq[40]" +set_location_assignment PIN_A30 -to "mem1_dq[41]" +set_location_assignment PIN_C30 -to "mem1_dq[42]" +set_location_assignment PIN_C31 -to "mem1_dq[43]" +set_location_assignment PIN_A33 -to "mem1_dq[44]" +set_location_assignment PIN_A34 -to "mem1_dq[45]" +set_location_assignment PIN_D31 -to "mem1_dq[46]" +set_location_assignment PIN_E31 -to "mem1_dq[47]" +set_location_assignment PIN_E39 -to "mem1_dq[48]" +set_location_assignment PIN_F40 -to "mem1_dq[49]" +set_location_assignment PIN_F38 -to "mem1_dq[50]" +set_location_assignment PIN_F39 -to "mem1_dq[51]" +set_location_assignment PIN_C41 -to "mem1_dq[52]" +set_location_assignment PIN_C40 -to "mem1_dq[53]" +set_location_assignment PIN_D42 -to "mem1_dq[54]" +set_location_assignment PIN_D41 -to "mem1_dq[55]" +set_location_assignment PIN_R37 -to "mem1_dq[56]" +set_location_assignment PIN_P37 -to "mem1_dq[57]" +set_location_assignment PIN_P38 -to "mem1_dq[58]" +set_location_assignment PIN_N38 -to "mem1_dq[59]" +set_location_assignment PIN_J37 -to "mem1_dq[60]" +set_location_assignment PIN_K37 -to "mem1_dq[61]" +set_location_assignment PIN_L37 -to "mem1_dq[62]" +set_location_assignment PIN_M37 -to "mem1_dq[63]" +set_location_assignment PIN_H41 -to "mem1_dq[64]" +set_location_assignment PIN_G41 -to "mem1_dq[65]" +set_location_assignment PIN_G42 -to "mem1_dq[66]" +set_location_assignment PIN_H42 -to "mem1_dq[67]" +set_location_assignment PIN_K39 -to "mem1_dq[68]" +set_location_assignment PIN_J39 -to "mem1_dq[69]" +set_location_assignment PIN_H40 -to "mem1_dq[70]" +set_location_assignment PIN_G40 -to "mem1_dq[71]" diff --git a/example/520N_MX/fpga_10g/fpga.sdc b/example/520N_MX/fpga_10g/fpga.sdc new file mode 100644 index 000000000..9c5afa6e6 --- /dev/null +++ b/example/520N_MX/fpga_10g/fpga.sdc @@ -0,0 +1,170 @@ +# Timing constraints for BittWare 520N-MX + +set_time_format -unit ns -decimal_places 3 + +# Clock constraints +create_clock -name {config_clk} -period 20.000 [ get_ports {config_clk} ] +create_clock -name {usr_refclk0} -period 3.333 [ get_ports {usr_refclk0} ] +create_clock -name {usr_refclk1} -period 3.333 [ get_ports {usr_refclk1} ] + +create_clock -name {mem0_refclk} -period 3.333 [ get_ports {mem0_refclk} ] +create_clock -name {mem1_refclk} -period 3.333 [ get_ports {mem1_refclk} ] + +create_clock -name {esram_0_refclk} -period 5.000 [ get_ports {esram_0_refclk} ] +create_clock -name {esram_1_refclk} -period 5.000 [ get_ports {esram_1_refclk} ] + +create_clock -name {hbm_top_refclk} -period 5.000 [ get_ports {hbm_top_refclk} ] +create_clock -name {hbm_bottom_refclk} -period 5.000 [ get_ports {hbm_bottom_refclk} ] + +create_clock -name {pcie_refclk} -period 10.000 [ get_ports {pcie_refclk} ] + +create_clock -name {qsfp0_refclk} -period 1.551 [ get_ports {qsfp0_refclk} ] +create_clock -name {qsfp1_refclk} -period 1.551 [ get_ports {qsfp1_refclk} ] +create_clock -name {qsfp2_refclk} -period 1.551 [ get_ports {qsfp2_refclk} ] +create_clock -name {qsfp3_refclk} -period 1.551 [ get_ports {qsfp3_refclk} ] + +derive_clock_uncertainty + +set_clock_groups -asynchronous -group [ get_clocks {config_clk} ] +set_clock_groups -asynchronous -group [ get_clocks {usr_refclk0} ] +set_clock_groups -asynchronous -group [ get_clocks {usr_refclk1} ] + +set_clock_groups -asynchronous -group [ get_clocks {mem0_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {mem1_refclk} ] + +set_clock_groups -asynchronous -group [ get_clocks {esram_0_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {esram_1_refclk} ] + +set_clock_groups -asynchronous -group [ get_clocks {hbm_top_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {hbm_bottom_refclk} ] + +set_clock_groups -asynchronous -group [ get_clocks {pcie_refclk} ] + +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_refclk} ] + +# JTAG constraints +create_clock -name {altera_reserved_tck} -period 62.500 {altera_reserved_tck} + +set_clock_groups -asynchronous -group {altera_reserved_tck} + +# IO constraints +set_false_path -to "led_user_red[*]" +set_false_path -to "led_user_grn[*]" +set_false_path -to "led_qsfp[*]" + +set_false_path -to "uart_rx" +set_false_path -from "uart_tx" + +set_false_path -to "fpga_i2c_sda" +set_false_path -from "fpga_i2c_sda" +set_false_path -to "fpga_i2c_scl" +set_false_path -from "fpga_i2c_scl" +set_false_path -to "fpga_i2c_req_l" +set_false_path -from "fpga_i2c_mux_gnt" + +set_false_path -from "fpga_gpio_1" +set_false_path -from "fpga_rst_n" + +set_false_path -from "pcie_perstn" + +set_false_path -from "qsfp_irq_n[*]" + +set_false_path -to "oc0_gpio[*]" +set_false_path -from "oc0_gpio[*]" +set_false_path -to "oc0_gpio_dir[*]" +set_false_path -to "oc0_buff_en_n[*]" + +set_false_path -to "oc1_gpio[*]" +set_false_path -from "oc1_gpio[*]" +set_false_path -to "oc1_gpio_dir[*]" +set_false_path -to "oc1_buff_en_n[*]" + +set_false_path -from "oc2_perst_n" +set_false_path -to "oc2_buff_in_sel" + +set_false_path -from "oc3_perst_n" +set_false_path -to "oc3_buff_in_sel" + + +source ../lib/eth/syn/quartus_pro/eth_mac_fifo.sdc +source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc +source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc + +# clocking infrastructure +constrain_sync_reset_inst "sync_reset_100mhz_inst" + +# PHY clocks +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ] + +# PHY resets +constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp2_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst" +constrain_sync_reset_inst "qsfp3_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst" + +# 10G MAC +constrain_eth_mac_fifo_inst "core_inst|eth_mac_10g_fifo_inst" +constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|rx_fifo|fifo_inst" +constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|tx_fifo|fifo_inst" diff --git a/example/520N_MX/fpga_10g/fpga/Makefile b/example/520N_MX/fpga_10g/fpga/Makefile new file mode 100644 index 000000000..760aa4fdf --- /dev/null +++ b/example/520N_MX/fpga_10g/fpga/Makefile @@ -0,0 +1,68 @@ + +# FPGA settings +FPGA_TOP = fpga +FPGA_FAMILY = "Stratix 10 MX" +FPGA_DEVICE = 1SM21CHU2F53E2VG + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# IP files +IP_TCL_FILES += ip/reset_release.tcl +IP_TCL_FILES += ip/eth_xcvr.tcl +IP_TCL_FILES += ip/eth_xcvr_pll.tcl +IP_TCL_FILES += ip/eth_xcvr_reset.tcl + +# QSF files +QSF_FILES = fpga.qsf + +# SDC files +SDC_FILES = fpga.sdc + +include ../common/quartus_pro.mk + +program: fpga + quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" diff --git a/example/520N_MX/fpga_10g/ip/eth_xcvr.tcl b/example/520N_MX/fpga_10g/ip/eth_xcvr.tcl new file mode 100644 index 000000000..a5666cf44 --- /dev/null +++ b/example/520N_MX/fpga_10g/ip/eth_xcvr.tcl @@ -0,0 +1,382 @@ +package require -exact qsys 20.4 + +# create the system "eth_xcvr" +proc do_create_eth_xcvr {} { + # create the system + create_system eth_xcvr + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_native_s10_htile_0 altera_xcvr_native_s10_htile + set_instance_parameter_value xcvr_native_s10_htile_0 {adapter_ehip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_link} {lr} + set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_voltage} {1_1V} + set_instance_parameter_value xcvr_native_s10_htile_0 {avmm_ehip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {base_device} {Unknown} + set_instance_parameter_value xcvr_native_s10_htile_0 {bonded_mode} {not_bonded} + set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_cnt} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_select} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {channel_type} {GX} + set_instance_parameter_value xcvr_native_s10_htile_0 {channels} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout2_sel} {clock_delay_measurement_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout_sel} {clock_delay_measurement_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {design_environment} {NATIVE} + set_instance_parameter_value xcvr_native_s10_htile_0 {design_example_filename} {dexample} + set_instance_parameter_value xcvr_native_s10_htile_0 {disable_digital_reset_sequencer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {disable_reset_sequencer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {duplex_mode} {duplex} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t1} {60} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t2} {150} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t3} {1000} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_advanced_user_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_background_cal_gui} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_channel_powerdown} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_de_hardware_debug} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_debug_ports} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_direct_reset_control} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_double_rate_transfer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_early_spd_chng} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ehip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_fast_sim} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hard_reset} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_insert_eios_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_mac_total_control} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_manual_bonding_settings} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_clock_delay_measurement} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_tx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_latency_measurement} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_data_valid} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_bitslip} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_blk_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_clr_errblk_count} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_crc32_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber_clr_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_align_clr} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_insert} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_latency_adj_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pempty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pfull} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_rd_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtodata} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtoref} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_clkslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_iqtxrx_clkout} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_qpipulldn} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_polinv} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_seriallpbken} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitrev_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslipboundarysel} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_byterev_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_signaldetect} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_a1a2size} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_patternalign} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_dll_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_bitslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_burst_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_latency_adj_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pempty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pfull} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_elecidle} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_iqtxrx_clkout} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipulldn} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipullup} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_rxfound} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_txdetectrx} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_polinv} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_std_bitslipboundarysel} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_adaptation} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_hclk} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_rx_elecidle} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_sw} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_manual_cdr_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_prbs} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_async_transfer} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rcfg_tx_digitalreset_release_ctrl} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rx_fast_pipeln_reg} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_simple_interface} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_split_interface} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_transparent_pcs} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_coreclkin2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_fast_pipeln_reg} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_workaround_rules} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_advanced_user_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_low_latency_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pcs_pma_width} {64} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pld_pcs_width} {66} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_64b66b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_bitslip_enable} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_blksync_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_crcchk_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_descram_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_dispchk_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_mfrm_length} {2048} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_type} {10G} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_64b66b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_bitslip_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcerr_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_dispgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_burst_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_mfrm_length} {2048} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_len} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_randomdispbit_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_seed} {2.88230376152e+17} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_sh_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {generate_add_hdl_instance_example} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {generate_docs} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_channels} {x1} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_prot_mode} {gen1} + set_instance_parameter_value xcvr_native_s10_htile_0 {loopback_tx_clk_sel} {internal_clk} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {message_level} {error} + set_instance_parameter_value xcvr_native_s10_htile_0 {number_physical_bonding_clocks} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {osc_clk_divider} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_rx_dv_mode} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_tx_dv_mode} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {parallel_loopback_mode} {disable} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcie_rate_match} {Bypass} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_direct_width} {8} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_reset_sequencing_mode} {not_bonded} + set_instance_parameter_value xcvr_native_s10_htile_0 {pll_select} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {plls} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {pma_mode} {basic} + set_instance_parameter_value xcvr_native_s10_htile_0 {protocol_mode} {basic_enh} + set_instance_parameter_value xcvr_native_s10_htile_0 {qsf_assignments_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_debug} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable_avmm_busy_port} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_rcfg_10} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_files_as_common_package} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_h_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_iface_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_jtag_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_mif_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_multi_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_cnt} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data0} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data1} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data2} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data3} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data4} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data5} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data6} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data7} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_select} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_reduced_files_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data0} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data1} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data2} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data3} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data4} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data5} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data6} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data7} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_separate_avmm_busy} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_shared} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sv_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_txt_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_use_clk_reset_only} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {reduced_reset_sim_time} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout2_sel} {pcs_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout_sel} {pma_div_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_coreclkin_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_ac_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_eq_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_align_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_control_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_mode} {Phase compensation} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pempty} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pfull} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_mode} {ctle_dfe} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_analog_mode} {user_custom} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_div_clkout_divider} {33} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_optimal_settings} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_term_sel} {r_r2} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ppm_detect_threshold} {1000} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_vga_dc_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_capability_reg_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_freq} {644.531250} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_receiver_detect_src} {iqclk} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_csr_soft_logic_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_data_rate} {10312.5} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_embedded_debug_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_calibration} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_eios_rx_protect} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_hip_cal_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_odi_soft_logic_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_pcs_bonding_master} {Auto} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_prbs_soft_logic_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_rcfg_emb_strm_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_user_identifier} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_low_latency_bypass_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_pcs_pma_width} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_8b10b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_bitrev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byte_deser_mode} {Disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byterev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_mode} {disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_n} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_p} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_fast_sync_status_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_mode} {bitslip} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern} {0.0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern_len} {7} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_renumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rgnumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rknumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rvnumber} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_disp_ctrl_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitrev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitslip_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byte_ser_mode} {Disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byterev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {support_mode} {user_mode} + set_instance_parameter_value xcvr_native_s10_htile_0 {suppress_design_example_messages} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tile_type_suffix} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout2_sel} {pcs_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout_sel} {pma_div_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_coreclkin_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_mode} {Phase compensation} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pempty} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pfull} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pcs_bonding_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_refclk} {644.53125} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_type} {ATX} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_analog_mode} {user_custom} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_clk_div} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_compensation_en} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_div_clkout_divider} {33} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_optimal_settings} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_output_swing_ctrl} {12} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_1st_post_tap} {negative} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_pre_tap_1t} {negative} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_1st_post_tap} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_pre_tap_1t} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_slew_rate_ctrl} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_term_sel} {r_r1} + set_instance_parameter_value xcvr_native_s10_htile_0 {use_rx_clkout2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {use_tx_clkout2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {usr_rx_dv_mode} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {usr_tx_dv_mode} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {validation_rule_select} {} + set_instance_property xcvr_native_s10_htile_0 AUTO_EXPORT true + + # add wirelevel expressions + + # add the exports + set_interface_property tx_analogreset EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset + set_interface_property rx_analogreset EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset + set_interface_property tx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset + set_interface_property rx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset + set_interface_property tx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset_stat + set_interface_property rx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset_stat + set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset_stat + set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset_stat + set_interface_property tx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.tx_cal_busy + set_interface_property rx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.rx_cal_busy + set_interface_property tx_serial_clk0 EXPORT_OF xcvr_native_s10_htile_0.tx_serial_clk0 + set_interface_property rx_cdr_refclk0 EXPORT_OF xcvr_native_s10_htile_0.rx_cdr_refclk0 + set_interface_property tx_serial_data EXPORT_OF xcvr_native_s10_htile_0.tx_serial_data + set_interface_property rx_serial_data EXPORT_OF xcvr_native_s10_htile_0.rx_serial_data + set_interface_property rx_is_lockedtoref EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtoref + set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtodata + set_interface_property tx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.tx_coreclkin + set_interface_property rx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.rx_coreclkin + set_interface_property tx_clkout EXPORT_OF xcvr_native_s10_htile_0.tx_clkout + set_interface_property tx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.tx_clkout2 + set_interface_property rx_clkout EXPORT_OF xcvr_native_s10_htile_0.rx_clkout + set_interface_property rx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.rx_clkout2 + set_interface_property tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.tx_parallel_data + set_interface_property tx_control EXPORT_OF xcvr_native_s10_htile_0.tx_control + set_interface_property tx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.tx_enh_data_valid + set_interface_property unused_tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_tx_parallel_data + set_interface_property rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.rx_parallel_data + set_interface_property rx_control EXPORT_OF xcvr_native_s10_htile_0.rx_control + set_interface_property rx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.rx_enh_data_valid + set_interface_property unused_rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_rx_parallel_data + set_interface_property rx_bitslip EXPORT_OF xcvr_native_s10_htile_0.rx_bitslip + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/example/520N_MX/fpga_10g/ip/eth_xcvr_pll.tcl b/example/520N_MX/fpga_10g/ip/eth_xcvr_pll.tcl new file mode 100644 index 000000000..ef63522f5 --- /dev/null +++ b/example/520N_MX/fpga_10g/ip/eth_xcvr_pll.tcl @@ -0,0 +1,141 @@ +package require -exact qsys 20.4 + +# create the system "eth_xcvr_pll" +proc do_create_eth_xcvr_pll {} { + # create the system + create_system eth_xcvr_pll + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_atx_pll_s10_htile_0 altera_xcvr_atx_pll_s10_htile + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {base_device} {Unknown} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {bw_sel} {high} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_abv_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_abv_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_blw_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {disabled} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_abv} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_blw} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_analog_resets} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_bonding_clks} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_cascade_out} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_debug_ports_parameters} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_ext_lockdetect_ports} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_fb_comp_bonding} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hfreq_clk} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hip_cal_done_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_manual_configuration} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_pcie_clksw} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_reset} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_clk} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_hip_connectivity} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_atx_cal_busy_port} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pll_lock} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_vco_bypass} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {generate_add_hdl_instance_example} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_aux_clkin_cnt} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_div} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {message_level} {error} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {pma_width} {64} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GX clock output buffer} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {prot_mode} {Basic} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_debug} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_atx_pll_s10} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_files_as_common_package} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_h_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_jtag_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_mif_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_multi_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_cnt} {2} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data0} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data1} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data2} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data3} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data4} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data5} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data6} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data7} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_select} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_reduced_files_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_separate_avmm_busy} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sv_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_txt_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_cnt} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_index} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_altera_xcvr_atx_pll_s10_calibration_en} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_capability_reg_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_csr_soft_logic_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_fref_clock_frequency} {156.25} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_hip_cal_en} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_k_counter} {1.0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_counter} {4} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_predivider} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_counter} {4} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_m_counter} {24} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_manual_reference_clock_frequency} {200.0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {5156.25} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_rcfg_emb_strm_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_ref_clk_div} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_user_identifier} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {silicon_rev} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {support_mode} {user_mode} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {test_mode} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {usr_analog_voltage} {1_1V} + set_instance_property xcvr_atx_pll_s10_htile_0 AUTO_EXPORT true + + # add wirelevel expressions + + # add the exports + set_interface_property pll_refclk0 EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_refclk0 + set_interface_property tx_serial_clk EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk + set_interface_property pll_locked EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_locked + set_interface_property pll_cal_busy EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_cal_busy + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr_pll.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr_pll} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr_pll +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr_pll + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/example/520N_MX/fpga_10g/ip/eth_xcvr_reset.tcl b/example/520N_MX/fpga_10g/ip/eth_xcvr_reset.tcl new file mode 100644 index 000000000..4f786240f --- /dev/null +++ b/example/520N_MX/fpga_10g/ip/eth_xcvr_reset.tcl @@ -0,0 +1,87 @@ +package require -exact qsys 20.4 + +# create the system "eth_xcvr_reset" +proc do_create_eth_xcvr_reset {} { + # create the system + create_system eth_xcvr_reset + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_reset_control_s10_0 altera_xcvr_reset_control_s10 + set_instance_parameter_value xcvr_reset_control_s10_0 {CHANNELS} {4} + set_instance_parameter_value xcvr_reset_control_s10_0 {ENABLE_DIGITAL_SEQ} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {PLLS} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {REDUCED_SIM_TIME} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {RX_ENABLE} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {RX_MANUAL_RESET} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {RX_PER_CHANNEL} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {SYS_CLK_IN_MHZ} {300} + set_instance_parameter_value xcvr_reset_control_s10_0 {TILE_TYPE} {h_tile} + set_instance_parameter_value xcvr_reset_control_s10_0 {TX_ENABLE} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {TX_MANUAL_RESET} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {TX_PER_CHANNEL} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {TX_PLL_ENABLE} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_PLL_LOCK_HYST} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_PLL_POWERDOWN} {1000} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_RX_ANALOGRESET} {40} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_RX_DIGITALRESET} {5000} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_TX_ANALOGRESET} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_TX_DIGITALRESET} {20} + set_instance_parameter_value xcvr_reset_control_s10_0 {gui_pll_cal_busy} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {gui_split_interfaces} {0} + set_instance_property xcvr_reset_control_s10_0 AUTO_EXPORT true + + # add wirelevel expressions + + # add the exports + set_interface_property clock EXPORT_OF xcvr_reset_control_s10_0.clock + set_interface_property reset EXPORT_OF xcvr_reset_control_s10_0.reset + set_interface_property tx_analogreset EXPORT_OF xcvr_reset_control_s10_0.tx_analogreset + set_interface_property tx_digitalreset EXPORT_OF xcvr_reset_control_s10_0.tx_digitalreset + set_interface_property tx_ready EXPORT_OF xcvr_reset_control_s10_0.tx_ready + set_interface_property pll_locked EXPORT_OF xcvr_reset_control_s10_0.pll_locked + set_interface_property pll_select EXPORT_OF xcvr_reset_control_s10_0.pll_select + set_interface_property tx_cal_busy EXPORT_OF xcvr_reset_control_s10_0.tx_cal_busy + set_interface_property tx_analogreset_stat EXPORT_OF xcvr_reset_control_s10_0.tx_analogreset_stat + set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_reset_control_s10_0.tx_digitalreset_stat + set_interface_property pll_cal_busy EXPORT_OF xcvr_reset_control_s10_0.pll_cal_busy + set_interface_property rx_analogreset EXPORT_OF xcvr_reset_control_s10_0.rx_analogreset + set_interface_property rx_digitalreset EXPORT_OF xcvr_reset_control_s10_0.rx_digitalreset + set_interface_property rx_ready EXPORT_OF xcvr_reset_control_s10_0.rx_ready + set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_reset_control_s10_0.rx_is_lockedtodata + set_interface_property rx_cal_busy EXPORT_OF xcvr_reset_control_s10_0.rx_cal_busy + set_interface_property rx_analogreset_stat EXPORT_OF xcvr_reset_control_s10_0.rx_analogreset_stat + set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_reset_control_s10_0.rx_digitalreset_stat + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr_reset.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr_reset} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr_reset +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr_reset + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/example/520N_MX/fpga_10g/ip/reset_release.tcl b/example/520N_MX/fpga_10g/ip/reset_release.tcl new file mode 100644 index 000000000..b79c1ae73 --- /dev/null +++ b/example/520N_MX/fpga_10g/ip/reset_release.tcl @@ -0,0 +1,50 @@ +package require -exact qsys 20.4 + +# create the system "reset_release" +proc do_create_reset_release {} { + # create the system + create_system reset_release + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate + set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} + set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true + + # add wirelevel expressions + + # add the exports + set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {reset_release.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {reset_release} + + # save the system + sync_sysinfo_parameters + save_system reset_release +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_reset_release + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/example/520N_MX/fpga_10g/lib/eth b/example/520N_MX/fpga_10g/lib/eth new file mode 120000 index 000000000..11a54ed36 --- /dev/null +++ b/example/520N_MX/fpga_10g/lib/eth @@ -0,0 +1 @@ +../../../../ \ No newline at end of file diff --git a/example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..85ace0759 --- /dev/null +++ b/example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,273 @@ +/* + +Copyright (c) 2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper ( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + input wire xcvr_ref_clk, + output wire [3:0] xcvr_tx_serial_data, + input wire [3:0] xcvr_rx_serial_data, + + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [63:0] phy_1_xgmii_txd, + input wire [7:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [63:0] phy_1_xgmii_rxd, + output wire [7:0] phy_1_xgmii_rxc, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [63:0] phy_2_xgmii_txd, + input wire [7:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [63:0] phy_2_xgmii_rxd, + output wire [7:0] phy_2_xgmii_rxc, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [63:0] phy_3_xgmii_txd, + input wire [7:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [63:0] phy_3_xgmii_rxd, + output wire [7:0] phy_3_xgmii_rxc, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [63:0] phy_4_xgmii_txd, + input wire [7:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [63:0] phy_4_xgmii_rxd, + output wire [7:0] phy_4_xgmii_rxc, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber +); + +wire xcvr_pll_locked; +wire xcvr_pll_cal_busy; + +wire xcvr_tx_serial_clk; + +wire [3:0] xcvr_tx_analogreset; +wire [3:0] xcvr_rx_analogreset; +wire [3:0] xcvr_tx_digitalreset; +wire [3:0] xcvr_rx_digitalreset; +wire [3:0] xcvr_tx_analogreset_stat; +wire [3:0] xcvr_rx_analogreset_stat; +wire [3:0] xcvr_tx_digitalreset_stat; +wire [3:0] xcvr_rx_digitalreset_stat; +wire [3:0] xcvr_tx_cal_busy; +wire [3:0] xcvr_rx_cal_busy; +wire [3:0] xcvr_rx_is_lockedtoref; +wire [3:0] xcvr_rx_is_lockedtodata; +wire [3:0] xcvr_tx_ready; +wire [3:0] xcvr_rx_ready; + +eth_xcvr_reset eth_xcvr_reset_inst ( + .clock (xcvr_ctrl_clk), + .reset (xcvr_ctrl_rst), + .tx_analogreset (xcvr_tx_analogreset), + .tx_digitalreset (xcvr_tx_digitalreset), + .tx_ready (xcvr_tx_ready), + .pll_locked (xcvr_pll_locked), + .pll_select (4'd0), + .tx_cal_busy (xcvr_tx_cal_busy), + .tx_analogreset_stat (xcvr_tx_analogreset_stat), + .tx_digitalreset_stat (xcvr_tx_digitalreset_stat), + .pll_cal_busy (xcvr_pll_cal_busy), + .rx_analogreset (xcvr_rx_analogreset), + .rx_digitalreset (xcvr_rx_digitalreset), + .rx_ready (xcvr_rx_ready), + .rx_is_lockedtodata (xcvr_rx_is_lockedtodata), + .rx_cal_busy (xcvr_rx_cal_busy), + .rx_analogreset_stat (xcvr_rx_analogreset_stat), + .rx_digitalreset_stat (xcvr_rx_digitalreset_stat) +); + +eth_xcvr_pll eth_xcvr_pll_inst ( + .pll_refclk0 (xcvr_ref_clk), + .tx_serial_clk (xcvr_tx_serial_clk), + .pll_locked (xcvr_pll_locked), + .pll_cal_busy (xcvr_pll_cal_busy) +); + +eth_xcvr_phy_wrapper eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + .xcvr_tx_analogreset(xcvr_tx_analogreset[0]), + .xcvr_rx_analogreset(xcvr_rx_analogreset[0]), + .xcvr_tx_digitalreset(xcvr_tx_digitalreset[0]), + .xcvr_rx_digitalreset(xcvr_rx_digitalreset[0]), + .xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[0]), + .xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[0]), + .xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[0]), + .xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[0]), + .xcvr_tx_cal_busy(xcvr_tx_cal_busy[0]), + .xcvr_rx_cal_busy(xcvr_rx_cal_busy[0]), + .xcvr_tx_serial_clk(xcvr_tx_serial_clk), + .xcvr_rx_cdr_refclk(xcvr_ref_clk), + .xcvr_tx_serial_data(xcvr_tx_serial_data[0]), + .xcvr_rx_serial_data(xcvr_rx_serial_data[0]), + .xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[0]), + .xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[0]), + .xcvr_tx_ready(xcvr_tx_ready[0]), + .xcvr_rx_ready(xcvr_rx_ready[0]), + + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber) +); + +eth_xcvr_phy_wrapper eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + .xcvr_tx_analogreset(xcvr_tx_analogreset[1]), + .xcvr_rx_analogreset(xcvr_rx_analogreset[1]), + .xcvr_tx_digitalreset(xcvr_tx_digitalreset[1]), + .xcvr_rx_digitalreset(xcvr_rx_digitalreset[1]), + .xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[1]), + .xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[1]), + .xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[1]), + .xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[1]), + .xcvr_tx_cal_busy(xcvr_tx_cal_busy[1]), + .xcvr_rx_cal_busy(xcvr_rx_cal_busy[1]), + .xcvr_tx_serial_clk(xcvr_tx_serial_clk), + .xcvr_rx_cdr_refclk(xcvr_ref_clk), + .xcvr_tx_serial_data(xcvr_tx_serial_data[1]), + .xcvr_rx_serial_data(xcvr_rx_serial_data[1]), + .xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[1]), + .xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[1]), + .xcvr_tx_ready(xcvr_tx_ready[1]), + .xcvr_rx_ready(xcvr_rx_ready[1]), + + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber) +); + +eth_xcvr_phy_wrapper eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + .xcvr_tx_analogreset(xcvr_tx_analogreset[2]), + .xcvr_rx_analogreset(xcvr_rx_analogreset[2]), + .xcvr_tx_digitalreset(xcvr_tx_digitalreset[2]), + .xcvr_rx_digitalreset(xcvr_rx_digitalreset[2]), + .xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[2]), + .xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[2]), + .xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[2]), + .xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[2]), + .xcvr_tx_cal_busy(xcvr_tx_cal_busy[2]), + .xcvr_rx_cal_busy(xcvr_rx_cal_busy[2]), + .xcvr_tx_serial_clk(xcvr_tx_serial_clk), + .xcvr_rx_cdr_refclk(xcvr_ref_clk), + .xcvr_tx_serial_data(xcvr_tx_serial_data[2]), + .xcvr_rx_serial_data(xcvr_rx_serial_data[2]), + .xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[2]), + .xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[2]), + .xcvr_tx_ready(xcvr_tx_ready[2]), + .xcvr_rx_ready(xcvr_rx_ready[2]), + + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber) +); + +eth_xcvr_phy_wrapper eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + .xcvr_tx_analogreset(xcvr_tx_analogreset[3]), + .xcvr_rx_analogreset(xcvr_rx_analogreset[3]), + .xcvr_tx_digitalreset(xcvr_tx_digitalreset[3]), + .xcvr_rx_digitalreset(xcvr_rx_digitalreset[3]), + .xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[3]), + .xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[3]), + .xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[3]), + .xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[3]), + .xcvr_tx_cal_busy(xcvr_tx_cal_busy[3]), + .xcvr_rx_cal_busy(xcvr_rx_cal_busy[3]), + .xcvr_tx_serial_clk(xcvr_tx_serial_clk), + .xcvr_rx_cdr_refclk(xcvr_ref_clk), + .xcvr_tx_serial_data(xcvr_tx_serial_data[3]), + .xcvr_rx_serial_data(xcvr_rx_serial_data[3]), + .xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[3]), + .xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[3]), + .xcvr_tx_ready(xcvr_tx_ready[3]), + .xcvr_rx_ready(xcvr_rx_ready[3]), + + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber) +); + +endmodule + +`resetall diff --git a/example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_wrapper.v new file mode 100644 index 000000000..c79772fd8 --- /dev/null +++ b/example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -0,0 +1,167 @@ +/* + +Copyright (c) 2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY wrapper + */ +module eth_xcvr_phy_wrapper ( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + input wire xcvr_tx_analogreset, + input wire xcvr_rx_analogreset, + input wire xcvr_tx_digitalreset, + input wire xcvr_rx_digitalreset, + output wire xcvr_tx_analogreset_stat, + output wire xcvr_rx_analogreset_stat, + output wire xcvr_tx_digitalreset_stat, + output wire xcvr_rx_digitalreset_stat, + output wire xcvr_tx_cal_busy, + output wire xcvr_rx_cal_busy, + input wire xcvr_tx_serial_clk, + input wire xcvr_rx_cdr_refclk, + output wire xcvr_tx_serial_data, + input wire xcvr_rx_serial_data, + output wire xcvr_rx_is_lockedtoref, + output wire xcvr_rx_is_lockedtodata, + input wire xcvr_tx_ready, + input wire xcvr_rx_ready, + + output wire phy_tx_clk, + output wire phy_tx_rst, + input wire [63:0] phy_xgmii_txd, + input wire [7:0] phy_xgmii_txc, + output wire phy_rx_clk, + output wire phy_rx_rst, + output wire [63:0] phy_xgmii_rxd, + output wire [7:0] phy_xgmii_rxc, + output wire phy_rx_block_lock, + output wire phy_rx_high_ber +); + +wire xcvr_tx_clk; +wire xcvr_rx_clk; + +assign phy_tx_clk = xcvr_tx_clk; +assign phy_rx_clk = xcvr_rx_clk; + +wire [1:0] xcvr_tx_hdr; +wire [63:0] xcvr_tx_data; +wire [1:0] xcvr_rx_hdr; +wire [63:0] xcvr_rx_data; + +wire [1:0] phy_tx_hdr; +wire [63:0] phy_tx_data; +wire [1:0] phy_rx_hdr; +wire [63:0] phy_rx_data; + +wire xcvr_rx_bitslip; + +assign {xcvr_tx_hdr, xcvr_tx_data} = {phy_tx_data, phy_tx_hdr}; +assign {phy_rx_data, phy_rx_hdr} = {xcvr_rx_hdr, xcvr_rx_data}; + +eth_xcvr eth_xcvr_inst ( + .tx_analogreset (xcvr_tx_analogreset), + .rx_analogreset (xcvr_rx_analogreset), + .tx_digitalreset (xcvr_tx_digitalreset), + .rx_digitalreset (xcvr_rx_digitalreset), + .tx_analogreset_stat (xcvr_tx_analogreset_stat), + .rx_analogreset_stat (xcvr_rx_analogreset_stat), + .tx_digitalreset_stat (xcvr_tx_digitalreset_stat), + .rx_digitalreset_stat (xcvr_rx_digitalreset_stat), + .tx_cal_busy (xcvr_tx_cal_busy), + .rx_cal_busy (xcvr_rx_cal_busy), + .tx_serial_clk0 (xcvr_tx_serial_clk), + .rx_cdr_refclk0 (xcvr_rx_cdr_refclk), + .tx_serial_data (xcvr_tx_serial_data), + .rx_serial_data (xcvr_rx_serial_data), + .rx_is_lockedtoref (xcvr_rx_is_lockedtoref), + .rx_is_lockedtodata (xcvr_rx_is_lockedtodata), + .tx_coreclkin (xcvr_tx_clk), + .rx_coreclkin (xcvr_rx_clk), + .tx_clkout (xcvr_tx_clk), + .tx_clkout2 (), + .rx_clkout (xcvr_rx_clk), + .rx_clkout2 (), + .tx_parallel_data (xcvr_tx_data), + .tx_control (xcvr_tx_hdr), + .tx_enh_data_valid (1'b1), + .unused_tx_parallel_data (13'd0), + .rx_parallel_data (xcvr_rx_data), + .rx_control (xcvr_rx_hdr), + .rx_enh_data_valid (), + .unused_rx_parallel_data (), + .rx_bitslip (xcvr_rx_bitslip) +); + +sync_reset #( + .N(4) +) +phy_tx_rst_reset_sync_inst ( + .clk(phy_tx_clk), + .rst(~xcvr_tx_ready), + .out(phy_tx_rst) +); + +sync_reset #( + .N(4) +) +phy_rx_rst_reset_sync_inst ( + .clk(phy_rx_clk), + .rst(~xcvr_rx_ready), + .out(phy_rx_rst) +); + +eth_phy_10g #( + .BIT_REVERSE(0), + .BITSLIP_HIGH_CYCLES(32), + .BITSLIP_LOW_CYCLES(32) +) +phy_inst ( + .tx_clk(phy_tx_clk), + .tx_rst(phy_tx_rst), + .rx_clk(phy_rx_clk), + .rx_rst(phy_rx_rst), + .xgmii_txd(phy_xgmii_txd), + .xgmii_txc(phy_xgmii_txc), + .xgmii_rxd(phy_xgmii_rxd), + .xgmii_rxc(phy_xgmii_rxc), + .serdes_tx_data(phy_tx_data), + .serdes_tx_hdr(phy_tx_hdr), + .serdes_rx_data(phy_rx_data), + .serdes_rx_hdr(phy_rx_hdr), + .serdes_rx_bitslip(xcvr_rx_bitslip), + .rx_block_lock(phy_rx_block_lock), + .rx_high_ber(phy_rx_high_ber) +); + +endmodule + +`resetall diff --git a/example/520N_MX/fpga_10g/rtl/fpga.v b/example/520N_MX/fpga_10g/rtl/fpga.v new file mode 100644 index 000000000..247819308 --- /dev/null +++ b/example/520N_MX/fpga_10g/rtl/fpga.v @@ -0,0 +1,602 @@ +/* + +Copyright (c) 2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga ( + /* + * Clock: 300 MHz + */ + input wire usr_refclk0, + + /* + * GPIO + */ + output wire [1:0] led_user_grn, + output wire [1:0] led_user_red, + output wire [3:0] led_qsfp, + + /* + * Ethernet: QSFP28 + */ + output wire [3:0] qsfp0_tx, + input wire [3:0] qsfp0_rx, + input wire qsfp0_refclk, + + output wire [3:0] qsfp1_tx, + input wire [3:0] qsfp1_rx, + input wire qsfp1_refclk, + + output wire [3:0] qsfp2_tx, + input wire [3:0] qsfp2_rx, + input wire qsfp2_refclk, + + output wire [3:0] qsfp3_tx, + input wire [3:0] qsfp3_rx, + input wire qsfp3_refclk, + + input wire [3:0] qsfp_irq_n +); + +// Clock and reset +wire ninit_done; + +reset_release reset_release_inst ( + .ninit_done (ninit_done) +); + +wire clk_300mhz = usr_refclk0; +wire rst_300mhz; + +sync_reset #( + .N(4) +) +sync_reset_300mhz_inst ( + .clk(clk_300mhz), + .rst(ninit_done), + .out(rst_300mhz) +); + +wire clk_156mhz_int; +wire rst_156mhz_int; + +// XGMII 10G PHY + +// QSFP0 +wire qsfp0_tx_clk_1_int; +wire qsfp0_tx_rst_1_int; +wire [63:0] qsfp0_txd_1_int; +wire [7:0] qsfp0_txc_1_int; +wire qsfp0_rx_clk_1_int; +wire qsfp0_rx_rst_1_int; +wire [63:0] qsfp0_rxd_1_int; +wire [7:0] qsfp0_rxc_1_int; +wire qsfp0_tx_clk_2_int; +wire qsfp0_tx_rst_2_int; +wire [63:0] qsfp0_txd_2_int; +wire [7:0] qsfp0_txc_2_int; +wire qsfp0_rx_clk_2_int; +wire qsfp0_rx_rst_2_int; +wire [63:0] qsfp0_rxd_2_int; +wire [7:0] qsfp0_rxc_2_int; +wire qsfp0_tx_clk_3_int; +wire qsfp0_tx_rst_3_int; +wire [63:0] qsfp0_txd_3_int; +wire [7:0] qsfp0_txc_3_int; +wire qsfp0_rx_clk_3_int; +wire qsfp0_rx_rst_3_int; +wire [63:0] qsfp0_rxd_3_int; +wire [7:0] qsfp0_rxc_3_int; +wire qsfp0_tx_clk_4_int; +wire qsfp0_tx_rst_4_int; +wire [63:0] qsfp0_txd_4_int; +wire [7:0] qsfp0_txc_4_int; +wire qsfp0_rx_clk_4_int; +wire qsfp0_rx_rst_4_int; +wire [63:0] qsfp0_rxd_4_int; +wire [7:0] qsfp0_rxc_4_int; + +assign clk_156mhz_int = qsfp0_tx_clk_1_int; +assign rst_156mhz_int = qsfp0_tx_rst_1_int; + +wire qsfp0_rx_block_lock_1; +wire qsfp0_rx_block_lock_2; +wire qsfp0_rx_block_lock_3; +wire qsfp0_rx_block_lock_4; + +eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad ( + .xcvr_ctrl_clk(clk_300mhz), + .xcvr_ctrl_rst(rst_300mhz), + .xcvr_ref_clk(qsfp0_refclk), + .xcvr_tx_serial_data(qsfp0_tx), + .xcvr_rx_serial_data(qsfp0_rx), + + .phy_1_tx_clk(qsfp0_tx_clk_1_int), + .phy_1_tx_rst(qsfp0_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp0_txd_1_int), + .phy_1_xgmii_txc(qsfp0_txc_1_int), + .phy_1_rx_clk(qsfp0_rx_clk_1_int), + .phy_1_rx_rst(qsfp0_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp0_rxd_1_int), + .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_2_tx_clk(qsfp0_tx_clk_2_int), + .phy_2_tx_rst(qsfp0_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp0_txd_2_int), + .phy_2_xgmii_txc(qsfp0_txc_2_int), + .phy_2_rx_clk(qsfp0_rx_clk_2_int), + .phy_2_rx_rst(qsfp0_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp0_rxd_2_int), + .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_3_tx_clk(qsfp0_tx_clk_3_int), + .phy_3_tx_rst(qsfp0_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp0_txd_3_int), + .phy_3_xgmii_txc(qsfp0_txc_3_int), + .phy_3_rx_clk(qsfp0_rx_clk_3_int), + .phy_3_rx_rst(qsfp0_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp0_rxd_3_int), + .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_4_tx_clk(qsfp0_tx_clk_4_int), + .phy_4_tx_rst(qsfp0_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp0_txd_4_int), + .phy_4_xgmii_txc(qsfp0_txc_4_int), + .phy_4_rx_clk(qsfp0_rx_clk_4_int), + .phy_4_rx_rst(qsfp0_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp0_rxd_4_int), + .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_high_ber() +); + +// QSFP1 +wire qsfp1_tx_clk_1_int; +wire qsfp1_tx_rst_1_int; +wire [63:0] qsfp1_txd_1_int; +wire [7:0] qsfp1_txc_1_int; +wire qsfp1_rx_clk_1_int; +wire qsfp1_rx_rst_1_int; +wire [63:0] qsfp1_rxd_1_int; +wire [7:0] qsfp1_rxc_1_int; +wire qsfp1_tx_clk_2_int; +wire qsfp1_tx_rst_2_int; +wire [63:0] qsfp1_txd_2_int; +wire [7:0] qsfp1_txc_2_int; +wire qsfp1_rx_clk_2_int; +wire qsfp1_rx_rst_2_int; +wire [63:0] qsfp1_rxd_2_int; +wire [7:0] qsfp1_rxc_2_int; +wire qsfp1_tx_clk_3_int; +wire qsfp1_tx_rst_3_int; +wire [63:0] qsfp1_txd_3_int; +wire [7:0] qsfp1_txc_3_int; +wire qsfp1_rx_clk_3_int; +wire qsfp1_rx_rst_3_int; +wire [63:0] qsfp1_rxd_3_int; +wire [7:0] qsfp1_rxc_3_int; +wire qsfp1_tx_clk_4_int; +wire qsfp1_tx_rst_4_int; +wire [63:0] qsfp1_txd_4_int; +wire [7:0] qsfp1_txc_4_int; +wire qsfp1_rx_clk_4_int; +wire qsfp1_rx_rst_4_int; +wire [63:0] qsfp1_rxd_4_int; +wire [7:0] qsfp1_rxc_4_int; + +wire qsfp1_rx_block_lock_1; +wire qsfp1_rx_block_lock_2; +wire qsfp1_rx_block_lock_3; +wire qsfp1_rx_block_lock_4; + +eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad ( + .xcvr_ctrl_clk(clk_300mhz), + .xcvr_ctrl_rst(rst_300mhz), + .xcvr_ref_clk(qsfp1_refclk), + .xcvr_tx_serial_data(qsfp1_tx), + .xcvr_rx_serial_data(qsfp1_rx), + + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_high_ber() +); + +// QSFP2 +wire qsfp2_tx_clk_1_int; +wire qsfp2_tx_rst_1_int; +wire [63:0] qsfp2_txd_1_int; +wire [7:0] qsfp2_txc_1_int; +wire qsfp2_rx_clk_1_int; +wire qsfp2_rx_rst_1_int; +wire [63:0] qsfp2_rxd_1_int; +wire [7:0] qsfp2_rxc_1_int; +wire qsfp2_tx_clk_2_int; +wire qsfp2_tx_rst_2_int; +wire [63:0] qsfp2_txd_2_int; +wire [7:0] qsfp2_txc_2_int; +wire qsfp2_rx_clk_2_int; +wire qsfp2_rx_rst_2_int; +wire [63:0] qsfp2_rxd_2_int; +wire [7:0] qsfp2_rxc_2_int; +wire qsfp2_tx_clk_3_int; +wire qsfp2_tx_rst_3_int; +wire [63:0] qsfp2_txd_3_int; +wire [7:0] qsfp2_txc_3_int; +wire qsfp2_rx_clk_3_int; +wire qsfp2_rx_rst_3_int; +wire [63:0] qsfp2_rxd_3_int; +wire [7:0] qsfp2_rxc_3_int; +wire qsfp2_tx_clk_4_int; +wire qsfp2_tx_rst_4_int; +wire [63:0] qsfp2_txd_4_int; +wire [7:0] qsfp2_txc_4_int; +wire qsfp2_rx_clk_4_int; +wire qsfp2_rx_rst_4_int; +wire [63:0] qsfp2_rxd_4_int; +wire [7:0] qsfp2_rxc_4_int; + +wire qsfp2_rx_block_lock_1; +wire qsfp2_rx_block_lock_2; +wire qsfp2_rx_block_lock_3; +wire qsfp2_rx_block_lock_4; + +eth_xcvr_phy_quad_wrapper qsfp2_eth_xcvr_phy_quad ( + .xcvr_ctrl_clk(clk_300mhz), + .xcvr_ctrl_rst(rst_300mhz), + .xcvr_ref_clk(qsfp2_refclk), + .xcvr_tx_serial_data(qsfp2_tx), + .xcvr_rx_serial_data(qsfp2_rx), + + .phy_1_tx_clk(qsfp2_tx_clk_1_int), + .phy_1_tx_rst(qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp2_txd_1_int), + .phy_1_xgmii_txc(qsfp2_txc_1_int), + .phy_1_rx_clk(qsfp2_rx_clk_1_int), + .phy_1_rx_rst(qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp2_rxc_1_int), + .phy_1_rx_block_lock(qsfp2_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_2_tx_clk(qsfp2_tx_clk_2_int), + .phy_2_tx_rst(qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp2_txd_2_int), + .phy_2_xgmii_txc(qsfp2_txc_2_int), + .phy_2_rx_clk(qsfp2_rx_clk_2_int), + .phy_2_rx_rst(qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp2_rxc_2_int), + .phy_2_rx_block_lock(qsfp2_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_3_tx_clk(qsfp2_tx_clk_3_int), + .phy_3_tx_rst(qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp2_txd_3_int), + .phy_3_xgmii_txc(qsfp2_txc_3_int), + .phy_3_rx_clk(qsfp2_rx_clk_3_int), + .phy_3_rx_rst(qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp2_rxc_3_int), + .phy_3_rx_block_lock(qsfp2_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_4_tx_clk(qsfp2_tx_clk_4_int), + .phy_4_tx_rst(qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp2_txd_4_int), + .phy_4_xgmii_txc(qsfp2_txc_4_int), + .phy_4_rx_clk(qsfp2_rx_clk_4_int), + .phy_4_rx_rst(qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp2_rxc_4_int), + .phy_4_rx_block_lock(qsfp2_rx_block_lock_4), + .phy_4_rx_high_ber() +); + +// QSFP3 +wire qsfp3_tx_clk_1_int; +wire qsfp3_tx_rst_1_int; +wire [63:0] qsfp3_txd_1_int; +wire [7:0] qsfp3_txc_1_int; +wire qsfp3_rx_clk_1_int; +wire qsfp3_rx_rst_1_int; +wire [63:0] qsfp3_rxd_1_int; +wire [7:0] qsfp3_rxc_1_int; +wire qsfp3_tx_clk_2_int; +wire qsfp3_tx_rst_2_int; +wire [63:0] qsfp3_txd_2_int; +wire [7:0] qsfp3_txc_2_int; +wire qsfp3_rx_clk_2_int; +wire qsfp3_rx_rst_2_int; +wire [63:0] qsfp3_rxd_2_int; +wire [7:0] qsfp3_rxc_2_int; +wire qsfp3_tx_clk_3_int; +wire qsfp3_tx_rst_3_int; +wire [63:0] qsfp3_txd_3_int; +wire [7:0] qsfp3_txc_3_int; +wire qsfp3_rx_clk_3_int; +wire qsfp3_rx_rst_3_int; +wire [63:0] qsfp3_rxd_3_int; +wire [7:0] qsfp3_rxc_3_int; +wire qsfp3_tx_clk_4_int; +wire qsfp3_tx_rst_4_int; +wire [63:0] qsfp3_txd_4_int; +wire [7:0] qsfp3_txc_4_int; +wire qsfp3_rx_clk_4_int; +wire qsfp3_rx_rst_4_int; +wire [63:0] qsfp3_rxd_4_int; +wire [7:0] qsfp3_rxc_4_int; + +wire qsfp3_rx_block_lock_1; +wire qsfp3_rx_block_lock_2; +wire qsfp3_rx_block_lock_3; +wire qsfp3_rx_block_lock_4; + +eth_xcvr_phy_quad_wrapper qsfp3_eth_xcvr_phy_quad ( + .xcvr_ctrl_clk(clk_300mhz), + .xcvr_ctrl_rst(rst_300mhz), + .xcvr_ref_clk(qsfp3_refclk), + .xcvr_tx_serial_data(qsfp3_tx), + .xcvr_rx_serial_data(qsfp3_rx), + + .phy_1_tx_clk(qsfp3_tx_clk_1_int), + .phy_1_tx_rst(qsfp3_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp3_txd_1_int), + .phy_1_xgmii_txc(qsfp3_txc_1_int), + .phy_1_rx_clk(qsfp3_rx_clk_1_int), + .phy_1_rx_rst(qsfp3_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp3_rxd_1_int), + .phy_1_xgmii_rxc(qsfp3_rxc_1_int), + .phy_1_rx_block_lock(qsfp3_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_2_tx_clk(qsfp3_tx_clk_2_int), + .phy_2_tx_rst(qsfp3_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp3_txd_2_int), + .phy_2_xgmii_txc(qsfp3_txc_2_int), + .phy_2_rx_clk(qsfp3_rx_clk_2_int), + .phy_2_rx_rst(qsfp3_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp3_rxd_2_int), + .phy_2_xgmii_rxc(qsfp3_rxc_2_int), + .phy_2_rx_block_lock(qsfp3_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_3_tx_clk(qsfp3_tx_clk_3_int), + .phy_3_tx_rst(qsfp3_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp3_txd_3_int), + .phy_3_xgmii_txc(qsfp3_txc_3_int), + .phy_3_rx_clk(qsfp3_rx_clk_3_int), + .phy_3_rx_rst(qsfp3_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp3_rxd_3_int), + .phy_3_xgmii_rxc(qsfp3_rxc_3_int), + .phy_3_rx_block_lock(qsfp3_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_4_tx_clk(qsfp3_tx_clk_4_int), + .phy_4_tx_rst(qsfp3_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp3_txd_4_int), + .phy_4_xgmii_txc(qsfp3_txc_4_int), + .phy_4_rx_clk(qsfp3_rx_clk_4_int), + .phy_4_rx_rst(qsfp3_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp3_rxd_4_int), + .phy_4_xgmii_rxc(qsfp3_rxc_4_int), + .phy_4_rx_block_lock(qsfp3_rx_block_lock_4), + .phy_4_rx_high_ber() +); + +assign led_qsfp[0] = qsfp0_rx_block_lock_1; +assign led_qsfp[1] = qsfp1_rx_block_lock_1; +assign led_qsfp[2] = qsfp2_rx_block_lock_1; +assign led_qsfp[3] = qsfp3_rx_block_lock_1; + +fpga_core +core_inst ( + /* + * Clock: 156.25 MHz + * Synchronous reset + */ + .clk(clk_156mhz_int), + .rst(rst_156mhz_int), + /* + * GPIO + */ + .led_user_grn(led_user_grn), + .led_user_red(led_user_red), + // .led_qsfp(led_qsfp), + /* + * Ethernet: QSFP28 + */ + .qsfp0_tx_clk_1(qsfp0_tx_clk_1_int), + .qsfp0_tx_rst_1(qsfp0_tx_rst_1_int), + .qsfp0_txd_1(qsfp0_txd_1_int), + .qsfp0_txc_1(qsfp0_txc_1_int), + .qsfp0_rx_clk_1(qsfp0_rx_clk_1_int), + .qsfp0_rx_rst_1(qsfp0_rx_rst_1_int), + .qsfp0_rxd_1(qsfp0_rxd_1_int), + .qsfp0_rxc_1(qsfp0_rxc_1_int), + .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int), + .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int), + .qsfp0_txd_2(qsfp0_txd_2_int), + .qsfp0_txc_2(qsfp0_txc_2_int), + .qsfp0_rx_clk_2(qsfp0_rx_clk_2_int), + .qsfp0_rx_rst_2(qsfp0_rx_rst_2_int), + .qsfp0_rxd_2(qsfp0_rxd_2_int), + .qsfp0_rxc_2(qsfp0_rxc_2_int), + .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int), + .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int), + .qsfp0_txd_3(qsfp0_txd_3_int), + .qsfp0_txc_3(qsfp0_txc_3_int), + .qsfp0_rx_clk_3(qsfp0_rx_clk_3_int), + .qsfp0_rx_rst_3(qsfp0_rx_rst_3_int), + .qsfp0_rxd_3(qsfp0_rxd_3_int), + .qsfp0_rxc_3(qsfp0_rxc_3_int), + .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int), + .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int), + .qsfp0_txd_4(qsfp0_txd_4_int), + .qsfp0_txc_4(qsfp0_txc_4_int), + .qsfp0_rx_clk_4(qsfp0_rx_clk_4_int), + .qsfp0_rx_rst_4(qsfp0_rx_rst_4_int), + .qsfp0_rxd_4(qsfp0_rxd_4_int), + .qsfp0_rxc_4(qsfp0_rxc_4_int), + .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), + .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), + .qsfp1_txd_1(qsfp1_txd_1_int), + .qsfp1_txc_1(qsfp1_txc_1_int), + .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), + .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), + .qsfp1_rxd_1(qsfp1_rxd_1_int), + .qsfp1_rxc_1(qsfp1_rxc_1_int), + .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), + .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), + .qsfp1_txd_2(qsfp1_txd_2_int), + .qsfp1_txc_2(qsfp1_txc_2_int), + .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), + .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), + .qsfp1_rxd_2(qsfp1_rxd_2_int), + .qsfp1_rxc_2(qsfp1_rxc_2_int), + .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), + .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), + .qsfp1_txd_3(qsfp1_txd_3_int), + .qsfp1_txc_3(qsfp1_txc_3_int), + .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), + .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), + .qsfp1_rxd_3(qsfp1_rxd_3_int), + .qsfp1_rxc_3(qsfp1_rxc_3_int), + .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), + .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), + .qsfp1_txd_4(qsfp1_txd_4_int), + .qsfp1_txc_4(qsfp1_txc_4_int), + .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), + .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), + .qsfp1_rxd_4(qsfp1_rxd_4_int), + .qsfp1_rxc_4(qsfp1_rxc_4_int), + .qsfp2_tx_clk_1(qsfp2_tx_clk_1_int), + .qsfp2_tx_rst_1(qsfp2_tx_rst_1_int), + .qsfp2_txd_1(qsfp2_txd_1_int), + .qsfp2_txc_1(qsfp2_txc_1_int), + .qsfp2_rx_clk_1(qsfp2_rx_clk_1_int), + .qsfp2_rx_rst_1(qsfp2_rx_rst_1_int), + .qsfp2_rxd_1(qsfp2_rxd_1_int), + .qsfp2_rxc_1(qsfp2_rxc_1_int), + .qsfp2_tx_clk_2(qsfp2_tx_clk_2_int), + .qsfp2_tx_rst_2(qsfp2_tx_rst_2_int), + .qsfp2_txd_2(qsfp2_txd_2_int), + .qsfp2_txc_2(qsfp2_txc_2_int), + .qsfp2_rx_clk_2(qsfp2_rx_clk_2_int), + .qsfp2_rx_rst_2(qsfp2_rx_rst_2_int), + .qsfp2_rxd_2(qsfp2_rxd_2_int), + .qsfp2_rxc_2(qsfp2_rxc_2_int), + .qsfp2_tx_clk_3(qsfp2_tx_clk_3_int), + .qsfp2_tx_rst_3(qsfp2_tx_rst_3_int), + .qsfp2_txd_3(qsfp2_txd_3_int), + .qsfp2_txc_3(qsfp2_txc_3_int), + .qsfp2_rx_clk_3(qsfp2_rx_clk_3_int), + .qsfp2_rx_rst_3(qsfp2_rx_rst_3_int), + .qsfp2_rxd_3(qsfp2_rxd_3_int), + .qsfp2_rxc_3(qsfp2_rxc_3_int), + .qsfp2_tx_clk_4(qsfp2_tx_clk_4_int), + .qsfp2_tx_rst_4(qsfp2_tx_rst_4_int), + .qsfp2_txd_4(qsfp2_txd_4_int), + .qsfp2_txc_4(qsfp2_txc_4_int), + .qsfp2_rx_clk_4(qsfp2_rx_clk_4_int), + .qsfp2_rx_rst_4(qsfp2_rx_rst_4_int), + .qsfp2_rxd_4(qsfp2_rxd_4_int), + .qsfp2_rxc_4(qsfp2_rxc_4_int), + .qsfp3_tx_clk_1(qsfp3_tx_clk_1_int), + .qsfp3_tx_rst_1(qsfp3_tx_rst_1_int), + .qsfp3_txd_1(qsfp3_txd_1_int), + .qsfp3_txc_1(qsfp3_txc_1_int), + .qsfp3_rx_clk_1(qsfp3_rx_clk_1_int), + .qsfp3_rx_rst_1(qsfp3_rx_rst_1_int), + .qsfp3_rxd_1(qsfp3_rxd_1_int), + .qsfp3_rxc_1(qsfp3_rxc_1_int), + .qsfp3_tx_clk_2(qsfp3_tx_clk_2_int), + .qsfp3_tx_rst_2(qsfp3_tx_rst_2_int), + .qsfp3_txd_2(qsfp3_txd_2_int), + .qsfp3_txc_2(qsfp3_txc_2_int), + .qsfp3_rx_clk_2(qsfp3_rx_clk_2_int), + .qsfp3_rx_rst_2(qsfp3_rx_rst_2_int), + .qsfp3_rxd_2(qsfp3_rxd_2_int), + .qsfp3_rxc_2(qsfp3_rxc_2_int), + .qsfp3_tx_clk_3(qsfp3_tx_clk_3_int), + .qsfp3_tx_rst_3(qsfp3_tx_rst_3_int), + .qsfp3_txd_3(qsfp3_txd_3_int), + .qsfp3_txc_3(qsfp3_txc_3_int), + .qsfp3_rx_clk_3(qsfp3_rx_clk_3_int), + .qsfp3_rx_rst_3(qsfp3_rx_rst_3_int), + .qsfp3_rxd_3(qsfp3_rxd_3_int), + .qsfp3_rxc_3(qsfp3_rxc_3_int), + .qsfp3_tx_clk_4(qsfp3_tx_clk_4_int), + .qsfp3_tx_rst_4(qsfp3_tx_rst_4_int), + .qsfp3_txd_4(qsfp3_txd_4_int), + .qsfp3_txc_4(qsfp3_txc_4_int), + .qsfp3_rx_clk_4(qsfp3_rx_clk_4_int), + .qsfp3_rx_rst_4(qsfp3_rx_rst_4_int), + .qsfp3_rxd_4(qsfp3_rxd_4_int), + .qsfp3_rxc_4(qsfp3_rxc_4_int) +); + +endmodule + +`resetall diff --git a/example/520N_MX/fpga_10g/rtl/fpga_core.v b/example/520N_MX/fpga_10g/rtl/fpga_core.v new file mode 100644 index 000000000..edaf3e722 --- /dev/null +++ b/example/520N_MX/fpga_10g/rtl/fpga_core.v @@ -0,0 +1,743 @@ +/* + +Copyright (c) 2014-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core +( + /* + * Clock: 156.25MHz + * Synchronous reset + */ + input wire clk, + input wire rst, + + /* + * GPIO + */ + output wire [1:0] led_user_grn, + output wire [1:0] led_user_red, + output wire [3:0] led_qsfp, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp0_tx_clk_1, + input wire qsfp0_tx_rst_1, + output wire [63:0] qsfp0_txd_1, + output wire [7:0] qsfp0_txc_1, + input wire qsfp0_rx_clk_1, + input wire qsfp0_rx_rst_1, + input wire [63:0] qsfp0_rxd_1, + input wire [7:0] qsfp0_rxc_1, + input wire qsfp0_tx_clk_2, + input wire qsfp0_tx_rst_2, + output wire [63:0] qsfp0_txd_2, + output wire [7:0] qsfp0_txc_2, + input wire qsfp0_rx_clk_2, + input wire qsfp0_rx_rst_2, + input wire [63:0] qsfp0_rxd_2, + input wire [7:0] qsfp0_rxc_2, + input wire qsfp0_tx_clk_3, + input wire qsfp0_tx_rst_3, + output wire [63:0] qsfp0_txd_3, + output wire [7:0] qsfp0_txc_3, + input wire qsfp0_rx_clk_3, + input wire qsfp0_rx_rst_3, + input wire [63:0] qsfp0_rxd_3, + input wire [7:0] qsfp0_rxc_3, + input wire qsfp0_tx_clk_4, + input wire qsfp0_tx_rst_4, + output wire [63:0] qsfp0_txd_4, + output wire [7:0] qsfp0_txc_4, + input wire qsfp0_rx_clk_4, + input wire qsfp0_rx_rst_4, + input wire [63:0] qsfp0_rxd_4, + input wire [7:0] qsfp0_rxc_4, + input wire qsfp1_tx_clk_1, + input wire qsfp1_tx_rst_1, + output wire [63:0] qsfp1_txd_1, + output wire [7:0] qsfp1_txc_1, + input wire qsfp1_rx_clk_1, + input wire qsfp1_rx_rst_1, + input wire [63:0] qsfp1_rxd_1, + input wire [7:0] qsfp1_rxc_1, + input wire qsfp1_tx_clk_2, + input wire qsfp1_tx_rst_2, + output wire [63:0] qsfp1_txd_2, + output wire [7:0] qsfp1_txc_2, + input wire qsfp1_rx_clk_2, + input wire qsfp1_rx_rst_2, + input wire [63:0] qsfp1_rxd_2, + input wire [7:0] qsfp1_rxc_2, + input wire qsfp1_tx_clk_3, + input wire qsfp1_tx_rst_3, + output wire [63:0] qsfp1_txd_3, + output wire [7:0] qsfp1_txc_3, + input wire qsfp1_rx_clk_3, + input wire qsfp1_rx_rst_3, + input wire [63:0] qsfp1_rxd_3, + input wire [7:0] qsfp1_rxc_3, + input wire qsfp1_tx_clk_4, + input wire qsfp1_tx_rst_4, + output wire [63:0] qsfp1_txd_4, + output wire [7:0] qsfp1_txc_4, + input wire qsfp1_rx_clk_4, + input wire qsfp1_rx_rst_4, + input wire [63:0] qsfp1_rxd_4, + input wire [7:0] qsfp1_rxc_4, + input wire qsfp2_tx_clk_1, + input wire qsfp2_tx_rst_1, + output wire [63:0] qsfp2_txd_1, + output wire [7:0] qsfp2_txc_1, + input wire qsfp2_rx_clk_1, + input wire qsfp2_rx_rst_1, + input wire [63:0] qsfp2_rxd_1, + input wire [7:0] qsfp2_rxc_1, + input wire qsfp2_tx_clk_2, + input wire qsfp2_tx_rst_2, + output wire [63:0] qsfp2_txd_2, + output wire [7:0] qsfp2_txc_2, + input wire qsfp2_rx_clk_2, + input wire qsfp2_rx_rst_2, + input wire [63:0] qsfp2_rxd_2, + input wire [7:0] qsfp2_rxc_2, + input wire qsfp2_tx_clk_3, + input wire qsfp2_tx_rst_3, + output wire [63:0] qsfp2_txd_3, + output wire [7:0] qsfp2_txc_3, + input wire qsfp2_rx_clk_3, + input wire qsfp2_rx_rst_3, + input wire [63:0] qsfp2_rxd_3, + input wire [7:0] qsfp2_rxc_3, + input wire qsfp2_tx_clk_4, + input wire qsfp2_tx_rst_4, + output wire [63:0] qsfp2_txd_4, + output wire [7:0] qsfp2_txc_4, + input wire qsfp2_rx_clk_4, + input wire qsfp2_rx_rst_4, + input wire [63:0] qsfp2_rxd_4, + input wire [7:0] qsfp2_rxc_4, + input wire qsfp3_tx_clk_1, + input wire qsfp3_tx_rst_1, + output wire [63:0] qsfp3_txd_1, + output wire [7:0] qsfp3_txc_1, + input wire qsfp3_rx_clk_1, + input wire qsfp3_rx_rst_1, + input wire [63:0] qsfp3_rxd_1, + input wire [7:0] qsfp3_rxc_1, + input wire qsfp3_tx_clk_2, + input wire qsfp3_tx_rst_2, + output wire [63:0] qsfp3_txd_2, + output wire [7:0] qsfp3_txc_2, + input wire qsfp3_rx_clk_2, + input wire qsfp3_rx_rst_2, + input wire [63:0] qsfp3_rxd_2, + input wire [7:0] qsfp3_rxc_2, + input wire qsfp3_tx_clk_3, + input wire qsfp3_tx_rst_3, + output wire [63:0] qsfp3_txd_3, + output wire [7:0] qsfp3_txc_3, + input wire qsfp3_rx_clk_3, + input wire qsfp3_rx_rst_3, + input wire [63:0] qsfp3_rxd_3, + input wire [7:0] qsfp3_rxc_3, + input wire qsfp3_tx_clk_4, + input wire qsfp3_tx_rst_4, + output wire [63:0] qsfp3_txd_4, + output wire [7:0] qsfp3_txc_4, + input wire qsfp3_rx_clk_4, + input wire qsfp3_rx_rst_4, + input wire [63:0] qsfp3_rxd_4, + input wire [7:0] qsfp3_rxc_4 +); + +// AXI between MAC and Ethernet modules +wire [63:0] rx_axis_tdata; +wire [7:0] rx_axis_tkeep; +wire rx_axis_tvalid; +wire rx_axis_tready; +wire rx_axis_tlast; +wire rx_axis_tuser; + +wire [63:0] tx_axis_tdata; +wire [7:0] tx_axis_tkeep; +wire tx_axis_tvalid; +wire tx_axis_tready; +wire tx_axis_tlast; +wire tx_axis_tuser; + +// Ethernet frame between Ethernet modules and UDP stack +wire rx_eth_hdr_ready; +wire rx_eth_hdr_valid; +wire [47:0] rx_eth_dest_mac; +wire [47:0] rx_eth_src_mac; +wire [15:0] rx_eth_type; +wire [63:0] rx_eth_payload_axis_tdata; +wire [7:0] rx_eth_payload_axis_tkeep; +wire rx_eth_payload_axis_tvalid; +wire rx_eth_payload_axis_tready; +wire rx_eth_payload_axis_tlast; +wire rx_eth_payload_axis_tuser; + +wire tx_eth_hdr_ready; +wire tx_eth_hdr_valid; +wire [47:0] tx_eth_dest_mac; +wire [47:0] tx_eth_src_mac; +wire [15:0] tx_eth_type; +wire [63:0] tx_eth_payload_axis_tdata; +wire [7:0] tx_eth_payload_axis_tkeep; +wire tx_eth_payload_axis_tvalid; +wire tx_eth_payload_axis_tready; +wire tx_eth_payload_axis_tlast; +wire tx_eth_payload_axis_tuser; + +// IP frame connections +wire rx_ip_hdr_valid; +wire rx_ip_hdr_ready; +wire [47:0] rx_ip_eth_dest_mac; +wire [47:0] rx_ip_eth_src_mac; +wire [15:0] rx_ip_eth_type; +wire [3:0] rx_ip_version; +wire [3:0] rx_ip_ihl; +wire [5:0] rx_ip_dscp; +wire [1:0] rx_ip_ecn; +wire [15:0] rx_ip_length; +wire [15:0] rx_ip_identification; +wire [2:0] rx_ip_flags; +wire [12:0] rx_ip_fragment_offset; +wire [7:0] rx_ip_ttl; +wire [7:0] rx_ip_protocol; +wire [15:0] rx_ip_header_checksum; +wire [31:0] rx_ip_source_ip; +wire [31:0] rx_ip_dest_ip; +wire [63:0] rx_ip_payload_axis_tdata; +wire [7:0] rx_ip_payload_axis_tkeep; +wire rx_ip_payload_axis_tvalid; +wire rx_ip_payload_axis_tready; +wire rx_ip_payload_axis_tlast; +wire rx_ip_payload_axis_tuser; + +wire tx_ip_hdr_valid; +wire tx_ip_hdr_ready; +wire [5:0] tx_ip_dscp; +wire [1:0] tx_ip_ecn; +wire [15:0] tx_ip_length; +wire [7:0] tx_ip_ttl; +wire [7:0] tx_ip_protocol; +wire [31:0] tx_ip_source_ip; +wire [31:0] tx_ip_dest_ip; +wire [63:0] tx_ip_payload_axis_tdata; +wire [7:0] tx_ip_payload_axis_tkeep; +wire tx_ip_payload_axis_tvalid; +wire tx_ip_payload_axis_tready; +wire tx_ip_payload_axis_tlast; +wire tx_ip_payload_axis_tuser; + +// UDP frame connections +wire rx_udp_hdr_valid; +wire rx_udp_hdr_ready; +wire [47:0] rx_udp_eth_dest_mac; +wire [47:0] rx_udp_eth_src_mac; +wire [15:0] rx_udp_eth_type; +wire [3:0] rx_udp_ip_version; +wire [3:0] rx_udp_ip_ihl; +wire [5:0] rx_udp_ip_dscp; +wire [1:0] rx_udp_ip_ecn; +wire [15:0] rx_udp_ip_length; +wire [15:0] rx_udp_ip_identification; +wire [2:0] rx_udp_ip_flags; +wire [12:0] rx_udp_ip_fragment_offset; +wire [7:0] rx_udp_ip_ttl; +wire [7:0] rx_udp_ip_protocol; +wire [15:0] rx_udp_ip_header_checksum; +wire [31:0] rx_udp_ip_source_ip; +wire [31:0] rx_udp_ip_dest_ip; +wire [15:0] rx_udp_source_port; +wire [15:0] rx_udp_dest_port; +wire [15:0] rx_udp_length; +wire [15:0] rx_udp_checksum; +wire [63:0] rx_udp_payload_axis_tdata; +wire [7:0] rx_udp_payload_axis_tkeep; +wire rx_udp_payload_axis_tvalid; +wire rx_udp_payload_axis_tready; +wire rx_udp_payload_axis_tlast; +wire rx_udp_payload_axis_tuser; + +wire tx_udp_hdr_valid; +wire tx_udp_hdr_ready; +wire [5:0] tx_udp_ip_dscp; +wire [1:0] tx_udp_ip_ecn; +wire [7:0] tx_udp_ip_ttl; +wire [31:0] tx_udp_ip_source_ip; +wire [31:0] tx_udp_ip_dest_ip; +wire [15:0] tx_udp_source_port; +wire [15:0] tx_udp_dest_port; +wire [15:0] tx_udp_length; +wire [15:0] tx_udp_checksum; +wire [63:0] tx_udp_payload_axis_tdata; +wire [7:0] tx_udp_payload_axis_tkeep; +wire tx_udp_payload_axis_tvalid; +wire tx_udp_payload_axis_tready; +wire tx_udp_payload_axis_tlast; +wire tx_udp_payload_axis_tuser; + +wire [63:0] rx_fifo_udp_payload_axis_tdata; +wire [7:0] rx_fifo_udp_payload_axis_tkeep; +wire rx_fifo_udp_payload_axis_tvalid; +wire rx_fifo_udp_payload_axis_tready; +wire rx_fifo_udp_payload_axis_tlast; +wire rx_fifo_udp_payload_axis_tuser; + +wire [63:0] tx_fifo_udp_payload_axis_tdata; +wire [7:0] tx_fifo_udp_payload_axis_tkeep; +wire tx_fifo_udp_payload_axis_tvalid; +wire tx_fifo_udp_payload_axis_tready; +wire tx_fifo_udp_payload_axis_tlast; +wire tx_fifo_udp_payload_axis_tuser; + +// Configuration +wire [47:0] local_mac = 48'h02_00_00_00_00_00; +wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; +wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; +wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; + +// IP ports not used +assign rx_ip_hdr_ready = 1; +assign rx_ip_payload_axis_tready = 1; + +assign tx_ip_hdr_valid = 0; +assign tx_ip_dscp = 0; +assign tx_ip_ecn = 0; +assign tx_ip_length = 0; +assign tx_ip_ttl = 0; +assign tx_ip_protocol = 0; +assign tx_ip_source_ip = 0; +assign tx_ip_dest_ip = 0; +assign tx_ip_payload_axis_tdata = 0; +assign tx_ip_payload_axis_tkeep = 0; +assign tx_ip_payload_axis_tvalid = 0; +assign tx_ip_payload_axis_tlast = 0; +assign tx_ip_payload_axis_tuser = 0; + +// Loop back UDP +wire match_cond = rx_udp_dest_port == 1234; +wire no_match = !match_cond; + +reg match_cond_reg = 0; +reg no_match_reg = 0; + +always @(posedge clk) begin + if (rst) begin + match_cond_reg <= 0; + no_match_reg <= 0; + end else begin + if (rx_udp_payload_axis_tvalid) begin + if ((!match_cond_reg && !no_match_reg) || + (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin + match_cond_reg <= match_cond; + no_match_reg <= no_match; + end + end else begin + match_cond_reg <= 0; + no_match_reg <= 0; + end + end +end + +assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; +assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; +assign tx_udp_ip_dscp = 0; +assign tx_udp_ip_ecn = 0; +assign tx_udp_ip_ttl = 64; +assign tx_udp_ip_source_ip = local_ip; +assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; +assign tx_udp_source_port = rx_udp_dest_port; +assign tx_udp_dest_port = rx_udp_source_port; +assign tx_udp_length = rx_udp_length; +assign tx_udp_checksum = 0; + +assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; +assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep; +assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; +assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; +assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; +assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; + +assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; +assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep; +assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; +assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; +assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; +assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; + +// Place first payload byte onto LEDs +reg valid_last = 0; +reg [7:0] led_reg = 0; + +always @(posedge clk) begin + if (rst) begin + led_reg <= 0; + end else begin + valid_last <= tx_udp_payload_axis_tvalid; + if (tx_udp_payload_axis_tvalid && !valid_last) begin + led_reg <= tx_udp_payload_axis_tdata; + end + end +end + +assign led_user_grn = led_reg; +assign led_user_red = 0; +assign led_qsfp = 0; + +assign qsfp0_txd_2 = 64'h0707070707070707; +assign qsfp0_txc_2 = 8'hff; +assign qsfp0_txd_3 = 64'h0707070707070707; +assign qsfp0_txc_3 = 8'hff; +assign qsfp0_txd_4 = 64'h0707070707070707; +assign qsfp0_txc_4 = 8'hff; + +assign qsfp1_txd_1 = 64'h0707070707070707; +assign qsfp1_txc_1 = 8'hff; +assign qsfp1_txd_2 = 64'h0707070707070707; +assign qsfp1_txc_2 = 8'hff; +assign qsfp1_txd_3 = 64'h0707070707070707; +assign qsfp1_txc_3 = 8'hff; +assign qsfp1_txd_4 = 64'h0707070707070707; +assign qsfp1_txc_4 = 8'hff; + +assign qsfp2_txd_1 = 64'h0707070707070707; +assign qsfp2_txc_1 = 8'hff; +assign qsfp2_txd_2 = 64'h0707070707070707; +assign qsfp2_txc_2 = 8'hff; +assign qsfp2_txd_3 = 64'h0707070707070707; +assign qsfp2_txc_3 = 8'hff; +assign qsfp2_txd_4 = 64'h0707070707070707; +assign qsfp2_txc_4 = 8'hff; + +assign qsfp3_txd_1 = 64'h0707070707070707; +assign qsfp3_txc_1 = 8'hff; +assign qsfp3_txd_2 = 64'h0707070707070707; +assign qsfp3_txc_2 = 8'hff; +assign qsfp3_txd_3 = 64'h0707070707070707; +assign qsfp3_txc_3 = 8'hff; +assign qsfp3_txd_4 = 64'h0707070707070707; +assign qsfp3_txc_4 = 8'hff; + +eth_mac_10g_fifo #( + .ENABLE_PADDING(1), + .ENABLE_DIC(1), + .MIN_FRAME_LENGTH(64), + .TX_FIFO_DEPTH(4096), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(4096), + .RX_FRAME_FIFO(1) +) +eth_mac_10g_fifo_inst ( + .rx_clk(qsfp0_rx_clk_1), + .rx_rst(qsfp0_rx_rst_1), + .tx_clk(qsfp0_tx_clk_1), + .tx_rst(qsfp0_tx_rst_1), + .logic_clk(clk), + .logic_rst(rst), + + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tuser(tx_axis_tuser), + + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tuser(rx_axis_tuser), + + .xgmii_rxd(qsfp0_rxd_1), + .xgmii_rxc(qsfp0_rxc_1), + .xgmii_txd(qsfp0_txd_1), + .xgmii_txc(qsfp0_txc_1), + + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + .ifg_delay(8'd12) +); + +eth_axis_rx #( + .DATA_WIDTH(64) +) +eth_axis_rx_inst ( + .clk(clk), + .rst(rst), + // AXI input + .s_axis_tdata(rx_axis_tdata), + .s_axis_tkeep(rx_axis_tkeep), + .s_axis_tvalid(rx_axis_tvalid), + .s_axis_tready(rx_axis_tready), + .s_axis_tlast(rx_axis_tlast), + .s_axis_tuser(rx_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(rx_eth_hdr_valid), + .m_eth_hdr_ready(rx_eth_hdr_ready), + .m_eth_dest_mac(rx_eth_dest_mac), + .m_eth_src_mac(rx_eth_src_mac), + .m_eth_type(rx_eth_type), + .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Status signals + .busy(), + .error_header_early_termination() +); + +eth_axis_tx #( + .DATA_WIDTH(64) +) +eth_axis_tx_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(tx_eth_hdr_valid), + .s_eth_hdr_ready(tx_eth_hdr_ready), + .s_eth_dest_mac(tx_eth_dest_mac), + .s_eth_src_mac(tx_eth_src_mac), + .s_eth_type(tx_eth_type), + .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // AXI output + .m_axis_tdata(tx_axis_tdata), + .m_axis_tkeep(tx_axis_tkeep), + .m_axis_tvalid(tx_axis_tvalid), + .m_axis_tready(tx_axis_tready), + .m_axis_tlast(tx_axis_tlast), + .m_axis_tuser(tx_axis_tuser), + // Status signals + .busy() +); + +udp_complete_64 +udp_complete_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(rx_eth_hdr_valid), + .s_eth_hdr_ready(rx_eth_hdr_ready), + .s_eth_dest_mac(rx_eth_dest_mac), + .s_eth_src_mac(rx_eth_src_mac), + .s_eth_type(rx_eth_type), + .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(tx_eth_hdr_valid), + .m_eth_hdr_ready(tx_eth_hdr_ready), + .m_eth_dest_mac(tx_eth_dest_mac), + .m_eth_src_mac(tx_eth_src_mac), + .m_eth_type(tx_eth_type), + .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // IP frame input + .s_ip_hdr_valid(tx_ip_hdr_valid), + .s_ip_hdr_ready(tx_ip_hdr_ready), + .s_ip_dscp(tx_ip_dscp), + .s_ip_ecn(tx_ip_ecn), + .s_ip_length(tx_ip_length), + .s_ip_ttl(tx_ip_ttl), + .s_ip_protocol(tx_ip_protocol), + .s_ip_source_ip(tx_ip_source_ip), + .s_ip_dest_ip(tx_ip_dest_ip), + .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), + .s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep), + .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), + .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), + .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), + .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), + // IP frame output + .m_ip_hdr_valid(rx_ip_hdr_valid), + .m_ip_hdr_ready(rx_ip_hdr_ready), + .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), + .m_ip_eth_src_mac(rx_ip_eth_src_mac), + .m_ip_eth_type(rx_ip_eth_type), + .m_ip_version(rx_ip_version), + .m_ip_ihl(rx_ip_ihl), + .m_ip_dscp(rx_ip_dscp), + .m_ip_ecn(rx_ip_ecn), + .m_ip_length(rx_ip_length), + .m_ip_identification(rx_ip_identification), + .m_ip_flags(rx_ip_flags), + .m_ip_fragment_offset(rx_ip_fragment_offset), + .m_ip_ttl(rx_ip_ttl), + .m_ip_protocol(rx_ip_protocol), + .m_ip_header_checksum(rx_ip_header_checksum), + .m_ip_source_ip(rx_ip_source_ip), + .m_ip_dest_ip(rx_ip_dest_ip), + .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), + .m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep), + .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), + .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), + .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), + .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), + // UDP frame input + .s_udp_hdr_valid(tx_udp_hdr_valid), + .s_udp_hdr_ready(tx_udp_hdr_ready), + .s_udp_ip_dscp(tx_udp_ip_dscp), + .s_udp_ip_ecn(tx_udp_ip_ecn), + .s_udp_ip_ttl(tx_udp_ip_ttl), + .s_udp_ip_source_ip(tx_udp_ip_source_ip), + .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), + .s_udp_source_port(tx_udp_source_port), + .s_udp_dest_port(tx_udp_dest_port), + .s_udp_length(tx_udp_length), + .s_udp_checksum(tx_udp_checksum), + .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), + .s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep), + .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), + .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), + .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), + .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), + // UDP frame output + .m_udp_hdr_valid(rx_udp_hdr_valid), + .m_udp_hdr_ready(rx_udp_hdr_ready), + .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), + .m_udp_eth_src_mac(rx_udp_eth_src_mac), + .m_udp_eth_type(rx_udp_eth_type), + .m_udp_ip_version(rx_udp_ip_version), + .m_udp_ip_ihl(rx_udp_ip_ihl), + .m_udp_ip_dscp(rx_udp_ip_dscp), + .m_udp_ip_ecn(rx_udp_ip_ecn), + .m_udp_ip_length(rx_udp_ip_length), + .m_udp_ip_identification(rx_udp_ip_identification), + .m_udp_ip_flags(rx_udp_ip_flags), + .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), + .m_udp_ip_ttl(rx_udp_ip_ttl), + .m_udp_ip_protocol(rx_udp_ip_protocol), + .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), + .m_udp_ip_source_ip(rx_udp_ip_source_ip), + .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), + .m_udp_source_port(rx_udp_source_port), + .m_udp_dest_port(rx_udp_dest_port), + .m_udp_length(rx_udp_length), + .m_udp_checksum(rx_udp_checksum), + .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), + .m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep), + .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), + .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), + .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), + .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), + // Status signals + .ip_rx_busy(), + .ip_tx_busy(), + .udp_rx_busy(), + .udp_tx_busy(), + .ip_rx_error_header_early_termination(), + .ip_rx_error_payload_early_termination(), + .ip_rx_error_invalid_header(), + .ip_rx_error_invalid_checksum(), + .ip_tx_error_payload_early_termination(), + .ip_tx_error_arp_failed(), + .udp_rx_error_header_early_termination(), + .udp_rx_error_payload_early_termination(), + .udp_tx_error_payload_early_termination(), + // Configuration + .local_mac(local_mac), + .local_ip(local_ip), + .gateway_ip(gateway_ip), + .subnet_mask(subnet_mask), + .clear_arp_cache(1'b0) +); + +axis_fifo #( + .DEPTH(8192), + .DATA_WIDTH(64), + .KEEP_ENABLE(1), + .KEEP_WIDTH(8), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .FRAME_FIFO(0) +) +udp_payload_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), + .s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep), + .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), + .s_axis_tready(rx_fifo_udp_payload_axis_tready), + .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), + + // AXI output + .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), + .m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep), + .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), + .m_axis_tready(tx_fifo_udp_payload_axis_tready), + .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() +); + +endmodule + +`resetall diff --git a/example/520N_MX/fpga_10g/rtl/sync_signal.v b/example/520N_MX/fpga_10g/rtl/sync_signal.v new file mode 100644 index 000000000..74b855fa1 --- /dev/null +++ b/example/520N_MX/fpga_10g/rtl/sync_signal.v @@ -0,0 +1,62 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule + +`resetall diff --git a/example/520N_MX/fpga_10g/tb/fpga_core/Makefile b/example/520N_MX/fpga_10g/tb/fpga_core/Makefile new file mode 100644 index 000000000..8541e6ca4 --- /dev/null +++ b/example/520N_MX/fpga_10g/tb/fpga_core/Makefile @@ -0,0 +1,95 @@ +# Copyright (c) 2021 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g_fifo.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_rx.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_tx.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_complete_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_checksum_gen_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_complete_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_arb_mux.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_cache.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_rx.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_tx.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_arb_mux.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/arbiter.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/priority_encoder.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v + +# module parameters +#export PARAM_A ?= value + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + +# COMPILE_ARGS += -P $(TOPLEVEL).A=$(PARAM_A) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + +# COMPILE_ARGS += -GA=$(PARAM_A) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..549dc3fc4 --- /dev/null +++ b/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,375 @@ +""" + +Copyright (c) 2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os + +from scapy.layers.l2 import Ether, ARP +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.fork(Clock(dut.clk, 6.4, units="ns").start()) + + # Ethernet + cocotb.fork(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) + self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) + cocotb.fork(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) + self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) + + cocotb.fork(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) + self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) + cocotb.fork(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) + self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) + + cocotb.fork(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) + self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) + cocotb.fork(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) + self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) + + cocotb.fork(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) + self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) + cocotb.fork(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) + self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) + + cocotb.fork(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) + self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) + cocotb.fork(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) + self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) + + cocotb.fork(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) + self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) + cocotb.fork(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) + self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) + + cocotb.fork(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) + self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) + cocotb.fork(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) + self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) + + cocotb.fork(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) + self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) + cocotb.fork(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) + self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) + + cocotb.fork(Clock(dut.qsfp2_rx_clk_1, 6.4, units="ns").start()) + self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1, dut.qsfp2_rx_clk_1, dut.qsfp2_rx_rst_1) + cocotb.fork(Clock(dut.qsfp2_tx_clk_1, 6.4, units="ns").start()) + self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1, dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1) + + cocotb.fork(Clock(dut.qsfp2_rx_clk_2, 6.4, units="ns").start()) + self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2, dut.qsfp2_rx_clk_2, dut.qsfp2_rx_rst_2) + cocotb.fork(Clock(dut.qsfp2_tx_clk_2, 6.4, units="ns").start()) + self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2, dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2) + + cocotb.fork(Clock(dut.qsfp2_rx_clk_3, 6.4, units="ns").start()) + self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3, dut.qsfp2_rx_clk_3, dut.qsfp2_rx_rst_3) + cocotb.fork(Clock(dut.qsfp2_tx_clk_3, 6.4, units="ns").start()) + self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3, dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3) + + cocotb.fork(Clock(dut.qsfp2_rx_clk_4, 6.4, units="ns").start()) + self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4, dut.qsfp2_rx_clk_4, dut.qsfp2_rx_rst_4) + cocotb.fork(Clock(dut.qsfp2_tx_clk_4, 6.4, units="ns").start()) + self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4) + + cocotb.fork(Clock(dut.qsfp3_rx_clk_1, 6.4, units="ns").start()) + self.qsfp3_1_source = XgmiiSource(dut.qsfp3_rxd_1, dut.qsfp3_rxc_1, dut.qsfp3_rx_clk_1, dut.qsfp3_rx_rst_1) + cocotb.fork(Clock(dut.qsfp3_tx_clk_1, 6.4, units="ns").start()) + self.qsfp3_1_sink = XgmiiSink(dut.qsfp3_txd_1, dut.qsfp3_txc_1, dut.qsfp3_tx_clk_1, dut.qsfp3_tx_rst_1) + + cocotb.fork(Clock(dut.qsfp3_rx_clk_2, 6.4, units="ns").start()) + self.qsfp3_2_source = XgmiiSource(dut.qsfp3_rxd_2, dut.qsfp3_rxc_2, dut.qsfp3_rx_clk_2, dut.qsfp3_rx_rst_2) + cocotb.fork(Clock(dut.qsfp3_tx_clk_2, 6.4, units="ns").start()) + self.qsfp3_2_sink = XgmiiSink(dut.qsfp3_txd_2, dut.qsfp3_txc_2, dut.qsfp3_tx_clk_2, dut.qsfp3_tx_rst_2) + + cocotb.fork(Clock(dut.qsfp3_rx_clk_3, 6.4, units="ns").start()) + self.qsfp3_3_source = XgmiiSource(dut.qsfp3_rxd_3, dut.qsfp3_rxc_3, dut.qsfp3_rx_clk_3, dut.qsfp3_rx_rst_3) + cocotb.fork(Clock(dut.qsfp3_tx_clk_3, 6.4, units="ns").start()) + self.qsfp3_3_sink = XgmiiSink(dut.qsfp3_txd_3, dut.qsfp3_txc_3, dut.qsfp3_tx_clk_3, dut.qsfp3_tx_rst_3) + + cocotb.fork(Clock(dut.qsfp3_rx_clk_4, 6.4, units="ns").start()) + self.qsfp3_4_source = XgmiiSource(dut.qsfp3_rxd_4, dut.qsfp3_rxc_4, dut.qsfp3_rx_clk_4, dut.qsfp3_rx_rst_4) + cocotb.fork(Clock(dut.qsfp3_tx_clk_4, 6.4, units="ns").start()) + self.qsfp3_4_sink = XgmiiSink(dut.qsfp3_txd_4, dut.qsfp3_txc_4, dut.qsfp3_tx_clk_4, dut.qsfp3_tx_rst_4) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_4.setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst <= 1 + self.dut.qsfp0_rx_rst_1 <= 1 + self.dut.qsfp0_tx_rst_1 <= 1 + self.dut.qsfp0_rx_rst_2 <= 1 + self.dut.qsfp0_tx_rst_2 <= 1 + self.dut.qsfp0_rx_rst_3 <= 1 + self.dut.qsfp0_tx_rst_3 <= 1 + self.dut.qsfp0_rx_rst_4 <= 1 + self.dut.qsfp0_tx_rst_4 <= 1 + self.dut.qsfp1_rx_rst_1 <= 1 + self.dut.qsfp1_tx_rst_1 <= 1 + self.dut.qsfp1_rx_rst_2 <= 1 + self.dut.qsfp1_tx_rst_2 <= 1 + self.dut.qsfp1_rx_rst_3 <= 1 + self.dut.qsfp1_tx_rst_3 <= 1 + self.dut.qsfp1_rx_rst_4 <= 1 + self.dut.qsfp1_tx_rst_4 <= 1 + self.dut.qsfp2_rx_rst_1 <= 1 + self.dut.qsfp2_tx_rst_1 <= 1 + self.dut.qsfp2_rx_rst_2 <= 1 + self.dut.qsfp2_tx_rst_2 <= 1 + self.dut.qsfp2_rx_rst_3 <= 1 + self.dut.qsfp2_tx_rst_3 <= 1 + self.dut.qsfp2_rx_rst_4 <= 1 + self.dut.qsfp2_tx_rst_4 <= 1 + self.dut.qsfp3_rx_rst_1 <= 1 + self.dut.qsfp3_tx_rst_1 <= 1 + self.dut.qsfp3_rx_rst_2 <= 1 + self.dut.qsfp3_tx_rst_2 <= 1 + self.dut.qsfp3_rx_rst_3 <= 1 + self.dut.qsfp3_tx_rst_3 <= 1 + self.dut.qsfp3_rx_rst_4 <= 1 + self.dut.qsfp3_tx_rst_4 <= 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst <= 0 + self.dut.qsfp0_rx_rst_1 <= 0 + self.dut.qsfp0_tx_rst_1 <= 0 + self.dut.qsfp0_rx_rst_2 <= 0 + self.dut.qsfp0_tx_rst_2 <= 0 + self.dut.qsfp0_rx_rst_3 <= 0 + self.dut.qsfp0_tx_rst_3 <= 0 + self.dut.qsfp0_rx_rst_4 <= 0 + self.dut.qsfp0_tx_rst_4 <= 0 + self.dut.qsfp1_rx_rst_1 <= 0 + self.dut.qsfp1_tx_rst_1 <= 0 + self.dut.qsfp1_rx_rst_2 <= 0 + self.dut.qsfp1_tx_rst_2 <= 0 + self.dut.qsfp1_rx_rst_3 <= 0 + self.dut.qsfp1_tx_rst_3 <= 0 + self.dut.qsfp1_rx_rst_4 <= 0 + self.dut.qsfp1_tx_rst_4 <= 0 + self.dut.qsfp2_rx_rst_1 <= 0 + self.dut.qsfp2_tx_rst_1 <= 0 + self.dut.qsfp2_rx_rst_2 <= 0 + self.dut.qsfp2_tx_rst_2 <= 0 + self.dut.qsfp2_rx_rst_3 <= 0 + self.dut.qsfp2_tx_rst_3 <= 0 + self.dut.qsfp2_rx_rst_4 <= 0 + self.dut.qsfp2_tx_rst_4 <= 0 + self.dut.qsfp3_rx_rst_1 <= 0 + self.dut.qsfp3_tx_rst_1 <= 0 + self.dut.qsfp3_rx_rst_2 <= 0 + self.dut.qsfp3_tx_rst_2 <= 0 + self.dut.qsfp3_rx_rst_3 <= 0 + self.dut.qsfp3_tx_rst_3 <= 0 + self.dut.qsfp3_rx_rst_4 <= 0 + self.dut.qsfp3_tx_rst_4 <= 0 + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("test UDP RX packet") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') + ip = IP(src='192.168.1.100', dst='192.168.1.128') + udp = UDP(sport=5678, dport=1234) + test_pkt = eth / ip / udp / payload + + test_frame = XgmiiFrame.from_payload(test_pkt.build()) + + await tb.qsfp0_1_source.send(test_frame) + + tb.log.info("receive ARP request") + + rx_frame = await tb.qsfp0_1_sink.recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[ARP].hwtype == 1 + assert rx_pkt[ARP].ptype == 0x0800 + assert rx_pkt[ARP].hwlen == 6 + assert rx_pkt[ARP].plen == 4 + assert rx_pkt[ARP].op == 1 + assert rx_pkt[ARP].hwsrc == test_pkt.dst + assert rx_pkt[ARP].psrc == test_pkt[IP].dst + assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' + assert rx_pkt[ARP].pdst == test_pkt[IP].src + + tb.log.info("send ARP response") + + eth = Ether(src=test_pkt.src, dst=test_pkt.dst) + arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, + hwsrc=test_pkt.src, psrc=test_pkt[IP].src, + hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) + resp_pkt = eth / arp + + resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) + + await tb.qsfp0_1_source.send(resp_frame) + + tb.log.info("receive UDP packet") + + rx_frame = await tb.qsfp0_1_sink.recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == test_pkt.src + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[IP].dst == test_pkt[IP].src + assert rx_pkt[IP].src == test_pkt[IP].dst + assert rx_pkt[UDP].dport == test_pkt[UDP].sport + assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert rx_pkt[UDP].payload == test_pkt[UDP].payload + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "eth_axis_rx.v"), + os.path.join(eth_rtl_dir, "eth_axis_tx.v"), + os.path.join(eth_rtl_dir, "udp_complete_64.v"), + os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), + os.path.join(eth_rtl_dir, "udp_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_complete_64.v"), + os.path.join(eth_rtl_dir, "ip_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_arb_mux.v"), + os.path.join(eth_rtl_dir, "arp.v"), + os.path.join(eth_rtl_dir, "arp_cache.v"), + os.path.join(eth_rtl_dir, "arp_eth_rx.v"), + os.path.join(eth_rtl_dir, "arp_eth_tx.v"), + os.path.join(eth_rtl_dir, "eth_arb_mux.v"), + os.path.join(axis_rtl_dir, "arbiter.v"), + os.path.join(axis_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + ] + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )