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fpga: Remove redundant RX_RSS_ENABLE parameter

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-10-13 17:10:25 -07:00
parent 2714ba5cdd
commit d0cc106783
156 changed files with 2 additions and 315 deletions
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6
docs/source/modules/mqnic_core.rst
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@ -217,13 +217,9 @@ Parameters
Enable TCP/UDP checksum offloading on transmit path, default ``1``.
.. object:: RX_RSS_ENABLE
Enable receive side scaling, default ``1``. Requires ``RX_HASH_ENABLE`` to be set.
.. object:: RX_HASH_ENABLE
Enable Toeplitz flow hashing for RX traffic, default ``1``.
Enable Toeplitz flow hashing and receive side scaling for RX traffic, default ``1``.
.. object:: RX_CHECKSUM_ENABLE

3
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -187,7 +187,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -297,7 +296,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -395,7 +393,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -1007,7 +1007,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

3
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -186,7 +186,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -296,7 +295,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -394,7 +392,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -847,7 +847,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/common/rtl/mqnic_core.v
View File

@ -108,7 +108,6 @@ module mqnic_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -2565,7 +2564,6 @@ generate
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/common/rtl/mqnic_core_axi.v
View File

@ -108,7 +108,6 @@ module mqnic_core_axi #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1019,7 +1018,6 @@ mqnic_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/common/rtl/mqnic_core_pcie.v
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@ -108,7 +108,6 @@ module mqnic_core_pcie #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1649,7 +1648,6 @@ mqnic_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/common/rtl/mqnic_core_pcie_ptile.v
View File

@ -108,7 +108,6 @@ module mqnic_core_pcie_ptile #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -815,7 +814,6 @@ mqnic_core_pcie #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/common/rtl/mqnic_core_pcie_s10.v
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@ -108,7 +108,6 @@ module mqnic_core_pcie_s10 #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -824,7 +823,6 @@ mqnic_core_pcie #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/common/rtl/mqnic_core_pcie_us.v
View File

@ -108,7 +108,6 @@ module mqnic_core_pcie_us #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -945,7 +944,6 @@ mqnic_core_pcie #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

1
fpga/common/rtl/mqnic_ingress.v
View File

@ -47,7 +47,6 @@ module mqnic_ingress #
// Receive queue index width
parameter RX_QUEUE_INDEX_WIDTH = 8,
// Enable RX RSS
parameter RX_RSS_ENABLE = 1,
// Enable RX hashing
parameter RX_HASH_ENABLE = 1,
// Enable RX checksum offload

4
fpga/common/rtl/mqnic_interface.v
View File

@ -90,7 +90,6 @@ module mqnic_interface #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1147,7 +1146,7 @@ always @(posedge clk) begin
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // IF ctrl: Next header
RBB+8'h0C: begin
// IF ctrl: features
ctrl_reg_rd_data_reg[0] <= RX_RSS_ENABLE && RX_HASH_ENABLE;
ctrl_reg_rd_data_reg[0] <= RX_HASH_ENABLE;
ctrl_reg_rd_data_reg[4] <= PTP_TS_ENABLE;
ctrl_reg_rd_data_reg[8] <= TX_CHECKSUM_ENABLE;
ctrl_reg_rd_data_reg[9] <= RX_CHECKSUM_ENABLE;
@ -2601,7 +2600,6 @@ mqnic_interface_rx #(
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.MAX_RX_SIZE(MAX_RX_SIZE),

2
fpga/common/rtl/mqnic_interface_rx.v
View File

@ -73,7 +73,6 @@ module mqnic_interface_rx #
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter MAX_RX_SIZE = 9214,
@ -548,7 +547,6 @@ wire [INT_AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser_int;
mqnic_ingress #(
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),

3
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -170,7 +170,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -280,7 +279,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -378,7 +376,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -622,7 +622,6 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

3
fpga/common/tb/mqnic_core_pcie_ptile/Makefile
View File

@ -185,7 +185,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -301,7 +300,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -405,7 +403,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
View File

@ -837,7 +837,6 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

3
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -184,7 +184,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -299,7 +298,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -402,7 +400,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -784,7 +784,6 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

3
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -184,7 +184,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -294,7 +293,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -392,7 +390,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -858,7 +858,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

3
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -186,7 +186,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_TAG_WIDTH ?= 16
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -296,7 +295,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -394,7 +392,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -913,7 +913,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1823,7 +1822,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
View File

@ -105,7 +105,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -872,7 +871,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
View File

@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -289,7 +288,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -764,7 +764,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1422,7 +1421,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1139,7 +1138,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -830,7 +830,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -2170,7 +2169,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -105,7 +105,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -941,7 +940,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -289,7 +288,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -764,7 +764,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1773,7 +1772,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1207,7 +1206,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -830,7 +830,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -2553,7 +2552,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -105,7 +105,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -949,7 +948,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -289,7 +288,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -764,7 +764,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -2153,7 +2152,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1216,7 +1215,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -830,7 +830,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -2553,7 +2552,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -105,7 +105,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -949,7 +948,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -289,7 +288,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -764,7 +764,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -2153,7 +2152,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1216,7 +1215,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -830,7 +830,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -3562,7 +3561,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -105,7 +105,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -892,7 +891,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -289,7 +288,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -753,7 +753,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -3170,7 +3169,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1159,7 +1158,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -819,7 +819,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -2785,7 +2784,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -105,7 +105,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -815,7 +814,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -289,7 +288,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -713,7 +713,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -2588,7 +2587,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1001,7 +1000,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -739,7 +739,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -784,7 +783,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v
View File

@ -104,7 +104,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 8,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -802,7 +801,6 @@ mqnic_core_pcie_ptile #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -298,7 +297,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -392,7 +390,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -790,7 +790,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1682,7 +1681,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v
View File

@ -106,7 +106,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 8,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1236,7 +1235,6 @@ mqnic_core_pcie_ptile #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile
View File

@ -194,7 +194,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -302,7 +301,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -398,7 +396,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -1110,7 +1110,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1625,7 +1624,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1235,7 +1234,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -794,7 +794,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1361,7 +1360,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -106,7 +106,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -781,7 +780,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
View File

@ -191,7 +191,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -294,7 +293,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -385,7 +383,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -716,7 +716,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v
View File

@ -99,7 +99,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1076,7 +1075,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
View File

@ -106,7 +106,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -935,7 +934,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -705,7 +705,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1550,7 +1549,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1271,7 +1270,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -834,7 +834,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

2
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v
View File

@ -102,7 +102,6 @@ module fpga #
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
@ -1117,7 +1116,6 @@ fpga_core #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

2
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
View File

@ -109,7 +109,6 @@ module fpga_core #
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
@ -1033,7 +1032,6 @@ mqnic_core_pcie_us #(
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),

3
fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
View File

@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
@ -295,7 +294,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)

1
fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -734,7 +734,6 @@ def test_fpga_core(request):
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768

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