From d0cc1067831f5de4a82103082414e58cc818b0f1 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 13 Oct 2022 17:10:25 -0700 Subject: [PATCH] fpga: Remove redundant RX_RSS_ENABLE parameter Signed-off-by: Alex Forencich --- docs/source/modules/mqnic_core.rst | 6 +----- fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile | 3 --- .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 1 - fpga/app/template/tb/mqnic_core_pcie_us/Makefile | 3 --- .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 1 - fpga/common/rtl/mqnic_core.v | 2 -- fpga/common/rtl/mqnic_core_axi.v | 2 -- fpga/common/rtl/mqnic_core_pcie.v | 2 -- fpga/common/rtl/mqnic_core_pcie_ptile.v | 2 -- fpga/common/rtl/mqnic_core_pcie_s10.v | 2 -- fpga/common/rtl/mqnic_core_pcie_us.v | 2 -- fpga/common/rtl/mqnic_ingress.v | 1 - fpga/common/rtl/mqnic_interface.v | 4 +--- fpga/common/rtl/mqnic_interface_rx.v | 2 -- fpga/common/tb/mqnic_core_axi/Makefile | 3 --- fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py | 1 - fpga/common/tb/mqnic_core_pcie_ptile/Makefile | 3 --- .../tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py | 1 - fpga/common/tb/mqnic_core_pcie_s10/Makefile | 3 --- .../tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py | 1 - fpga/common/tb/mqnic_core_pcie_us/Makefile | 3 --- .../common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 1 - fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile | 3 --- .../tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py | 1 - fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile | 3 --- .../ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile | 3 --- .../ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU200/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU200/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU250/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU250/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU280/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU280/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU50/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU50/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile | 3 --- .../DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile | 3 --- .../DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v | 2 -- fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v | 2 -- .../mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile | 3 --- .../fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v | 2 -- fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v | 2 -- fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 3 --- fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v | 2 -- fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v | 2 -- fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile | 3 --- fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile | 3 --- .../Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile | 3 --- .../Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ZCU102/fpga/rtl/fpga.v | 2 -- fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v | 2 -- fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile | 3 --- fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v | 2 -- fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v | 2 -- fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile | 3 --- fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v | 2 -- fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v | 2 -- fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile | 3 --- .../mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile | 3 --- fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - 156 files changed, 2 insertions(+), 315 deletions(-) diff --git a/docs/source/modules/mqnic_core.rst b/docs/source/modules/mqnic_core.rst index 66281fb18..4174e8a6d 100644 --- a/docs/source/modules/mqnic_core.rst +++ b/docs/source/modules/mqnic_core.rst @@ -217,13 +217,9 @@ Parameters Enable TCP/UDP checksum offloading on transmit path, default ``1``. -.. object:: RX_RSS_ENABLE - - Enable receive side scaling, default ``1``. Requires ``RX_HASH_ENABLE`` to be set. - .. object:: RX_HASH_ENABLE - Enable Toeplitz flow hashing for RX traffic, default ``1``. + Enable Toeplitz flow hashing and receive side scaling for RX traffic, default ``1``. .. object:: RX_CHECKSUM_ENABLE diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index 021d6eb57..f8173e80c 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -187,7 +187,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE) export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_TAG_WIDTH ?= 16 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -297,7 +296,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -395,7 +393,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 41d3a06d6..51a99deae 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -1007,7 +1007,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_TAG_WIDTH'] = 16 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index 4e76bdc26..0445cd31c 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -186,7 +186,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE) export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_TAG_WIDTH ?= 16 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -296,7 +295,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -394,7 +392,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 5e3ad45dd..abe750454 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -847,7 +847,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_TAG_WIDTH'] = 16 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 15d872364..672ce5c4a 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -108,7 +108,6 @@ module mqnic_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2565,7 +2564,6 @@ generate .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v index eed53e193..b3a1372dc 100644 --- a/fpga/common/rtl/mqnic_core_axi.v +++ b/fpga/common/rtl/mqnic_core_axi.v @@ -108,7 +108,6 @@ module mqnic_core_axi # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1019,7 +1018,6 @@ mqnic_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index 5ac394bc9..b12892b89 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -108,7 +108,6 @@ module mqnic_core_pcie # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1649,7 +1648,6 @@ mqnic_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/common/rtl/mqnic_core_pcie_ptile.v b/fpga/common/rtl/mqnic_core_pcie_ptile.v index e0c9634de..340c7de63 100644 --- a/fpga/common/rtl/mqnic_core_pcie_ptile.v +++ b/fpga/common/rtl/mqnic_core_pcie_ptile.v @@ -108,7 +108,6 @@ module mqnic_core_pcie_ptile # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -815,7 +814,6 @@ mqnic_core_pcie #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index c5493b5e2..74c687f5d 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -108,7 +108,6 @@ module mqnic_core_pcie_s10 # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -824,7 +823,6 @@ mqnic_core_pcie #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index d0b21d442..36931ed0c 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -108,7 +108,6 @@ module mqnic_core_pcie_us # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -945,7 +944,6 @@ mqnic_core_pcie #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/common/rtl/mqnic_ingress.v b/fpga/common/rtl/mqnic_ingress.v index 9a6832943..9a820095d 100644 --- a/fpga/common/rtl/mqnic_ingress.v +++ b/fpga/common/rtl/mqnic_ingress.v @@ -47,7 +47,6 @@ module mqnic_ingress # // Receive queue index width parameter RX_QUEUE_INDEX_WIDTH = 8, // Enable RX RSS - parameter RX_RSS_ENABLE = 1, // Enable RX hashing parameter RX_HASH_ENABLE = 1, // Enable RX checksum offload diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index e3a9e1f02..0c3c9ee3a 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -90,7 +90,6 @@ module mqnic_interface # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1147,7 +1146,7 @@ always @(posedge clk) begin RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // IF ctrl: Next header RBB+8'h0C: begin // IF ctrl: features - ctrl_reg_rd_data_reg[0] <= RX_RSS_ENABLE && RX_HASH_ENABLE; + ctrl_reg_rd_data_reg[0] <= RX_HASH_ENABLE; ctrl_reg_rd_data_reg[4] <= PTP_TS_ENABLE; ctrl_reg_rd_data_reg[8] <= TX_CHECKSUM_ENABLE; ctrl_reg_rd_data_reg[9] <= RX_CHECKSUM_ENABLE; @@ -2601,7 +2600,6 @@ mqnic_interface_rx #( // Interface configuration .PTP_TS_ENABLE(PTP_TS_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .MAX_RX_SIZE(MAX_RX_SIZE), diff --git a/fpga/common/rtl/mqnic_interface_rx.v b/fpga/common/rtl/mqnic_interface_rx.v index b58c05ab4..b57cbef51 100644 --- a/fpga/common/rtl/mqnic_interface_rx.v +++ b/fpga/common/rtl/mqnic_interface_rx.v @@ -73,7 +73,6 @@ module mqnic_interface_rx # // Interface configuration parameter PTP_TS_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter MAX_RX_SIZE = 9214, @@ -548,7 +547,6 @@ wire [INT_AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser_int; mqnic_ingress #( .REQ_TAG_WIDTH(REQ_TAG_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index 5e8b3d24e..9b69f09b3 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -170,7 +170,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE) export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_TAG_WIDTH ?= 16 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -280,7 +279,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -378,7 +376,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index 1ce8d8cbd..07aa9a25b 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -622,7 +622,6 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_TAG_WIDTH'] = 16 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index 2c24f22ef..3b8998301 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -185,7 +185,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE) export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_TAG_WIDTH ?= 16 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -301,7 +300,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -405,7 +403,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index c5fdf660f..61536b73e 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -837,7 +837,6 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_TAG_WIDTH'] = 16 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index d82196046..1fc748a49 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -184,7 +184,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE) export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_TAG_WIDTH ?= 16 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -299,7 +298,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -402,7 +400,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 2ad4c5c0b..7a470199b 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -784,7 +784,6 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_TAG_WIDTH'] = 16 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index 90a218ac9..27ea6bc26 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -184,7 +184,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE) export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_TAG_WIDTH ?= 16 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -294,7 +293,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -392,7 +390,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index d86104434..65775fe6f 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -858,7 +858,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_TAG_WIDTH'] = 16 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 348964d40..04b6c3242 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -186,7 +186,6 @@ export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE) export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_TAG_WIDTH ?= 16 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -296,7 +295,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -394,7 +392,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index 98696831c..3f7b731d9 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -913,7 +913,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_TAG_WIDTH'] = 16 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v index e38fc72a8..88a162990 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1823,7 +1822,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index 88afa0904..8ea56621c 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -872,7 +871,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index 0af5692fb..a8dfe24f5 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index 0645297d6..037b4f576 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -764,7 +764,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index d04270040..82bf0ad72 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1422,7 +1421,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v index 5937fca0d..e0ee8d09a 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1139,7 +1138,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index 2f22618d1..a0ffd1336 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index 6cd4aca54..ad2b493d3 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -830,7 +830,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v index 851d28117..b89062904 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2170,7 +2169,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index dcc969d89..4b02613c1 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -941,7 +940,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index ec086db3b..f96fe70a7 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 567b351a7..6725a712a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -764,7 +764,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 3c62f2722..707668183 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1773,7 +1772,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 4042769fa..5620bfee3 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1207,7 +1206,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index c6be61fca..e0b07f00e 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index d56636995..e71f94c17 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -830,7 +830,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index 6ed1184bb..be706eff4 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2553,7 +2552,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 709cedcbb..c7816d56d 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -949,7 +948,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index fc5078e61..f1c6022b6 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index 29403148f..074e659f5 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -764,7 +764,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index cb256a990..4c41516d0 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2153,7 +2152,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 1a21164b4..a8ac57187 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1216,7 +1215,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index 240acf838..37f6900d3 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index 0fffef2e9..ef4c2e213 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -830,7 +830,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v index 5ed4e4767..0b013b5db 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2553,7 +2552,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index b5804182c..7b85010c8 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -949,7 +948,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index fc5078e61..f1c6022b6 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index 29403148f..074e659f5 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -764,7 +764,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index af639874b..67b978a47 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2153,7 +2152,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v index d82687402..ace5fed87 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1216,7 +1215,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile index 240acf838..37f6900d3 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py index 0fffef2e9..ef4c2e213 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -830,7 +830,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v index f853f0055..a20c79a6c 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -3562,7 +3561,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index b4fa15cff..313787e13 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -892,7 +891,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index b0d2dce6c..8066b891c 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 1b10d7b46..2a89b165d 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -753,7 +753,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index d7454047c..8a185a71d 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -3170,7 +3169,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index eb3f954e5..8aaf878ab 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1159,7 +1158,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index 69f99a36e..78631f7d6 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index 8c29ef418..29a583be4 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -819,7 +819,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v index efeb7f344..3e605716b 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2785,7 +2784,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index eee392c9d..961019611 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -815,7 +814,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index e45407a3d..90a1f3610 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 1c31e4d4e..27fff88a1 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -713,7 +713,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index 238aadb28..04a31307f 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -2588,7 +2587,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index 6210ae808..3f9bd09a5 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1001,7 +1000,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index 78adf604a..b41d0ca2c 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index ad33400b5..7be96b239 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -739,7 +739,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v index 92125105d..c0748c97a 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -784,7 +783,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v index e008a07f4..8036ed851 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v @@ -104,7 +104,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 8, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -802,7 +801,6 @@ mqnic_core_pcie_ptile #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile index 94eb03b0d..88215e5d7 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -298,7 +297,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -392,7 +390,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index 9a7460bc2..fd7af1468 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -790,7 +790,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v index bd177b4b4..de66fb761 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1682,7 +1681,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v index 45abc2417..67b2ae265 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v @@ -106,7 +106,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 8, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1236,7 +1235,6 @@ mqnic_core_pcie_ptile #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile index 647d6f701..9a03877da 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile @@ -194,7 +194,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -302,7 +301,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -398,7 +396,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py index 426c78c87..68f020a91 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -1110,7 +1110,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index 31ebe99f9..8d697694d 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1625,7 +1624,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index faf864b62..9c257833d 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1235,7 +1234,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index dad23a675..d9129336c 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index a04f048d4..a1f1e03c5 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -794,7 +794,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v index 8c61a070f..be35f61ed 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1361,7 +1360,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index 09f294605..645fc618c 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -106,7 +106,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -781,7 +780,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index f2ace3706..4569f31e6 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -191,7 +191,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -294,7 +293,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -385,7 +383,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index a5ade26e7..6dc4e5503 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -716,7 +716,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v index 9d9651925..2b368a243 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1076,7 +1075,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v index 306bae16b..81c0f575e 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v @@ -106,7 +106,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -935,7 +934,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile index bf4338d83..ddb85a2ba 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py index b3751f1f0..e530d069f 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py @@ -705,7 +705,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index 2eb5a958b..1bf8fefd8 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1550,7 +1549,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index 45cc821d8..cd4c6a634 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1271,7 +1270,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index 003484aef..5f0553eb0 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index bf9e7ea6e..2ca99b725 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -834,7 +834,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v index fd583c837..62735a8e5 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1117,7 +1116,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v index d1c0fd707..3c0f835a2 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1033,7 +1032,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index 003484aef..5f0553eb0 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index 44c17c781..0abf22bfa 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -734,7 +734,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v index 6dc61caa0..dc51fed7f 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1067,7 +1066,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v index 2d7b268fe..b327571a6 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v @@ -106,7 +106,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -962,7 +961,6 @@ mqnic_core_pcie_ptile #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile index 6ed4fe546..0ebe5abe4 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile @@ -191,7 +191,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -299,7 +298,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -395,7 +393,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index 1becc1e87..c5b002b5c 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -900,7 +900,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v index d263ed527..c635e687b 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1013,7 +1012,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v index 90e037e47..31be71c02 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -890,7 +889,6 @@ mqnic_core_pcie_s10 #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile index 9994f094d..c163e829c 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile @@ -191,7 +191,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -297,7 +296,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -391,7 +389,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index 225e4f7cd..4c3742c5c 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -739,7 +739,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index 08aa0e42c..888b71f38 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1543,7 +1542,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v index 6ca084ef8..a0754baa6 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1041,7 +1040,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index da400240b..eb5536546 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index 7779d7ac5..eb00c5e94 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -726,7 +726,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v index 5f9813ed0..4869abfe5 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2160,7 +2159,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index 5ff7ab5cb..b70d626ac 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -917,7 +916,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index c7dc789cc..198bc81ff 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index 9fbbe9b06..7f518110a 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -768,7 +768,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index 3d3587b7f..388274316 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1759,7 +1758,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index 1043d129a..7ac7aa866 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1184,7 +1183,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index c53d6f95b..c42c2988c 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index 0d2829d91..d38424f48 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -834,7 +834,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v index dc2cf893c..33d6bb1b8 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2398,7 +2397,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index c012468b8..682211ee7 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -872,7 +871,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index fc5078e61..f1c6022b6 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index e632e4495..45ed8e263 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -762,7 +762,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index 26a7a256f..ebd6d4415 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1998,7 +1997,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v index 441992db7..c05379e41 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1139,7 +1138,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile index 240acf838..37f6900d3 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py index 7c9029908..17e001c9a 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -828,7 +828,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index 016d8dac0..677ce5de0 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -3329,7 +3328,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index 3f17c0e18..148583e72 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1128,7 +1127,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index 00356574f..3307fdebc 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -185,7 +185,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -289,7 +288,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -381,7 +379,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index 66341cdb9..8deec841e 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -832,7 +832,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index 462baa350..816c70a4c 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2529,7 +2528,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index eb64787df..b769c5aaa 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1557,7 +1556,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index 82d355d8a..aa6509b11 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index 749669bc4..1ee685c63 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -978,7 +978,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index 372e5ed8b..81c660dd8 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1030,7 +1029,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v index 803b65d2f..042abee9e 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -904,7 +903,6 @@ mqnic_core_axi #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index 0ac594e6a..b9d70d285 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -176,7 +176,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -272,7 +271,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -358,7 +356,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index a49fdfbf2..83b4b888c 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -519,7 +519,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index 1e428346a..8104b3ea6 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -1085,7 +1084,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index 317d171de..7f9d792e9 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -899,7 +898,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index c25724fcd..d11eebec4 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -192,7 +192,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -295,7 +294,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -386,7 +384,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index b005dc7aa..eb0bb237b 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -728,7 +728,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index 2a0a19922..a957e95de 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -951,7 +950,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index e0a81cc8a..12329fba7 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -858,7 +857,6 @@ mqnic_core_axi #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index 0ac594e6a..b9d70d285 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -176,7 +176,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -272,7 +271,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -358,7 +356,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index 115de52db..a35731c33 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -489,7 +489,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index 3a2478b7b..21877fdd6 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -99,7 +99,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2486,7 +2485,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 805cd38dd..261baa763 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -105,7 +105,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -974,7 +973,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index 01a8d4265..ee9268101 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -186,7 +186,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -290,7 +289,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -382,7 +380,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index f1fb98a22..0ef756d02 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -769,7 +769,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index 67d88be58..a5cba7376 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -102,7 +102,6 @@ module fpga # parameter PTP_TS_ENABLE = 1, parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter TX_FIFO_DEPTH = 32768, @@ -2098,7 +2097,6 @@ fpga_core #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 45909f424..1eb027f1d 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -109,7 +109,6 @@ module fpga_core # parameter TX_CPL_FIFO_DEPTH = 32, parameter TX_TAG_WIDTH = 16, parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, parameter ENABLE_PADDING = 1, @@ -1240,7 +1239,6 @@ mqnic_core_pcie_us #( .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), .TX_TAG_WIDTH(TX_TAG_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index 4c036a7f0..b58f2cd6b 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -193,7 +193,6 @@ export PARAM_TDMA_INDEX_WIDTH ?= 6 export PARAM_PTP_TS_ENABLE ?= 1 export PARAM_TX_CPL_FIFO_DEPTH ?= 32 export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 export PARAM_RX_HASH_ENABLE ?= 1 export PARAM_RX_CHECKSUM_ENABLE ?= 1 export PARAM_TX_FIFO_DEPTH ?= 32768 @@ -296,7 +295,6 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) @@ -387,7 +385,6 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 05976d5af..6ea1636fd 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -833,7 +833,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768