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docs: Fix signal names
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@ -59,8 +59,8 @@ Packet transmission
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#. :ref:`mod_mqnic_app_block` ``s_axis_sync_tx``: data is presented to the application section
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#. :ref:`mod_mqnic_app_block` ``m_axis_sync_tx``: data is returned from the application section
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#. :ref:`mod_mqnic_core`: Data passes through per-port transmit async FIFO module and is transferred to MAC TX clock domain
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#. :ref:`mod_mqnic_app_block` ``s_axis_sync_tx``: data is presented to the application section
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#. :ref:`mod_mqnic_app_block` ``m_axis_sync_tx``: data is returned from the application section
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#. :ref:`mod_mqnic_app_block` ``s_axis_direct_tx``: data is presented to the application section
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#. :ref:`mod_mqnic_app_block` ``m_axis_direct_tx``: data is returned from the application section
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#. :ref:`mod_mqnic_l2_egress`: layer 2 egress processing
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#. :ref:`mod_mqnic_core`: data leaves through transmit streaming interfaces
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#. The packet arrives at the MAC
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@ -141,8 +141,8 @@ receive:
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#. The MAC produces a PTP timestamp
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#. :ref:`mod_mqnic_core`: data enters through receive streaming interfaces
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#. :ref:`mod_mqnic_l2_ingress`: layer 2 ingress processing
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#. :ref:`mod_mqnic_app_block` ``s_axis_sync_rx``: data is presented to the application section
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#. :ref:`mod_mqnic_app_block` ``m_axis_sync_rx``: data is returned from the application section
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#. :ref:`mod_mqnic_app_block` ``s_axis_direct_rx``: data is presented to the application section
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#. :ref:`mod_mqnic_app_block` ``m_axis_direct_rx``: data is returned from the application section
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#. :ref:`mod_mqnic_core`: Data passes through per-port receive async FIFO module and is transferred to core clock domain
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#. :ref:`mod_mqnic_app_block` ``s_axis_sync_rx``: data is presented to the application section
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#. :ref:`mod_mqnic_app_block` ``m_axis_sync_rx``: data is returned from the application section
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