diff --git a/fpga/lib/eth/.github/workflows/regression-tests.yml b/fpga/lib/eth/.github/workflows/regression-tests.yml index a5243a10e..6acc2873c 100644 --- a/fpga/lib/eth/.github/workflows/regression-tests.yml +++ b/fpga/lib/eth/.github/workflows/regression-tests.yml @@ -9,14 +9,14 @@ jobs: strategy: matrix: - python-version: [3.9] + python-version: ["3.10"] group: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10] steps: - - uses: actions/checkout@v1 + - uses: actions/checkout@v3 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v2 + uses: actions/setup-python@v4 with: python-version: ${{ matrix.python-version }} @@ -30,4 +30,4 @@ jobs: pip install tox tox-gh-actions - name: Test with tox - run: tox -- --splits 10 --group ${{ matrix.group }} --splitting-algorithm least_duration + run: tox -- -n auto --verbose --splits 10 --group ${{ matrix.group }} --splitting-algorithm least_duration diff --git a/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py index 8c0e0c856..ef7224c09 100644 --- a/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -167,76 +167,76 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp0_rx_rst_1 <= 1 - self.dut.qsfp0_tx_rst_1 <= 1 - self.dut.qsfp0_rx_rst_2 <= 1 - self.dut.qsfp0_tx_rst_2 <= 1 - self.dut.qsfp0_rx_rst_3 <= 1 - self.dut.qsfp0_tx_rst_3 <= 1 - self.dut.qsfp0_rx_rst_4 <= 1 - self.dut.qsfp0_tx_rst_4 <= 1 - self.dut.qsfp1_rx_rst_1 <= 1 - self.dut.qsfp1_tx_rst_1 <= 1 - self.dut.qsfp1_rx_rst_2 <= 1 - self.dut.qsfp1_tx_rst_2 <= 1 - self.dut.qsfp1_rx_rst_3 <= 1 - self.dut.qsfp1_tx_rst_3 <= 1 - self.dut.qsfp1_rx_rst_4 <= 1 - self.dut.qsfp1_tx_rst_4 <= 1 - self.dut.qsfp2_rx_rst_1 <= 1 - self.dut.qsfp2_tx_rst_1 <= 1 - self.dut.qsfp2_rx_rst_2 <= 1 - self.dut.qsfp2_tx_rst_2 <= 1 - self.dut.qsfp2_rx_rst_3 <= 1 - self.dut.qsfp2_tx_rst_3 <= 1 - self.dut.qsfp2_rx_rst_4 <= 1 - self.dut.qsfp2_tx_rst_4 <= 1 - self.dut.qsfp3_rx_rst_1 <= 1 - self.dut.qsfp3_tx_rst_1 <= 1 - self.dut.qsfp3_rx_rst_2 <= 1 - self.dut.qsfp3_tx_rst_2 <= 1 - self.dut.qsfp3_rx_rst_3 <= 1 - self.dut.qsfp3_tx_rst_3 <= 1 - self.dut.qsfp3_rx_rst_4 <= 1 - self.dut.qsfp3_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp0_rx_rst_1.value = 1 + self.dut.qsfp0_tx_rst_1.value = 1 + self.dut.qsfp0_rx_rst_2.value = 1 + self.dut.qsfp0_tx_rst_2.value = 1 + self.dut.qsfp0_rx_rst_3.value = 1 + self.dut.qsfp0_tx_rst_3.value = 1 + self.dut.qsfp0_rx_rst_4.value = 1 + self.dut.qsfp0_tx_rst_4.value = 1 + self.dut.qsfp1_rx_rst_1.value = 1 + self.dut.qsfp1_tx_rst_1.value = 1 + self.dut.qsfp1_rx_rst_2.value = 1 + self.dut.qsfp1_tx_rst_2.value = 1 + self.dut.qsfp1_rx_rst_3.value = 1 + self.dut.qsfp1_tx_rst_3.value = 1 + self.dut.qsfp1_rx_rst_4.value = 1 + self.dut.qsfp1_tx_rst_4.value = 1 + self.dut.qsfp2_rx_rst_1.value = 1 + self.dut.qsfp2_tx_rst_1.value = 1 + self.dut.qsfp2_rx_rst_2.value = 1 + self.dut.qsfp2_tx_rst_2.value = 1 + self.dut.qsfp2_rx_rst_3.value = 1 + self.dut.qsfp2_tx_rst_3.value = 1 + self.dut.qsfp2_rx_rst_4.value = 1 + self.dut.qsfp2_tx_rst_4.value = 1 + self.dut.qsfp3_rx_rst_1.value = 1 + self.dut.qsfp3_tx_rst_1.value = 1 + self.dut.qsfp3_rx_rst_2.value = 1 + self.dut.qsfp3_tx_rst_2.value = 1 + self.dut.qsfp3_rx_rst_3.value = 1 + self.dut.qsfp3_tx_rst_3.value = 1 + self.dut.qsfp3_rx_rst_4.value = 1 + self.dut.qsfp3_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp0_rx_rst_1 <= 0 - self.dut.qsfp0_tx_rst_1 <= 0 - self.dut.qsfp0_rx_rst_2 <= 0 - self.dut.qsfp0_tx_rst_2 <= 0 - self.dut.qsfp0_rx_rst_3 <= 0 - self.dut.qsfp0_tx_rst_3 <= 0 - self.dut.qsfp0_rx_rst_4 <= 0 - self.dut.qsfp0_tx_rst_4 <= 0 - self.dut.qsfp1_rx_rst_1 <= 0 - self.dut.qsfp1_tx_rst_1 <= 0 - self.dut.qsfp1_rx_rst_2 <= 0 - self.dut.qsfp1_tx_rst_2 <= 0 - self.dut.qsfp1_rx_rst_3 <= 0 - self.dut.qsfp1_tx_rst_3 <= 0 - self.dut.qsfp1_rx_rst_4 <= 0 - self.dut.qsfp1_tx_rst_4 <= 0 - self.dut.qsfp2_rx_rst_1 <= 0 - self.dut.qsfp2_tx_rst_1 <= 0 - self.dut.qsfp2_rx_rst_2 <= 0 - self.dut.qsfp2_tx_rst_2 <= 0 - self.dut.qsfp2_rx_rst_3 <= 0 - self.dut.qsfp2_tx_rst_3 <= 0 - self.dut.qsfp2_rx_rst_4 <= 0 - self.dut.qsfp2_tx_rst_4 <= 0 - self.dut.qsfp3_rx_rst_1 <= 0 - self.dut.qsfp3_tx_rst_1 <= 0 - self.dut.qsfp3_rx_rst_2 <= 0 - self.dut.qsfp3_tx_rst_2 <= 0 - self.dut.qsfp3_rx_rst_3 <= 0 - self.dut.qsfp3_tx_rst_3 <= 0 - self.dut.qsfp3_rx_rst_4 <= 0 - self.dut.qsfp3_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp0_rx_rst_1.value = 0 + self.dut.qsfp0_tx_rst_1.value = 0 + self.dut.qsfp0_rx_rst_2.value = 0 + self.dut.qsfp0_tx_rst_2.value = 0 + self.dut.qsfp0_rx_rst_3.value = 0 + self.dut.qsfp0_tx_rst_3.value = 0 + self.dut.qsfp0_rx_rst_4.value = 0 + self.dut.qsfp0_tx_rst_4.value = 0 + self.dut.qsfp1_rx_rst_1.value = 0 + self.dut.qsfp1_tx_rst_1.value = 0 + self.dut.qsfp1_rx_rst_2.value = 0 + self.dut.qsfp1_tx_rst_2.value = 0 + self.dut.qsfp1_rx_rst_3.value = 0 + self.dut.qsfp1_tx_rst_3.value = 0 + self.dut.qsfp1_rx_rst_4.value = 0 + self.dut.qsfp1_tx_rst_4.value = 0 + self.dut.qsfp2_rx_rst_1.value = 0 + self.dut.qsfp2_tx_rst_1.value = 0 + self.dut.qsfp2_rx_rst_2.value = 0 + self.dut.qsfp2_tx_rst_2.value = 0 + self.dut.qsfp2_rx_rst_3.value = 0 + self.dut.qsfp2_tx_rst_3.value = 0 + self.dut.qsfp2_rx_rst_4.value = 0 + self.dut.qsfp2_tx_rst_4.value = 0 + self.dut.qsfp3_rx_rst_1.value = 0 + self.dut.qsfp3_tx_rst_1.value = 0 + self.dut.qsfp3_rx_rst_2.value = 0 + self.dut.qsfp3_tx_rst_2.value = 0 + self.dut.qsfp3_rx_rst_3.value = 0 + self.dut.qsfp3_tx_rst_3.value = 0 + self.dut.qsfp3_rx_rst_4.value = 0 + self.dut.qsfp3_tx_rst_4.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py index d65d197cf..6d907a8c7 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -113,44 +113,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp_0_rx_rst_0 <= 1 - self.dut.qsfp_0_tx_rst_0 <= 1 - self.dut.qsfp_0_rx_rst_1 <= 1 - self.dut.qsfp_0_tx_rst_1 <= 1 - self.dut.qsfp_0_rx_rst_2 <= 1 - self.dut.qsfp_0_tx_rst_2 <= 1 - self.dut.qsfp_0_rx_rst_3 <= 1 - self.dut.qsfp_0_tx_rst_3 <= 1 - self.dut.qsfp_1_rx_rst_0 <= 1 - self.dut.qsfp_1_tx_rst_0 <= 1 - self.dut.qsfp_1_rx_rst_1 <= 1 - self.dut.qsfp_1_tx_rst_1 <= 1 - self.dut.qsfp_1_rx_rst_2 <= 1 - self.dut.qsfp_1_tx_rst_2 <= 1 - self.dut.qsfp_1_rx_rst_3 <= 1 - self.dut.qsfp_1_tx_rst_3 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp_0_rx_rst_0.value = 1 + self.dut.qsfp_0_tx_rst_0.value = 1 + self.dut.qsfp_0_rx_rst_1.value = 1 + self.dut.qsfp_0_tx_rst_1.value = 1 + self.dut.qsfp_0_rx_rst_2.value = 1 + self.dut.qsfp_0_tx_rst_2.value = 1 + self.dut.qsfp_0_rx_rst_3.value = 1 + self.dut.qsfp_0_tx_rst_3.value = 1 + self.dut.qsfp_1_rx_rst_0.value = 1 + self.dut.qsfp_1_tx_rst_0.value = 1 + self.dut.qsfp_1_rx_rst_1.value = 1 + self.dut.qsfp_1_tx_rst_1.value = 1 + self.dut.qsfp_1_rx_rst_2.value = 1 + self.dut.qsfp_1_tx_rst_2.value = 1 + self.dut.qsfp_1_rx_rst_3.value = 1 + self.dut.qsfp_1_tx_rst_3.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp_0_rx_rst_0 <= 0 - self.dut.qsfp_0_tx_rst_0 <= 0 - self.dut.qsfp_0_rx_rst_1 <= 0 - self.dut.qsfp_0_tx_rst_1 <= 0 - self.dut.qsfp_0_rx_rst_2 <= 0 - self.dut.qsfp_0_tx_rst_2 <= 0 - self.dut.qsfp_0_rx_rst_3 <= 0 - self.dut.qsfp_0_tx_rst_3 <= 0 - self.dut.qsfp_1_rx_rst_0 <= 0 - self.dut.qsfp_1_tx_rst_0 <= 0 - self.dut.qsfp_1_rx_rst_1 <= 0 - self.dut.qsfp_1_tx_rst_1 <= 0 - self.dut.qsfp_1_rx_rst_2 <= 0 - self.dut.qsfp_1_tx_rst_2 <= 0 - self.dut.qsfp_1_rx_rst_3 <= 0 - self.dut.qsfp_1_tx_rst_3 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp_0_rx_rst_0.value = 0 + self.dut.qsfp_0_tx_rst_0.value = 0 + self.dut.qsfp_0_rx_rst_1.value = 0 + self.dut.qsfp_0_tx_rst_1.value = 0 + self.dut.qsfp_0_rx_rst_2.value = 0 + self.dut.qsfp_0_tx_rst_2.value = 0 + self.dut.qsfp_0_rx_rst_3.value = 0 + self.dut.qsfp_0_tx_rst_3.value = 0 + self.dut.qsfp_1_rx_rst_0.value = 0 + self.dut.qsfp_1_tx_rst_0.value = 0 + self.dut.qsfp_1_rx_rst_1.value = 0 + self.dut.qsfp_1_tx_rst_1.value = 0 + self.dut.qsfp_1_rx_rst_2.value = 0 + self.dut.qsfp_1_tx_rst_2.value = 0 + self.dut.qsfp_1_rx_rst_3.value = 0 + self.dut.qsfp_1_tx_rst_3.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index ec5c34f30..78e9eb932 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -113,44 +113,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp_0_rx_rst_0 <= 1 - self.dut.qsfp_0_tx_rst_0 <= 1 - self.dut.qsfp_0_rx_rst_1 <= 1 - self.dut.qsfp_0_tx_rst_1 <= 1 - self.dut.qsfp_0_rx_rst_2 <= 1 - self.dut.qsfp_0_tx_rst_2 <= 1 - self.dut.qsfp_0_rx_rst_3 <= 1 - self.dut.qsfp_0_tx_rst_3 <= 1 - self.dut.qsfp_1_rx_rst_0 <= 1 - self.dut.qsfp_1_tx_rst_0 <= 1 - self.dut.qsfp_1_rx_rst_1 <= 1 - self.dut.qsfp_1_tx_rst_1 <= 1 - self.dut.qsfp_1_rx_rst_2 <= 1 - self.dut.qsfp_1_tx_rst_2 <= 1 - self.dut.qsfp_1_rx_rst_3 <= 1 - self.dut.qsfp_1_tx_rst_3 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp_0_rx_rst_0.value = 1 + self.dut.qsfp_0_tx_rst_0.value = 1 + self.dut.qsfp_0_rx_rst_1.value = 1 + self.dut.qsfp_0_tx_rst_1.value = 1 + self.dut.qsfp_0_rx_rst_2.value = 1 + self.dut.qsfp_0_tx_rst_2.value = 1 + self.dut.qsfp_0_rx_rst_3.value = 1 + self.dut.qsfp_0_tx_rst_3.value = 1 + self.dut.qsfp_1_rx_rst_0.value = 1 + self.dut.qsfp_1_tx_rst_0.value = 1 + self.dut.qsfp_1_rx_rst_1.value = 1 + self.dut.qsfp_1_tx_rst_1.value = 1 + self.dut.qsfp_1_rx_rst_2.value = 1 + self.dut.qsfp_1_tx_rst_2.value = 1 + self.dut.qsfp_1_rx_rst_3.value = 1 + self.dut.qsfp_1_tx_rst_3.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp_0_rx_rst_0 <= 0 - self.dut.qsfp_0_tx_rst_0 <= 0 - self.dut.qsfp_0_rx_rst_1 <= 0 - self.dut.qsfp_0_tx_rst_1 <= 0 - self.dut.qsfp_0_rx_rst_2 <= 0 - self.dut.qsfp_0_tx_rst_2 <= 0 - self.dut.qsfp_0_rx_rst_3 <= 0 - self.dut.qsfp_0_tx_rst_3 <= 0 - self.dut.qsfp_1_rx_rst_0 <= 0 - self.dut.qsfp_1_tx_rst_0 <= 0 - self.dut.qsfp_1_rx_rst_1 <= 0 - self.dut.qsfp_1_tx_rst_1 <= 0 - self.dut.qsfp_1_rx_rst_2 <= 0 - self.dut.qsfp_1_tx_rst_2 <= 0 - self.dut.qsfp_1_rx_rst_3 <= 0 - self.dut.qsfp_1_tx_rst_3 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp_0_rx_rst_0.value = 0 + self.dut.qsfp_0_tx_rst_0.value = 0 + self.dut.qsfp_0_rx_rst_1.value = 0 + self.dut.qsfp_0_tx_rst_1.value = 0 + self.dut.qsfp_0_rx_rst_2.value = 0 + self.dut.qsfp_0_tx_rst_2.value = 0 + self.dut.qsfp_0_rx_rst_3.value = 0 + self.dut.qsfp_0_tx_rst_3.value = 0 + self.dut.qsfp_1_rx_rst_0.value = 0 + self.dut.qsfp_1_tx_rst_0.value = 0 + self.dut.qsfp_1_rx_rst_1.value = 0 + self.dut.qsfp_1_tx_rst_1.value = 0 + self.dut.qsfp_1_rx_rst_2.value = 0 + self.dut.qsfp_1_tx_rst_2.value = 0 + self.dut.qsfp_1_rx_rst_3.value = 0 + self.dut.qsfp_1_tx_rst_3.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/test_fpga_core.py index 47913a947..4dcffe3f7 100644 --- a/fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/test_fpga_core.py @@ -66,12 +66,12 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py index 37a47626b..6f609015c 100644 --- a/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -113,44 +113,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp0_rx_rst_1 <= 1 - self.dut.qsfp0_tx_rst_1 <= 1 - self.dut.qsfp0_rx_rst_2 <= 1 - self.dut.qsfp0_tx_rst_2 <= 1 - self.dut.qsfp0_rx_rst_3 <= 1 - self.dut.qsfp0_tx_rst_3 <= 1 - self.dut.qsfp0_rx_rst_4 <= 1 - self.dut.qsfp0_tx_rst_4 <= 1 - self.dut.qsfp1_rx_rst_1 <= 1 - self.dut.qsfp1_tx_rst_1 <= 1 - self.dut.qsfp1_rx_rst_2 <= 1 - self.dut.qsfp1_tx_rst_2 <= 1 - self.dut.qsfp1_rx_rst_3 <= 1 - self.dut.qsfp1_tx_rst_3 <= 1 - self.dut.qsfp1_rx_rst_4 <= 1 - self.dut.qsfp1_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp0_rx_rst_1.value = 1 + self.dut.qsfp0_tx_rst_1.value = 1 + self.dut.qsfp0_rx_rst_2.value = 1 + self.dut.qsfp0_tx_rst_2.value = 1 + self.dut.qsfp0_rx_rst_3.value = 1 + self.dut.qsfp0_tx_rst_3.value = 1 + self.dut.qsfp0_rx_rst_4.value = 1 + self.dut.qsfp0_tx_rst_4.value = 1 + self.dut.qsfp1_rx_rst_1.value = 1 + self.dut.qsfp1_tx_rst_1.value = 1 + self.dut.qsfp1_rx_rst_2.value = 1 + self.dut.qsfp1_tx_rst_2.value = 1 + self.dut.qsfp1_rx_rst_3.value = 1 + self.dut.qsfp1_tx_rst_3.value = 1 + self.dut.qsfp1_rx_rst_4.value = 1 + self.dut.qsfp1_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp0_rx_rst_1 <= 0 - self.dut.qsfp0_tx_rst_1 <= 0 - self.dut.qsfp0_rx_rst_2 <= 0 - self.dut.qsfp0_tx_rst_2 <= 0 - self.dut.qsfp0_rx_rst_3 <= 0 - self.dut.qsfp0_tx_rst_3 <= 0 - self.dut.qsfp0_rx_rst_4 <= 0 - self.dut.qsfp0_tx_rst_4 <= 0 - self.dut.qsfp1_rx_rst_1 <= 0 - self.dut.qsfp1_tx_rst_1 <= 0 - self.dut.qsfp1_rx_rst_2 <= 0 - self.dut.qsfp1_tx_rst_2 <= 0 - self.dut.qsfp1_rx_rst_3 <= 0 - self.dut.qsfp1_tx_rst_3 <= 0 - self.dut.qsfp1_rx_rst_4 <= 0 - self.dut.qsfp1_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp0_rx_rst_1.value = 0 + self.dut.qsfp0_tx_rst_1.value = 0 + self.dut.qsfp0_rx_rst_2.value = 0 + self.dut.qsfp0_tx_rst_2.value = 0 + self.dut.qsfp0_rx_rst_3.value = 0 + self.dut.qsfp0_tx_rst_3.value = 0 + self.dut.qsfp0_rx_rst_4.value = 0 + self.dut.qsfp0_tx_rst_4.value = 0 + self.dut.qsfp1_rx_rst_1.value = 0 + self.dut.qsfp1_tx_rst_1.value = 0 + self.dut.qsfp1_rx_rst_2.value = 0 + self.dut.qsfp1_tx_rst_2.value = 0 + self.dut.qsfp1_rx_rst_3.value = 0 + self.dut.qsfp1_tx_rst_3.value = 0 + self.dut.qsfp1_rx_rst_4.value = 0 + self.dut.qsfp1_tx_rst_4.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py index 37a47626b..6f609015c 100644 --- a/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -113,44 +113,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp0_rx_rst_1 <= 1 - self.dut.qsfp0_tx_rst_1 <= 1 - self.dut.qsfp0_rx_rst_2 <= 1 - self.dut.qsfp0_tx_rst_2 <= 1 - self.dut.qsfp0_rx_rst_3 <= 1 - self.dut.qsfp0_tx_rst_3 <= 1 - self.dut.qsfp0_rx_rst_4 <= 1 - self.dut.qsfp0_tx_rst_4 <= 1 - self.dut.qsfp1_rx_rst_1 <= 1 - self.dut.qsfp1_tx_rst_1 <= 1 - self.dut.qsfp1_rx_rst_2 <= 1 - self.dut.qsfp1_tx_rst_2 <= 1 - self.dut.qsfp1_rx_rst_3 <= 1 - self.dut.qsfp1_tx_rst_3 <= 1 - self.dut.qsfp1_rx_rst_4 <= 1 - self.dut.qsfp1_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp0_rx_rst_1.value = 1 + self.dut.qsfp0_tx_rst_1.value = 1 + self.dut.qsfp0_rx_rst_2.value = 1 + self.dut.qsfp0_tx_rst_2.value = 1 + self.dut.qsfp0_rx_rst_3.value = 1 + self.dut.qsfp0_tx_rst_3.value = 1 + self.dut.qsfp0_rx_rst_4.value = 1 + self.dut.qsfp0_tx_rst_4.value = 1 + self.dut.qsfp1_rx_rst_1.value = 1 + self.dut.qsfp1_tx_rst_1.value = 1 + self.dut.qsfp1_rx_rst_2.value = 1 + self.dut.qsfp1_tx_rst_2.value = 1 + self.dut.qsfp1_rx_rst_3.value = 1 + self.dut.qsfp1_tx_rst_3.value = 1 + self.dut.qsfp1_rx_rst_4.value = 1 + self.dut.qsfp1_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp0_rx_rst_1 <= 0 - self.dut.qsfp0_tx_rst_1 <= 0 - self.dut.qsfp0_rx_rst_2 <= 0 - self.dut.qsfp0_tx_rst_2 <= 0 - self.dut.qsfp0_rx_rst_3 <= 0 - self.dut.qsfp0_tx_rst_3 <= 0 - self.dut.qsfp0_rx_rst_4 <= 0 - self.dut.qsfp0_tx_rst_4 <= 0 - self.dut.qsfp1_rx_rst_1 <= 0 - self.dut.qsfp1_tx_rst_1 <= 0 - self.dut.qsfp1_rx_rst_2 <= 0 - self.dut.qsfp1_tx_rst_2 <= 0 - self.dut.qsfp1_rx_rst_3 <= 0 - self.dut.qsfp1_tx_rst_3 <= 0 - self.dut.qsfp1_rx_rst_4 <= 0 - self.dut.qsfp1_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp0_rx_rst_1.value = 0 + self.dut.qsfp0_tx_rst_1.value = 0 + self.dut.qsfp0_rx_rst_2.value = 0 + self.dut.qsfp0_tx_rst_2.value = 0 + self.dut.qsfp0_rx_rst_3.value = 0 + self.dut.qsfp0_tx_rst_3.value = 0 + self.dut.qsfp0_rx_rst_4.value = 0 + self.dut.qsfp0_tx_rst_4.value = 0 + self.dut.qsfp1_rx_rst_1.value = 0 + self.dut.qsfp1_tx_rst_1.value = 0 + self.dut.qsfp1_rx_rst_2.value = 0 + self.dut.qsfp1_tx_rst_2.value = 0 + self.dut.qsfp1_rx_rst_3.value = 0 + self.dut.qsfp1_tx_rst_3.value = 0 + self.dut.qsfp1_rx_rst_4.value = 0 + self.dut.qsfp1_tx_rst_4.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py index e989629b2..3884d768e 100644 --- a/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -111,44 +111,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp0_rx_rst_1 <= 1 - self.dut.qsfp0_tx_rst_1 <= 1 - self.dut.qsfp0_rx_rst_2 <= 1 - self.dut.qsfp0_tx_rst_2 <= 1 - self.dut.qsfp0_rx_rst_3 <= 1 - self.dut.qsfp0_tx_rst_3 <= 1 - self.dut.qsfp0_rx_rst_4 <= 1 - self.dut.qsfp0_tx_rst_4 <= 1 - self.dut.qsfp1_rx_rst_1 <= 1 - self.dut.qsfp1_tx_rst_1 <= 1 - self.dut.qsfp1_rx_rst_2 <= 1 - self.dut.qsfp1_tx_rst_2 <= 1 - self.dut.qsfp1_rx_rst_3 <= 1 - self.dut.qsfp1_tx_rst_3 <= 1 - self.dut.qsfp1_rx_rst_4 <= 1 - self.dut.qsfp1_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp0_rx_rst_1.value = 1 + self.dut.qsfp0_tx_rst_1.value = 1 + self.dut.qsfp0_rx_rst_2.value = 1 + self.dut.qsfp0_tx_rst_2.value = 1 + self.dut.qsfp0_rx_rst_3.value = 1 + self.dut.qsfp0_tx_rst_3.value = 1 + self.dut.qsfp0_rx_rst_4.value = 1 + self.dut.qsfp0_tx_rst_4.value = 1 + self.dut.qsfp1_rx_rst_1.value = 1 + self.dut.qsfp1_tx_rst_1.value = 1 + self.dut.qsfp1_rx_rst_2.value = 1 + self.dut.qsfp1_tx_rst_2.value = 1 + self.dut.qsfp1_rx_rst_3.value = 1 + self.dut.qsfp1_tx_rst_3.value = 1 + self.dut.qsfp1_rx_rst_4.value = 1 + self.dut.qsfp1_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp0_rx_rst_1 <= 0 - self.dut.qsfp0_tx_rst_1 <= 0 - self.dut.qsfp0_rx_rst_2 <= 0 - self.dut.qsfp0_tx_rst_2 <= 0 - self.dut.qsfp0_rx_rst_3 <= 0 - self.dut.qsfp0_tx_rst_3 <= 0 - self.dut.qsfp0_rx_rst_4 <= 0 - self.dut.qsfp0_tx_rst_4 <= 0 - self.dut.qsfp1_rx_rst_1 <= 0 - self.dut.qsfp1_tx_rst_1 <= 0 - self.dut.qsfp1_rx_rst_2 <= 0 - self.dut.qsfp1_tx_rst_2 <= 0 - self.dut.qsfp1_rx_rst_3 <= 0 - self.dut.qsfp1_tx_rst_3 <= 0 - self.dut.qsfp1_rx_rst_4 <= 0 - self.dut.qsfp1_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp0_rx_rst_1.value = 0 + self.dut.qsfp0_tx_rst_1.value = 0 + self.dut.qsfp0_rx_rst_2.value = 0 + self.dut.qsfp0_tx_rst_2.value = 0 + self.dut.qsfp0_rx_rst_3.value = 0 + self.dut.qsfp0_tx_rst_3.value = 0 + self.dut.qsfp0_rx_rst_4.value = 0 + self.dut.qsfp0_tx_rst_4.value = 0 + self.dut.qsfp1_rx_rst_1.value = 0 + self.dut.qsfp1_tx_rst_1.value = 0 + self.dut.qsfp1_rx_rst_2.value = 0 + self.dut.qsfp1_tx_rst_2.value = 0 + self.dut.qsfp1_rx_rst_3.value = 0 + self.dut.qsfp1_tx_rst_3.value = 0 + self.dut.qsfp1_rx_rst_4.value = 0 + self.dut.qsfp1_tx_rst_4.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py index 8921956ea..95d86a84c 100644 --- a/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -83,28 +83,28 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst.setimmediatevalue(1) - self.dut.qsfp_rx_rst_1 <= 1 - self.dut.qsfp_tx_rst_1 <= 1 - self.dut.qsfp_rx_rst_2 <= 1 - self.dut.qsfp_tx_rst_2 <= 1 - self.dut.qsfp_rx_rst_3 <= 1 - self.dut.qsfp_tx_rst_3 <= 1 - self.dut.qsfp_rx_rst_4 <= 1 - self.dut.qsfp_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp_rx_rst_1.value = 1 + self.dut.qsfp_tx_rst_1.value = 1 + self.dut.qsfp_rx_rst_2.value = 1 + self.dut.qsfp_tx_rst_2.value = 1 + self.dut.qsfp_rx_rst_3.value = 1 + self.dut.qsfp_tx_rst_3.value = 1 + self.dut.qsfp_rx_rst_4.value = 1 + self.dut.qsfp_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp_rx_rst_1 <= 0 - self.dut.qsfp_tx_rst_1 <= 0 - self.dut.qsfp_rx_rst_2 <= 0 - self.dut.qsfp_tx_rst_2 <= 0 - self.dut.qsfp_rx_rst_3 <= 0 - self.dut.qsfp_tx_rst_3 <= 0 - self.dut.qsfp_rx_rst_4 <= 0 - self.dut.qsfp_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp_rx_rst_1.value = 0 + self.dut.qsfp_tx_rst_1.value = 0 + self.dut.qsfp_rx_rst_2.value = 0 + self.dut.qsfp_tx_rst_2.value = 0 + self.dut.qsfp_rx_rst_3.value = 0 + self.dut.qsfp_tx_rst_3.value = 0 + self.dut.qsfp_rx_rst_4.value = 0 + self.dut.qsfp_tx_rst_4.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py index f4a58a58d..34d8ba613 100644 --- a/fpga/lib/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py @@ -64,12 +64,12 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/test_fpga_core.py index 331c63817..40558f75a 100644 --- a/fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/test_fpga_core.py @@ -64,23 +64,23 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 async def _run_clk(self): t = Timer(2, 'ns') while True: - self.dut.clk <= 1 + self.dut.clk.value = 1 await t - self.dut.clk90 <= 1 + self.dut.clk90.value = 1 await t - self.dut.clk <= 0 + self.dut.clk.value = 0 await t - self.dut.clk90 <= 0 + self.dut.clk90.value = 0 await t diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/test_fpga_core.py index c24ab12e1..f2a2f5dfb 100644 --- a/fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/test_fpga_core.py @@ -68,23 +68,23 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 async def _run_clk(self): t = Timer(2, 'ns') while True: - self.dut.clk <= 1 + self.dut.clk.value = 1 await t - self.dut.clk90 <= 1 + self.dut.clk90.value = 1 await t - self.dut.clk <= 0 + self.dut.clk.value = 0 await t - self.dut.clk90 <= 0 + self.dut.clk90.value = 0 await t diff --git a/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py index 89c239e2c..95b1238af 100644 --- a/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py @@ -70,12 +70,12 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py index 9907cad0b..d4370edac 100644 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py @@ -69,20 +69,20 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.sfp_1_rx_rst <= 1 - self.dut.sfp_1_tx_rst <= 1 - self.dut.sfp_2_rx_rst <= 1 - self.dut.sfp_2_tx_rst <= 1 + self.dut.rst.value = 1 + self.dut.sfp_1_rx_rst.value = 1 + self.dut.sfp_1_tx_rst.value = 1 + self.dut.sfp_2_rx_rst.value = 1 + self.dut.sfp_2_tx_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.sfp_1_rx_rst <= 0 - self.dut.sfp_1_tx_rst <= 0 - self.dut.sfp_2_rx_rst <= 0 - self.dut.sfp_2_tx_rst <= 0 + self.dut.rst.value = 0 + self.dut.sfp_1_rx_rst.value = 0 + self.dut.sfp_1_tx_rst.value = 0 + self.dut.sfp_2_rx_rst.value = 0 + self.dut.sfp_2_tx_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py index 9907cad0b..d4370edac 100644 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -69,20 +69,20 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.sfp_1_rx_rst <= 1 - self.dut.sfp_1_tx_rst <= 1 - self.dut.sfp_2_rx_rst <= 1 - self.dut.sfp_2_tx_rst <= 1 + self.dut.rst.value = 1 + self.dut.sfp_1_rx_rst.value = 1 + self.dut.sfp_1_tx_rst.value = 1 + self.dut.sfp_2_rx_rst.value = 1 + self.dut.sfp_2_tx_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.sfp_1_rx_rst <= 0 - self.dut.sfp_1_tx_rst <= 0 - self.dut.sfp_2_rx_rst <= 0 - self.dut.sfp_2_tx_rst <= 0 + self.dut.rst.value = 0 + self.dut.sfp_1_rx_rst.value = 0 + self.dut.sfp_1_tx_rst.value = 0 + self.dut.sfp_2_rx_rst.value = 0 + self.dut.sfp_2_tx_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py index e1eb8dea9..0a109c8be 100644 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -313,156 +313,156 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp_1_rx_rst_1 <= 1 - self.dut.qsfp_1_tx_rst_1 <= 1 - self.dut.qsfp_1_rx_rst_2 <= 1 - self.dut.qsfp_1_tx_rst_2 <= 1 - self.dut.qsfp_1_rx_rst_3 <= 1 - self.dut.qsfp_1_tx_rst_3 <= 1 - self.dut.qsfp_1_rx_rst_4 <= 1 - self.dut.qsfp_1_tx_rst_4 <= 1 - self.dut.qsfp_2_rx_rst_1 <= 1 - self.dut.qsfp_2_tx_rst_1 <= 1 - self.dut.qsfp_2_rx_rst_2 <= 1 - self.dut.qsfp_2_tx_rst_2 <= 1 - self.dut.qsfp_2_rx_rst_3 <= 1 - self.dut.qsfp_2_tx_rst_3 <= 1 - self.dut.qsfp_2_rx_rst_4 <= 1 - self.dut.qsfp_2_tx_rst_4 <= 1 - self.dut.qsfp_3_rx_rst_1 <= 1 - self.dut.qsfp_3_tx_rst_1 <= 1 - self.dut.qsfp_3_rx_rst_2 <= 1 - self.dut.qsfp_3_tx_rst_2 <= 1 - self.dut.qsfp_3_rx_rst_3 <= 1 - self.dut.qsfp_3_tx_rst_3 <= 1 - self.dut.qsfp_3_rx_rst_4 <= 1 - self.dut.qsfp_3_tx_rst_4 <= 1 - self.dut.qsfp_4_rx_rst_1 <= 1 - self.dut.qsfp_4_tx_rst_1 <= 1 - self.dut.qsfp_4_rx_rst_2 <= 1 - self.dut.qsfp_4_tx_rst_2 <= 1 - self.dut.qsfp_4_rx_rst_3 <= 1 - self.dut.qsfp_4_tx_rst_3 <= 1 - self.dut.qsfp_4_rx_rst_4 <= 1 - self.dut.qsfp_4_tx_rst_4 <= 1 - self.dut.qsfp_5_rx_rst_1 <= 1 - self.dut.qsfp_5_tx_rst_1 <= 1 - self.dut.qsfp_5_rx_rst_2 <= 1 - self.dut.qsfp_5_tx_rst_2 <= 1 - self.dut.qsfp_5_rx_rst_3 <= 1 - self.dut.qsfp_5_tx_rst_3 <= 1 - self.dut.qsfp_5_rx_rst_4 <= 1 - self.dut.qsfp_5_tx_rst_4 <= 1 - self.dut.qsfp_6_rx_rst_1 <= 1 - self.dut.qsfp_6_tx_rst_1 <= 1 - self.dut.qsfp_6_rx_rst_2 <= 1 - self.dut.qsfp_6_tx_rst_2 <= 1 - self.dut.qsfp_6_rx_rst_3 <= 1 - self.dut.qsfp_6_tx_rst_3 <= 1 - self.dut.qsfp_6_rx_rst_4 <= 1 - self.dut.qsfp_6_tx_rst_4 <= 1 - self.dut.qsfp_7_rx_rst_1 <= 1 - self.dut.qsfp_7_tx_rst_1 <= 1 - self.dut.qsfp_7_rx_rst_2 <= 1 - self.dut.qsfp_7_tx_rst_2 <= 1 - self.dut.qsfp_7_rx_rst_3 <= 1 - self.dut.qsfp_7_tx_rst_3 <= 1 - self.dut.qsfp_7_rx_rst_4 <= 1 - self.dut.qsfp_7_tx_rst_4 <= 1 - self.dut.qsfp_8_rx_rst_1 <= 1 - self.dut.qsfp_8_tx_rst_1 <= 1 - self.dut.qsfp_8_rx_rst_2 <= 1 - self.dut.qsfp_8_tx_rst_2 <= 1 - self.dut.qsfp_8_rx_rst_3 <= 1 - self.dut.qsfp_8_tx_rst_3 <= 1 - self.dut.qsfp_8_rx_rst_4 <= 1 - self.dut.qsfp_8_tx_rst_4 <= 1 - self.dut.qsfp_9_rx_rst_1 <= 1 - self.dut.qsfp_9_tx_rst_1 <= 1 - self.dut.qsfp_9_rx_rst_2 <= 1 - self.dut.qsfp_9_tx_rst_2 <= 1 - self.dut.qsfp_9_rx_rst_3 <= 1 - self.dut.qsfp_9_tx_rst_3 <= 1 - self.dut.qsfp_9_rx_rst_4 <= 1 - self.dut.qsfp_9_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp_1_rx_rst_1.value = 1 + self.dut.qsfp_1_tx_rst_1.value = 1 + self.dut.qsfp_1_rx_rst_2.value = 1 + self.dut.qsfp_1_tx_rst_2.value = 1 + self.dut.qsfp_1_rx_rst_3.value = 1 + self.dut.qsfp_1_tx_rst_3.value = 1 + self.dut.qsfp_1_rx_rst_4.value = 1 + self.dut.qsfp_1_tx_rst_4.value = 1 + self.dut.qsfp_2_rx_rst_1.value = 1 + self.dut.qsfp_2_tx_rst_1.value = 1 + self.dut.qsfp_2_rx_rst_2.value = 1 + self.dut.qsfp_2_tx_rst_2.value = 1 + self.dut.qsfp_2_rx_rst_3.value = 1 + self.dut.qsfp_2_tx_rst_3.value = 1 + self.dut.qsfp_2_rx_rst_4.value = 1 + self.dut.qsfp_2_tx_rst_4.value = 1 + self.dut.qsfp_3_rx_rst_1.value = 1 + self.dut.qsfp_3_tx_rst_1.value = 1 + self.dut.qsfp_3_rx_rst_2.value = 1 + self.dut.qsfp_3_tx_rst_2.value = 1 + self.dut.qsfp_3_rx_rst_3.value = 1 + self.dut.qsfp_3_tx_rst_3.value = 1 + self.dut.qsfp_3_rx_rst_4.value = 1 + self.dut.qsfp_3_tx_rst_4.value = 1 + self.dut.qsfp_4_rx_rst_1.value = 1 + self.dut.qsfp_4_tx_rst_1.value = 1 + self.dut.qsfp_4_rx_rst_2.value = 1 + self.dut.qsfp_4_tx_rst_2.value = 1 + self.dut.qsfp_4_rx_rst_3.value = 1 + self.dut.qsfp_4_tx_rst_3.value = 1 + self.dut.qsfp_4_rx_rst_4.value = 1 + self.dut.qsfp_4_tx_rst_4.value = 1 + self.dut.qsfp_5_rx_rst_1.value = 1 + self.dut.qsfp_5_tx_rst_1.value = 1 + self.dut.qsfp_5_rx_rst_2.value = 1 + self.dut.qsfp_5_tx_rst_2.value = 1 + self.dut.qsfp_5_rx_rst_3.value = 1 + self.dut.qsfp_5_tx_rst_3.value = 1 + self.dut.qsfp_5_rx_rst_4.value = 1 + self.dut.qsfp_5_tx_rst_4.value = 1 + self.dut.qsfp_6_rx_rst_1.value = 1 + self.dut.qsfp_6_tx_rst_1.value = 1 + self.dut.qsfp_6_rx_rst_2.value = 1 + self.dut.qsfp_6_tx_rst_2.value = 1 + self.dut.qsfp_6_rx_rst_3.value = 1 + self.dut.qsfp_6_tx_rst_3.value = 1 + self.dut.qsfp_6_rx_rst_4.value = 1 + self.dut.qsfp_6_tx_rst_4.value = 1 + self.dut.qsfp_7_rx_rst_1.value = 1 + self.dut.qsfp_7_tx_rst_1.value = 1 + self.dut.qsfp_7_rx_rst_2.value = 1 + self.dut.qsfp_7_tx_rst_2.value = 1 + self.dut.qsfp_7_rx_rst_3.value = 1 + self.dut.qsfp_7_tx_rst_3.value = 1 + self.dut.qsfp_7_rx_rst_4.value = 1 + self.dut.qsfp_7_tx_rst_4.value = 1 + self.dut.qsfp_8_rx_rst_1.value = 1 + self.dut.qsfp_8_tx_rst_1.value = 1 + self.dut.qsfp_8_rx_rst_2.value = 1 + self.dut.qsfp_8_tx_rst_2.value = 1 + self.dut.qsfp_8_rx_rst_3.value = 1 + self.dut.qsfp_8_tx_rst_3.value = 1 + self.dut.qsfp_8_rx_rst_4.value = 1 + self.dut.qsfp_8_tx_rst_4.value = 1 + self.dut.qsfp_9_rx_rst_1.value = 1 + self.dut.qsfp_9_tx_rst_1.value = 1 + self.dut.qsfp_9_rx_rst_2.value = 1 + self.dut.qsfp_9_tx_rst_2.value = 1 + self.dut.qsfp_9_rx_rst_3.value = 1 + self.dut.qsfp_9_tx_rst_3.value = 1 + self.dut.qsfp_9_rx_rst_4.value = 1 + self.dut.qsfp_9_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp_1_rx_rst_1 <= 0 - self.dut.qsfp_1_tx_rst_1 <= 0 - self.dut.qsfp_1_rx_rst_2 <= 0 - self.dut.qsfp_1_tx_rst_2 <= 0 - self.dut.qsfp_1_rx_rst_3 <= 0 - self.dut.qsfp_1_tx_rst_3 <= 0 - self.dut.qsfp_1_rx_rst_4 <= 0 - self.dut.qsfp_1_tx_rst_4 <= 0 - self.dut.qsfp_2_rx_rst_1 <= 0 - self.dut.qsfp_2_tx_rst_1 <= 0 - self.dut.qsfp_2_rx_rst_2 <= 0 - self.dut.qsfp_2_tx_rst_2 <= 0 - self.dut.qsfp_2_rx_rst_3 <= 0 - self.dut.qsfp_2_tx_rst_3 <= 0 - self.dut.qsfp_2_rx_rst_4 <= 0 - self.dut.qsfp_2_tx_rst_4 <= 0 - self.dut.qsfp_3_rx_rst_1 <= 0 - self.dut.qsfp_3_tx_rst_1 <= 0 - self.dut.qsfp_3_rx_rst_2 <= 0 - self.dut.qsfp_3_tx_rst_2 <= 0 - self.dut.qsfp_3_rx_rst_3 <= 0 - self.dut.qsfp_3_tx_rst_3 <= 0 - self.dut.qsfp_3_rx_rst_4 <= 0 - self.dut.qsfp_3_tx_rst_4 <= 0 - self.dut.qsfp_4_rx_rst_1 <= 0 - self.dut.qsfp_4_tx_rst_1 <= 0 - self.dut.qsfp_4_rx_rst_2 <= 0 - self.dut.qsfp_4_tx_rst_2 <= 0 - self.dut.qsfp_4_rx_rst_3 <= 0 - self.dut.qsfp_4_tx_rst_3 <= 0 - self.dut.qsfp_4_rx_rst_4 <= 0 - self.dut.qsfp_4_tx_rst_4 <= 0 - self.dut.qsfp_5_rx_rst_1 <= 0 - self.dut.qsfp_5_tx_rst_1 <= 0 - self.dut.qsfp_5_rx_rst_2 <= 0 - self.dut.qsfp_5_tx_rst_2 <= 0 - self.dut.qsfp_5_rx_rst_3 <= 0 - self.dut.qsfp_5_tx_rst_3 <= 0 - self.dut.qsfp_5_rx_rst_4 <= 0 - self.dut.qsfp_5_tx_rst_4 <= 0 - self.dut.qsfp_6_rx_rst_1 <= 0 - self.dut.qsfp_6_tx_rst_1 <= 0 - self.dut.qsfp_6_rx_rst_2 <= 0 - self.dut.qsfp_6_tx_rst_2 <= 0 - self.dut.qsfp_6_rx_rst_3 <= 0 - self.dut.qsfp_6_tx_rst_3 <= 0 - self.dut.qsfp_6_rx_rst_4 <= 0 - self.dut.qsfp_6_tx_rst_4 <= 0 - self.dut.qsfp_7_rx_rst_1 <= 0 - self.dut.qsfp_7_tx_rst_1 <= 0 - self.dut.qsfp_7_rx_rst_2 <= 0 - self.dut.qsfp_7_tx_rst_2 <= 0 - self.dut.qsfp_7_rx_rst_3 <= 0 - self.dut.qsfp_7_tx_rst_3 <= 0 - self.dut.qsfp_7_rx_rst_4 <= 0 - self.dut.qsfp_7_tx_rst_4 <= 0 - self.dut.qsfp_8_rx_rst_1 <= 0 - self.dut.qsfp_8_tx_rst_1 <= 0 - self.dut.qsfp_8_rx_rst_2 <= 0 - self.dut.qsfp_8_tx_rst_2 <= 0 - self.dut.qsfp_8_rx_rst_3 <= 0 - self.dut.qsfp_8_tx_rst_3 <= 0 - self.dut.qsfp_8_rx_rst_4 <= 0 - self.dut.qsfp_8_tx_rst_4 <= 0 - self.dut.qsfp_9_rx_rst_1 <= 0 - self.dut.qsfp_9_tx_rst_1 <= 0 - self.dut.qsfp_9_rx_rst_2 <= 0 - self.dut.qsfp_9_tx_rst_2 <= 0 - self.dut.qsfp_9_rx_rst_3 <= 0 - self.dut.qsfp_9_tx_rst_3 <= 0 - self.dut.qsfp_9_rx_rst_4 <= 0 - self.dut.qsfp_9_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp_1_rx_rst_1.value = 0 + self.dut.qsfp_1_tx_rst_1.value = 0 + self.dut.qsfp_1_rx_rst_2.value = 0 + self.dut.qsfp_1_tx_rst_2.value = 0 + self.dut.qsfp_1_rx_rst_3.value = 0 + self.dut.qsfp_1_tx_rst_3.value = 0 + self.dut.qsfp_1_rx_rst_4.value = 0 + self.dut.qsfp_1_tx_rst_4.value = 0 + self.dut.qsfp_2_rx_rst_1.value = 0 + self.dut.qsfp_2_tx_rst_1.value = 0 + self.dut.qsfp_2_rx_rst_2.value = 0 + self.dut.qsfp_2_tx_rst_2.value = 0 + self.dut.qsfp_2_rx_rst_3.value = 0 + self.dut.qsfp_2_tx_rst_3.value = 0 + self.dut.qsfp_2_rx_rst_4.value = 0 + self.dut.qsfp_2_tx_rst_4.value = 0 + self.dut.qsfp_3_rx_rst_1.value = 0 + self.dut.qsfp_3_tx_rst_1.value = 0 + self.dut.qsfp_3_rx_rst_2.value = 0 + self.dut.qsfp_3_tx_rst_2.value = 0 + self.dut.qsfp_3_rx_rst_3.value = 0 + self.dut.qsfp_3_tx_rst_3.value = 0 + self.dut.qsfp_3_rx_rst_4.value = 0 + self.dut.qsfp_3_tx_rst_4.value = 0 + self.dut.qsfp_4_rx_rst_1.value = 0 + self.dut.qsfp_4_tx_rst_1.value = 0 + self.dut.qsfp_4_rx_rst_2.value = 0 + self.dut.qsfp_4_tx_rst_2.value = 0 + self.dut.qsfp_4_rx_rst_3.value = 0 + self.dut.qsfp_4_tx_rst_3.value = 0 + self.dut.qsfp_4_rx_rst_4.value = 0 + self.dut.qsfp_4_tx_rst_4.value = 0 + self.dut.qsfp_5_rx_rst_1.value = 0 + self.dut.qsfp_5_tx_rst_1.value = 0 + self.dut.qsfp_5_rx_rst_2.value = 0 + self.dut.qsfp_5_tx_rst_2.value = 0 + self.dut.qsfp_5_rx_rst_3.value = 0 + self.dut.qsfp_5_tx_rst_3.value = 0 + self.dut.qsfp_5_rx_rst_4.value = 0 + self.dut.qsfp_5_tx_rst_4.value = 0 + self.dut.qsfp_6_rx_rst_1.value = 0 + self.dut.qsfp_6_tx_rst_1.value = 0 + self.dut.qsfp_6_rx_rst_2.value = 0 + self.dut.qsfp_6_tx_rst_2.value = 0 + self.dut.qsfp_6_rx_rst_3.value = 0 + self.dut.qsfp_6_tx_rst_3.value = 0 + self.dut.qsfp_6_rx_rst_4.value = 0 + self.dut.qsfp_6_tx_rst_4.value = 0 + self.dut.qsfp_7_rx_rst_1.value = 0 + self.dut.qsfp_7_tx_rst_1.value = 0 + self.dut.qsfp_7_rx_rst_2.value = 0 + self.dut.qsfp_7_tx_rst_2.value = 0 + self.dut.qsfp_7_rx_rst_3.value = 0 + self.dut.qsfp_7_tx_rst_3.value = 0 + self.dut.qsfp_7_rx_rst_4.value = 0 + self.dut.qsfp_7_tx_rst_4.value = 0 + self.dut.qsfp_8_rx_rst_1.value = 0 + self.dut.qsfp_8_tx_rst_1.value = 0 + self.dut.qsfp_8_rx_rst_2.value = 0 + self.dut.qsfp_8_tx_rst_2.value = 0 + self.dut.qsfp_8_rx_rst_3.value = 0 + self.dut.qsfp_8_tx_rst_3.value = 0 + self.dut.qsfp_8_rx_rst_4.value = 0 + self.dut.qsfp_8_tx_rst_4.value = 0 + self.dut.qsfp_9_rx_rst_1.value = 0 + self.dut.qsfp_9_tx_rst_1.value = 0 + self.dut.qsfp_9_rx_rst_2.value = 0 + self.dut.qsfp_9_tx_rst_2.value = 0 + self.dut.qsfp_9_rx_rst_3.value = 0 + self.dut.qsfp_9_tx_rst_3.value = 0 + self.dut.qsfp_9_rx_rst_4.value = 0 + self.dut.qsfp_9_tx_rst_4.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py index 7116db21e..a4698680d 100644 --- a/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py @@ -136,12 +136,12 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py index 0460b5326..7f3e94ed8 100644 --- a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py @@ -135,12 +135,12 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/test_fpga_core.py index f324b2205..589e2c8a5 100644 --- a/fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/test_fpga_core.py @@ -67,12 +67,12 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/test_fpga_core.py index c66d04590..e2a4b09f6 100644 --- a/fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/test_fpga_core.py @@ -68,23 +68,23 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 async def _run_clk(self): t = Timer(2, 'ns') while True: - self.dut.clk <= 1 + self.dut.clk.value = 1 await t - self.dut.clk90 <= 1 + self.dut.clk90.value = 1 await t - self.dut.clk <= 0 + self.dut.clk.value = 0 await t - self.dut.clk90 <= 0 + self.dut.clk90.value = 0 await t diff --git a/fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/test_fpga_core.py index 6a4cf4c28..318f92fe8 100644 --- a/fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/test_fpga_core.py @@ -72,14 +72,14 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.phy_gmii_rst <= 1 + self.dut.rst.value = 1 + self.dut.phy_gmii_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.phy_gmii_rst <= 0 + self.dut.rst.value = 0 + self.dut.phy_gmii_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/test_fpga_core.py index a37da8504..733a7f3c0 100644 --- a/fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/test_fpga_core.py @@ -67,12 +67,12 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk_125mhz) - self.dut.rst_125mhz <= 1 + self.dut.rst_125mhz.value = 1 for k in range(10): await RisingEdge(self.dut.clk_125mhz) - self.dut.rst_125mhz <= 0 + self.dut.rst_125mhz.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/test_fpga_core.py index bdab9452e..c9125bdc2 100644 --- a/fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/test_fpga_core.py @@ -68,23 +68,23 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk_125mhz) - self.dut.rst_125mhz <= 1 + self.dut.rst_125mhz.value = 1 for k in range(10): await RisingEdge(self.dut.clk_125mhz) - self.dut.rst_125mhz <= 0 + self.dut.rst_125mhz.value = 0 async def _run_clk_125mhz(self): t = Timer(2, 'ns') while True: - self.dut.clk_125mhz <= 1 + self.dut.clk_125mhz.value = 1 await t - self.dut.clk90_125mhz <= 1 + self.dut.clk90_125mhz.value = 1 await t - self.dut.clk_125mhz <= 0 + self.dut.clk_125mhz.value = 0 await t - self.dut.clk90_125mhz <= 0 + self.dut.clk90_125mhz.value = 0 await t diff --git a/fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/test_fpga_core.py index 1268b0025..6061778ed 100644 --- a/fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/test_fpga_core.py @@ -72,14 +72,14 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk_125mhz) - self.dut.rst_125mhz <= 1 - self.dut.phy_gmii_rst <= 1 + self.dut.rst_125mhz.value = 1 + self.dut.phy_gmii_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk_125mhz) - self.dut.rst_125mhz <= 0 - self.dut.phy_gmii_rst <= 0 + self.dut.rst_125mhz.value = 0 + self.dut.phy_gmii_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index 5f8296d10..4a25a06c1 100644 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -85,28 +85,28 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.sfp_1_rx_rst <= 1 - self.dut.sfp_1_tx_rst <= 1 - self.dut.sfp_2_rx_rst <= 1 - self.dut.sfp_2_tx_rst <= 1 - self.dut.sfp_3_rx_rst <= 1 - self.dut.sfp_3_tx_rst <= 1 - self.dut.sfp_4_rx_rst <= 1 - self.dut.sfp_4_tx_rst <= 1 + self.dut.rst.value = 1 + self.dut.sfp_1_rx_rst.value = 1 + self.dut.sfp_1_tx_rst.value = 1 + self.dut.sfp_2_rx_rst.value = 1 + self.dut.sfp_2_tx_rst.value = 1 + self.dut.sfp_3_rx_rst.value = 1 + self.dut.sfp_3_tx_rst.value = 1 + self.dut.sfp_4_rx_rst.value = 1 + self.dut.sfp_4_tx_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.sfp_1_rx_rst <= 0 - self.dut.sfp_1_tx_rst <= 0 - self.dut.sfp_2_rx_rst <= 0 - self.dut.sfp_2_tx_rst <= 0 - self.dut.sfp_3_rx_rst <= 0 - self.dut.sfp_3_tx_rst <= 0 - self.dut.sfp_4_rx_rst <= 0 - self.dut.sfp_4_tx_rst <= 0 + self.dut.rst.value = 0 + self.dut.sfp_1_rx_rst.value = 0 + self.dut.sfp_1_tx_rst.value = 0 + self.dut.sfp_2_rx_rst.value = 0 + self.dut.sfp_2_tx_rst.value = 0 + self.dut.sfp_3_rx_rst.value = 0 + self.dut.sfp_3_tx_rst.value = 0 + self.dut.sfp_4_rx_rst.value = 0 + self.dut.sfp_4_tx_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/test_fpga_core.py index e34c42ee6..042262ec0 100644 --- a/fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/test_fpga_core.py @@ -70,23 +70,23 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 + self.dut.rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 + self.dut.rst.value = 0 async def _run_clk(self): t = Timer(2, 'ns') while True: - self.dut.clk <= 1 + self.dut.clk.value = 1 await t - self.dut.clk90 <= 1 + self.dut.clk90.value = 1 await t - self.dut.clk <= 0 + self.dut.clk.value = 0 await t - self.dut.clk90 <= 0 + self.dut.clk90.value = 0 await t diff --git a/fpga/lib/eth/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py index d1c4fc17d..72d03bd32 100644 --- a/fpga/lib/eth/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -178,44 +178,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp1_mac_1_rx_rst <= 1 - self.dut.qsfp1_mac_1_tx_rst <= 1 - self.dut.qsfp1_mac_2_rx_rst <= 1 - self.dut.qsfp1_mac_2_tx_rst <= 1 - self.dut.qsfp1_mac_3_rx_rst <= 1 - self.dut.qsfp1_mac_3_tx_rst <= 1 - self.dut.qsfp1_mac_4_rx_rst <= 1 - self.dut.qsfp1_mac_4_tx_rst <= 1 - self.dut.qsfp2_mac_1_rx_rst <= 1 - self.dut.qsfp2_mac_1_tx_rst <= 1 - self.dut.qsfp2_mac_2_rx_rst <= 1 - self.dut.qsfp2_mac_2_tx_rst <= 1 - self.dut.qsfp2_mac_3_rx_rst <= 1 - self.dut.qsfp2_mac_3_tx_rst <= 1 - self.dut.qsfp2_mac_4_rx_rst <= 1 - self.dut.qsfp2_mac_4_tx_rst <= 1 + self.dut.rst.value = 1 + self.dut.qsfp1_mac_1_rx_rst.value = 1 + self.dut.qsfp1_mac_1_tx_rst.value = 1 + self.dut.qsfp1_mac_2_rx_rst.value = 1 + self.dut.qsfp1_mac_2_tx_rst.value = 1 + self.dut.qsfp1_mac_3_rx_rst.value = 1 + self.dut.qsfp1_mac_3_tx_rst.value = 1 + self.dut.qsfp1_mac_4_rx_rst.value = 1 + self.dut.qsfp1_mac_4_tx_rst.value = 1 + self.dut.qsfp2_mac_1_rx_rst.value = 1 + self.dut.qsfp2_mac_1_tx_rst.value = 1 + self.dut.qsfp2_mac_2_rx_rst.value = 1 + self.dut.qsfp2_mac_2_tx_rst.value = 1 + self.dut.qsfp2_mac_3_rx_rst.value = 1 + self.dut.qsfp2_mac_3_tx_rst.value = 1 + self.dut.qsfp2_mac_4_rx_rst.value = 1 + self.dut.qsfp2_mac_4_tx_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp1_mac_1_rx_rst <= 0 - self.dut.qsfp1_mac_1_tx_rst <= 0 - self.dut.qsfp1_mac_2_rx_rst <= 0 - self.dut.qsfp1_mac_2_tx_rst <= 0 - self.dut.qsfp1_mac_3_rx_rst <= 0 - self.dut.qsfp1_mac_3_tx_rst <= 0 - self.dut.qsfp1_mac_4_rx_rst <= 0 - self.dut.qsfp1_mac_4_tx_rst <= 0 - self.dut.qsfp2_mac_1_rx_rst <= 0 - self.dut.qsfp2_mac_1_tx_rst <= 0 - self.dut.qsfp2_mac_2_rx_rst <= 0 - self.dut.qsfp2_mac_2_tx_rst <= 0 - self.dut.qsfp2_mac_3_rx_rst <= 0 - self.dut.qsfp2_mac_3_tx_rst <= 0 - self.dut.qsfp2_mac_4_rx_rst <= 0 - self.dut.qsfp2_mac_4_tx_rst <= 0 + self.dut.rst.value = 0 + self.dut.qsfp1_mac_1_rx_rst.value = 0 + self.dut.qsfp1_mac_1_tx_rst.value = 0 + self.dut.qsfp1_mac_2_rx_rst.value = 0 + self.dut.qsfp1_mac_2_tx_rst.value = 0 + self.dut.qsfp1_mac_3_rx_rst.value = 0 + self.dut.qsfp1_mac_3_tx_rst.value = 0 + self.dut.qsfp1_mac_4_rx_rst.value = 0 + self.dut.qsfp1_mac_4_tx_rst.value = 0 + self.dut.qsfp2_mac_1_rx_rst.value = 0 + self.dut.qsfp2_mac_1_tx_rst.value = 0 + self.dut.qsfp2_mac_2_rx_rst.value = 0 + self.dut.qsfp2_mac_2_tx_rst.value = 0 + self.dut.qsfp2_mac_3_rx_rst.value = 0 + self.dut.qsfp2_mac_3_tx_rst.value = 0 + self.dut.qsfp2_mac_4_rx_rst.value = 0 + self.dut.qsfp2_mac_4_tx_rst.value = 0 for k in range(10): await RisingEdge(self.dut.clk) diff --git a/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py index 4c378adc0..934d967e9 100644 --- a/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -111,44 +111,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp0_rx_rst_1 <= 1 - self.dut.qsfp0_tx_rst_1 <= 1 - self.dut.qsfp0_rx_rst_2 <= 1 - self.dut.qsfp0_tx_rst_2 <= 1 - self.dut.qsfp0_rx_rst_3 <= 1 - self.dut.qsfp0_tx_rst_3 <= 1 - self.dut.qsfp0_rx_rst_4 <= 1 - self.dut.qsfp0_tx_rst_4 <= 1 - self.dut.qsfp1_rx_rst_1 <= 1 - self.dut.qsfp1_tx_rst_1 <= 1 - self.dut.qsfp1_rx_rst_2 <= 1 - self.dut.qsfp1_tx_rst_2 <= 1 - self.dut.qsfp1_rx_rst_3 <= 1 - self.dut.qsfp1_tx_rst_3 <= 1 - self.dut.qsfp1_rx_rst_4 <= 1 - self.dut.qsfp1_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp0_rx_rst_1.value = 1 + self.dut.qsfp0_tx_rst_1.value = 1 + self.dut.qsfp0_rx_rst_2.value = 1 + self.dut.qsfp0_tx_rst_2.value = 1 + self.dut.qsfp0_rx_rst_3.value = 1 + self.dut.qsfp0_tx_rst_3.value = 1 + self.dut.qsfp0_rx_rst_4.value = 1 + self.dut.qsfp0_tx_rst_4.value = 1 + self.dut.qsfp1_rx_rst_1.value = 1 + self.dut.qsfp1_tx_rst_1.value = 1 + self.dut.qsfp1_rx_rst_2.value = 1 + self.dut.qsfp1_tx_rst_2.value = 1 + self.dut.qsfp1_rx_rst_3.value = 1 + self.dut.qsfp1_tx_rst_3.value = 1 + self.dut.qsfp1_rx_rst_4.value = 1 + self.dut.qsfp1_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp0_rx_rst_1 <= 0 - self.dut.qsfp0_tx_rst_1 <= 0 - self.dut.qsfp0_rx_rst_2 <= 0 - self.dut.qsfp0_tx_rst_2 <= 0 - self.dut.qsfp0_rx_rst_3 <= 0 - self.dut.qsfp0_tx_rst_3 <= 0 - self.dut.qsfp0_rx_rst_4 <= 0 - self.dut.qsfp0_tx_rst_4 <= 0 - self.dut.qsfp1_rx_rst_1 <= 0 - self.dut.qsfp1_tx_rst_1 <= 0 - self.dut.qsfp1_rx_rst_2 <= 0 - self.dut.qsfp1_tx_rst_2 <= 0 - self.dut.qsfp1_rx_rst_3 <= 0 - self.dut.qsfp1_tx_rst_3 <= 0 - self.dut.qsfp1_rx_rst_4 <= 0 - self.dut.qsfp1_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp0_rx_rst_1.value = 0 + self.dut.qsfp0_tx_rst_1.value = 0 + self.dut.qsfp0_rx_rst_2.value = 0 + self.dut.qsfp0_tx_rst_2.value = 0 + self.dut.qsfp0_rx_rst_3.value = 0 + self.dut.qsfp0_tx_rst_3.value = 0 + self.dut.qsfp0_rx_rst_4.value = 0 + self.dut.qsfp0_tx_rst_4.value = 0 + self.dut.qsfp1_rx_rst_1.value = 0 + self.dut.qsfp1_tx_rst_1.value = 0 + self.dut.qsfp1_rx_rst_2.value = 0 + self.dut.qsfp1_tx_rst_2.value = 0 + self.dut.qsfp1_rx_rst_3.value = 0 + self.dut.qsfp1_tx_rst_3.value = 0 + self.dut.qsfp1_rx_rst_4.value = 0 + self.dut.qsfp1_tx_rst_4.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py index ee8ff7acb..4ec069372 100644 --- a/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -103,30 +103,30 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.phy_gmii_rst <= 1 - self.dut.qsfp_rx_rst_1 <= 1 - self.dut.qsfp_tx_rst_1 <= 1 - self.dut.qsfp_rx_rst_2 <= 1 - self.dut.qsfp_tx_rst_2 <= 1 - self.dut.qsfp_rx_rst_3 <= 1 - self.dut.qsfp_tx_rst_3 <= 1 - self.dut.qsfp_rx_rst_4 <= 1 - self.dut.qsfp_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.phy_gmii_rst.value = 1 + self.dut.qsfp_rx_rst_1.value = 1 + self.dut.qsfp_tx_rst_1.value = 1 + self.dut.qsfp_rx_rst_2.value = 1 + self.dut.qsfp_tx_rst_2.value = 1 + self.dut.qsfp_rx_rst_3.value = 1 + self.dut.qsfp_tx_rst_3.value = 1 + self.dut.qsfp_rx_rst_4.value = 1 + self.dut.qsfp_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.phy_gmii_rst <= 0 - self.dut.qsfp_rx_rst_1 <= 0 - self.dut.qsfp_tx_rst_1 <= 0 - self.dut.qsfp_rx_rst_2 <= 0 - self.dut.qsfp_tx_rst_2 <= 0 - self.dut.qsfp_rx_rst_3 <= 0 - self.dut.qsfp_tx_rst_3 <= 0 - self.dut.qsfp_rx_rst_4 <= 0 - self.dut.qsfp_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.phy_gmii_rst.value = 0 + self.dut.qsfp_rx_rst_1.value = 0 + self.dut.qsfp_tx_rst_1.value = 0 + self.dut.qsfp_rx_rst_2.value = 0 + self.dut.qsfp_tx_rst_2.value = 0 + self.dut.qsfp_rx_rst_3.value = 0 + self.dut.qsfp_tx_rst_3.value = 0 + self.dut.qsfp_rx_rst_4.value = 0 + self.dut.qsfp_tx_rst_4.value = 0 @cocotb.test() @@ -200,7 +200,7 @@ async def run_test(dut): # insert tap await RisingEdge(dut.clk) - dut.sw <= 0x8 + dut.sw.value = 0x8 await RisingEdge(dut.clk) payload = bytes([x % 256 for x in range(256)]) @@ -243,7 +243,7 @@ async def run_test(dut): # insert tap await RisingEdge(dut.clk) - dut.sw <= 0xC + dut.sw.value = 0xC await RisingEdge(dut.clk) payload = bytes([x % 256 for x in range(256)]) diff --git a/fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/test_fpga_core.py index fd8946828..07c66f794 100644 --- a/fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/test_fpga_core.py @@ -72,14 +72,14 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.phy_gmii_rst <= 1 + self.dut.rst.value = 1 + self.dut.phy_gmii_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.phy_gmii_rst <= 0 + self.dut.rst.value = 0 + self.dut.phy_gmii_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py index 656c80ae4..2ada7550b 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -131,46 +131,46 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.phy_gmii_rst <= 1 - self.dut.qsfp1_rx_rst_1 <= 1 - self.dut.qsfp1_tx_rst_1 <= 1 - self.dut.qsfp1_rx_rst_2 <= 1 - self.dut.qsfp1_tx_rst_2 <= 1 - self.dut.qsfp1_rx_rst_3 <= 1 - self.dut.qsfp1_tx_rst_3 <= 1 - self.dut.qsfp1_rx_rst_4 <= 1 - self.dut.qsfp1_tx_rst_4 <= 1 - self.dut.qsfp2_rx_rst_1 <= 1 - self.dut.qsfp2_tx_rst_1 <= 1 - self.dut.qsfp2_rx_rst_2 <= 1 - self.dut.qsfp2_tx_rst_2 <= 1 - self.dut.qsfp2_rx_rst_3 <= 1 - self.dut.qsfp2_tx_rst_3 <= 1 - self.dut.qsfp2_rx_rst_4 <= 1 - self.dut.qsfp2_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.phy_gmii_rst.value = 1 + self.dut.qsfp1_rx_rst_1.value = 1 + self.dut.qsfp1_tx_rst_1.value = 1 + self.dut.qsfp1_rx_rst_2.value = 1 + self.dut.qsfp1_tx_rst_2.value = 1 + self.dut.qsfp1_rx_rst_3.value = 1 + self.dut.qsfp1_tx_rst_3.value = 1 + self.dut.qsfp1_rx_rst_4.value = 1 + self.dut.qsfp1_tx_rst_4.value = 1 + self.dut.qsfp2_rx_rst_1.value = 1 + self.dut.qsfp2_tx_rst_1.value = 1 + self.dut.qsfp2_rx_rst_2.value = 1 + self.dut.qsfp2_tx_rst_2.value = 1 + self.dut.qsfp2_rx_rst_3.value = 1 + self.dut.qsfp2_tx_rst_3.value = 1 + self.dut.qsfp2_rx_rst_4.value = 1 + self.dut.qsfp2_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.phy_gmii_rst <= 0 - self.dut.qsfp1_rx_rst_1 <= 0 - self.dut.qsfp1_tx_rst_1 <= 0 - self.dut.qsfp1_rx_rst_2 <= 0 - self.dut.qsfp1_tx_rst_2 <= 0 - self.dut.qsfp1_rx_rst_3 <= 0 - self.dut.qsfp1_tx_rst_3 <= 0 - self.dut.qsfp1_rx_rst_4 <= 0 - self.dut.qsfp1_tx_rst_4 <= 0 - self.dut.qsfp2_rx_rst_1 <= 0 - self.dut.qsfp2_tx_rst_1 <= 0 - self.dut.qsfp2_rx_rst_2 <= 0 - self.dut.qsfp2_tx_rst_2 <= 0 - self.dut.qsfp2_rx_rst_3 <= 0 - self.dut.qsfp2_tx_rst_3 <= 0 - self.dut.qsfp2_rx_rst_4 <= 0 - self.dut.qsfp2_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.phy_gmii_rst.value = 0 + self.dut.qsfp1_rx_rst_1.value = 0 + self.dut.qsfp1_tx_rst_1.value = 0 + self.dut.qsfp1_rx_rst_2.value = 0 + self.dut.qsfp1_tx_rst_2.value = 0 + self.dut.qsfp1_rx_rst_3.value = 0 + self.dut.qsfp1_tx_rst_3.value = 0 + self.dut.qsfp1_rx_rst_4.value = 0 + self.dut.qsfp1_tx_rst_4.value = 0 + self.dut.qsfp2_rx_rst_1.value = 0 + self.dut.qsfp2_tx_rst_1.value = 0 + self.dut.qsfp2_rx_rst_2.value = 0 + self.dut.qsfp2_tx_rst_2.value = 0 + self.dut.qsfp2_rx_rst_3.value = 0 + self.dut.qsfp2_tx_rst_3.value = 0 + self.dut.qsfp2_rx_rst_4.value = 0 + self.dut.qsfp2_tx_rst_4.value = 0 @cocotb.test() @@ -244,7 +244,7 @@ async def run_test(dut): # insert tap await RisingEdge(dut.clk) - dut.sw <= 0x8 + dut.sw.value = 0x8 await RisingEdge(dut.clk) payload = bytes([x % 256 for x in range(256)]) @@ -287,7 +287,7 @@ async def run_test(dut): # insert tap await RisingEdge(dut.clk) - dut.sw <= 0xC + dut.sw.value = 0xC await RisingEdge(dut.clk) payload = bytes([x % 256 for x in range(256)]) diff --git a/fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/test_fpga_core.py index fd8946828..07c66f794 100644 --- a/fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/test_fpga_core.py @@ -72,14 +72,14 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.phy_gmii_rst <= 1 + self.dut.rst.value = 1 + self.dut.phy_gmii_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.phy_gmii_rst <= 0 + self.dut.rst.value = 0 + self.dut.phy_gmii_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index f5028aed3..0b751835f 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -131,46 +131,46 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.phy_gmii_rst <= 1 - self.dut.qsfp1_rx_rst_1 <= 1 - self.dut.qsfp1_tx_rst_1 <= 1 - self.dut.qsfp1_rx_rst_2 <= 1 - self.dut.qsfp1_tx_rst_2 <= 1 - self.dut.qsfp1_rx_rst_3 <= 1 - self.dut.qsfp1_tx_rst_3 <= 1 - self.dut.qsfp1_rx_rst_4 <= 1 - self.dut.qsfp1_tx_rst_4 <= 1 - self.dut.qsfp2_rx_rst_1 <= 1 - self.dut.qsfp2_tx_rst_1 <= 1 - self.dut.qsfp2_rx_rst_2 <= 1 - self.dut.qsfp2_tx_rst_2 <= 1 - self.dut.qsfp2_rx_rst_3 <= 1 - self.dut.qsfp2_tx_rst_3 <= 1 - self.dut.qsfp2_rx_rst_4 <= 1 - self.dut.qsfp2_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.phy_gmii_rst.value = 1 + self.dut.qsfp1_rx_rst_1.value = 1 + self.dut.qsfp1_tx_rst_1.value = 1 + self.dut.qsfp1_rx_rst_2.value = 1 + self.dut.qsfp1_tx_rst_2.value = 1 + self.dut.qsfp1_rx_rst_3.value = 1 + self.dut.qsfp1_tx_rst_3.value = 1 + self.dut.qsfp1_rx_rst_4.value = 1 + self.dut.qsfp1_tx_rst_4.value = 1 + self.dut.qsfp2_rx_rst_1.value = 1 + self.dut.qsfp2_tx_rst_1.value = 1 + self.dut.qsfp2_rx_rst_2.value = 1 + self.dut.qsfp2_tx_rst_2.value = 1 + self.dut.qsfp2_rx_rst_3.value = 1 + self.dut.qsfp2_tx_rst_3.value = 1 + self.dut.qsfp2_rx_rst_4.value = 1 + self.dut.qsfp2_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.phy_gmii_rst <= 0 - self.dut.qsfp1_rx_rst_1 <= 0 - self.dut.qsfp1_tx_rst_1 <= 0 - self.dut.qsfp1_rx_rst_2 <= 0 - self.dut.qsfp1_tx_rst_2 <= 0 - self.dut.qsfp1_rx_rst_3 <= 0 - self.dut.qsfp1_tx_rst_3 <= 0 - self.dut.qsfp1_rx_rst_4 <= 0 - self.dut.qsfp1_tx_rst_4 <= 0 - self.dut.qsfp2_rx_rst_1 <= 0 - self.dut.qsfp2_tx_rst_1 <= 0 - self.dut.qsfp2_rx_rst_2 <= 0 - self.dut.qsfp2_tx_rst_2 <= 0 - self.dut.qsfp2_rx_rst_3 <= 0 - self.dut.qsfp2_tx_rst_3 <= 0 - self.dut.qsfp2_rx_rst_4 <= 0 - self.dut.qsfp2_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.phy_gmii_rst.value = 0 + self.dut.qsfp1_rx_rst_1.value = 0 + self.dut.qsfp1_tx_rst_1.value = 0 + self.dut.qsfp1_rx_rst_2.value = 0 + self.dut.qsfp1_tx_rst_2.value = 0 + self.dut.qsfp1_rx_rst_3.value = 0 + self.dut.qsfp1_tx_rst_3.value = 0 + self.dut.qsfp1_rx_rst_4.value = 0 + self.dut.qsfp1_tx_rst_4.value = 0 + self.dut.qsfp2_rx_rst_1.value = 0 + self.dut.qsfp2_tx_rst_1.value = 0 + self.dut.qsfp2_rx_rst_2.value = 0 + self.dut.qsfp2_tx_rst_2.value = 0 + self.dut.qsfp2_rx_rst_3.value = 0 + self.dut.qsfp2_tx_rst_3.value = 0 + self.dut.qsfp2_rx_rst_4.value = 0 + self.dut.qsfp2_tx_rst_4.value = 0 @cocotb.test() @@ -244,7 +244,7 @@ async def run_test(dut): # insert tap await RisingEdge(dut.clk) - dut.sw <= 0x8 + dut.sw.value = 0x8 await RisingEdge(dut.clk) payload = bytes([x % 256 for x in range(256)]) @@ -287,7 +287,7 @@ async def run_test(dut): # insert tap await RisingEdge(dut.clk) - dut.sw <= 0xC + dut.sw.value = 0xC await RisingEdge(dut.clk) payload = bytes([x % 256 for x in range(256)]) diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py index 37a47626b..6f609015c 100644 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -113,44 +113,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp0_rx_rst_1 <= 1 - self.dut.qsfp0_tx_rst_1 <= 1 - self.dut.qsfp0_rx_rst_2 <= 1 - self.dut.qsfp0_tx_rst_2 <= 1 - self.dut.qsfp0_rx_rst_3 <= 1 - self.dut.qsfp0_tx_rst_3 <= 1 - self.dut.qsfp0_rx_rst_4 <= 1 - self.dut.qsfp0_tx_rst_4 <= 1 - self.dut.qsfp1_rx_rst_1 <= 1 - self.dut.qsfp1_tx_rst_1 <= 1 - self.dut.qsfp1_rx_rst_2 <= 1 - self.dut.qsfp1_tx_rst_2 <= 1 - self.dut.qsfp1_rx_rst_3 <= 1 - self.dut.qsfp1_tx_rst_3 <= 1 - self.dut.qsfp1_rx_rst_4 <= 1 - self.dut.qsfp1_tx_rst_4 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp0_rx_rst_1.value = 1 + self.dut.qsfp0_tx_rst_1.value = 1 + self.dut.qsfp0_rx_rst_2.value = 1 + self.dut.qsfp0_tx_rst_2.value = 1 + self.dut.qsfp0_rx_rst_3.value = 1 + self.dut.qsfp0_tx_rst_3.value = 1 + self.dut.qsfp0_rx_rst_4.value = 1 + self.dut.qsfp0_tx_rst_4.value = 1 + self.dut.qsfp1_rx_rst_1.value = 1 + self.dut.qsfp1_tx_rst_1.value = 1 + self.dut.qsfp1_rx_rst_2.value = 1 + self.dut.qsfp1_tx_rst_2.value = 1 + self.dut.qsfp1_rx_rst_3.value = 1 + self.dut.qsfp1_tx_rst_3.value = 1 + self.dut.qsfp1_rx_rst_4.value = 1 + self.dut.qsfp1_tx_rst_4.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp0_rx_rst_1 <= 0 - self.dut.qsfp0_tx_rst_1 <= 0 - self.dut.qsfp0_rx_rst_2 <= 0 - self.dut.qsfp0_tx_rst_2 <= 0 - self.dut.qsfp0_rx_rst_3 <= 0 - self.dut.qsfp0_tx_rst_3 <= 0 - self.dut.qsfp0_rx_rst_4 <= 0 - self.dut.qsfp0_tx_rst_4 <= 0 - self.dut.qsfp1_rx_rst_1 <= 0 - self.dut.qsfp1_tx_rst_1 <= 0 - self.dut.qsfp1_rx_rst_2 <= 0 - self.dut.qsfp1_tx_rst_2 <= 0 - self.dut.qsfp1_rx_rst_3 <= 0 - self.dut.qsfp1_tx_rst_3 <= 0 - self.dut.qsfp1_rx_rst_4 <= 0 - self.dut.qsfp1_tx_rst_4 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp0_rx_rst_1.value = 0 + self.dut.qsfp0_tx_rst_1.value = 0 + self.dut.qsfp0_rx_rst_2.value = 0 + self.dut.qsfp0_tx_rst_2.value = 0 + self.dut.qsfp0_rx_rst_3.value = 0 + self.dut.qsfp0_tx_rst_3.value = 0 + self.dut.qsfp0_rx_rst_4.value = 0 + self.dut.qsfp0_tx_rst_4.value = 0 + self.dut.qsfp1_rx_rst_1.value = 0 + self.dut.qsfp1_tx_rst_1.value = 0 + self.dut.qsfp1_rx_rst_2.value = 0 + self.dut.qsfp1_tx_rst_2.value = 0 + self.dut.qsfp1_rx_rst_3.value = 0 + self.dut.qsfp1_tx_rst_3.value = 0 + self.dut.qsfp1_rx_rst_4.value = 0 + self.dut.qsfp1_tx_rst_4.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 5e47a3c22..78aca5d74 100644 --- a/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -92,28 +92,28 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.sfp0_rx_rst <= 1 - self.dut.sfp0_tx_rst <= 1 - self.dut.sfp1_rx_rst <= 1 - self.dut.sfp1_tx_rst <= 1 - self.dut.sfp2_rx_rst <= 1 - self.dut.sfp2_tx_rst <= 1 - self.dut.sfp3_rx_rst <= 1 - self.dut.sfp3_tx_rst <= 1 + self.dut.rst.value = 1 + self.dut.sfp0_rx_rst.value = 1 + self.dut.sfp0_tx_rst.value = 1 + self.dut.sfp1_rx_rst.value = 1 + self.dut.sfp1_tx_rst.value = 1 + self.dut.sfp2_rx_rst.value = 1 + self.dut.sfp2_tx_rst.value = 1 + self.dut.sfp3_rx_rst.value = 1 + self.dut.sfp3_tx_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.sfp0_rx_rst <= 0 - self.dut.sfp0_tx_rst <= 0 - self.dut.sfp1_rx_rst <= 0 - self.dut.sfp1_tx_rst <= 0 - self.dut.sfp2_rx_rst <= 0 - self.dut.sfp2_tx_rst <= 0 - self.dut.sfp3_rx_rst <= 0 - self.dut.sfp3_tx_rst <= 0 + self.dut.rst.value = 0 + self.dut.sfp0_rx_rst.value = 0 + self.dut.sfp0_tx_rst.value = 0 + self.dut.sfp1_rx_rst.value = 0 + self.dut.sfp1_tx_rst.value = 0 + self.dut.sfp2_rx_rst.value = 0 + self.dut.sfp2_tx_rst.value = 0 + self.dut.sfp3_rx_rst.value = 0 + self.dut.sfp3_tx_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py index 7de8d6e9f..14a213b12 100644 --- a/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py @@ -78,20 +78,20 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.sfp0_rx_rst <= 1 - self.dut.sfp0_tx_rst <= 1 - self.dut.sfp1_rx_rst <= 1 - self.dut.sfp1_tx_rst <= 1 + self.dut.rst.value = 1 + self.dut.sfp0_rx_rst.value = 1 + self.dut.sfp0_tx_rst.value = 1 + self.dut.sfp1_rx_rst.value = 1 + self.dut.sfp1_tx_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.sfp0_rx_rst <= 0 - self.dut.sfp0_tx_rst <= 0 - self.dut.sfp1_rx_rst <= 0 - self.dut.sfp1_tx_rst <= 0 + self.dut.rst.value = 0 + self.dut.sfp0_rx_rst.value = 0 + self.dut.sfp0_tx_rst.value = 0 + self.dut.sfp1_rx_rst.value = 0 + self.dut.sfp1_tx_rst.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py index 181fdbf0d..9dcbf1323 100644 --- a/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -111,44 +111,44 @@ class TB: for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 1 - self.dut.qsfp_0_rx_rst_0 <= 1 - self.dut.qsfp_0_tx_rst_0 <= 1 - self.dut.qsfp_0_rx_rst_1 <= 1 - self.dut.qsfp_0_tx_rst_1 <= 1 - self.dut.qsfp_0_rx_rst_2 <= 1 - self.dut.qsfp_0_tx_rst_2 <= 1 - self.dut.qsfp_0_rx_rst_3 <= 1 - self.dut.qsfp_0_tx_rst_3 <= 1 - self.dut.qsfp_1_rx_rst_0 <= 1 - self.dut.qsfp_1_tx_rst_0 <= 1 - self.dut.qsfp_1_rx_rst_1 <= 1 - self.dut.qsfp_1_tx_rst_1 <= 1 - self.dut.qsfp_1_rx_rst_2 <= 1 - self.dut.qsfp_1_tx_rst_2 <= 1 - self.dut.qsfp_1_rx_rst_3 <= 1 - self.dut.qsfp_1_tx_rst_3 <= 1 + self.dut.rst.value = 1 + self.dut.qsfp_0_rx_rst_0.value = 1 + self.dut.qsfp_0_tx_rst_0.value = 1 + self.dut.qsfp_0_rx_rst_1.value = 1 + self.dut.qsfp_0_tx_rst_1.value = 1 + self.dut.qsfp_0_rx_rst_2.value = 1 + self.dut.qsfp_0_tx_rst_2.value = 1 + self.dut.qsfp_0_rx_rst_3.value = 1 + self.dut.qsfp_0_tx_rst_3.value = 1 + self.dut.qsfp_1_rx_rst_0.value = 1 + self.dut.qsfp_1_tx_rst_0.value = 1 + self.dut.qsfp_1_rx_rst_1.value = 1 + self.dut.qsfp_1_tx_rst_1.value = 1 + self.dut.qsfp_1_rx_rst_2.value = 1 + self.dut.qsfp_1_tx_rst_2.value = 1 + self.dut.qsfp_1_rx_rst_3.value = 1 + self.dut.qsfp_1_tx_rst_3.value = 1 for k in range(10): await RisingEdge(self.dut.clk) - self.dut.rst <= 0 - self.dut.qsfp_0_rx_rst_0 <= 0 - self.dut.qsfp_0_tx_rst_0 <= 0 - self.dut.qsfp_0_rx_rst_1 <= 0 - self.dut.qsfp_0_tx_rst_1 <= 0 - self.dut.qsfp_0_rx_rst_2 <= 0 - self.dut.qsfp_0_tx_rst_2 <= 0 - self.dut.qsfp_0_rx_rst_3 <= 0 - self.dut.qsfp_0_tx_rst_3 <= 0 - self.dut.qsfp_1_rx_rst_0 <= 0 - self.dut.qsfp_1_tx_rst_0 <= 0 - self.dut.qsfp_1_rx_rst_1 <= 0 - self.dut.qsfp_1_tx_rst_1 <= 0 - self.dut.qsfp_1_rx_rst_2 <= 0 - self.dut.qsfp_1_tx_rst_2 <= 0 - self.dut.qsfp_1_rx_rst_3 <= 0 - self.dut.qsfp_1_tx_rst_3 <= 0 + self.dut.rst.value = 0 + self.dut.qsfp_0_rx_rst_0.value = 0 + self.dut.qsfp_0_tx_rst_0.value = 0 + self.dut.qsfp_0_rx_rst_1.value = 0 + self.dut.qsfp_0_tx_rst_1.value = 0 + self.dut.qsfp_0_rx_rst_2.value = 0 + self.dut.qsfp_0_tx_rst_2.value = 0 + self.dut.qsfp_0_rx_rst_3.value = 0 + self.dut.qsfp_0_tx_rst_3.value = 0 + self.dut.qsfp_1_rx_rst_0.value = 0 + self.dut.qsfp_1_tx_rst_0.value = 0 + self.dut.qsfp_1_rx_rst_1.value = 0 + self.dut.qsfp_1_tx_rst_1.value = 0 + self.dut.qsfp_1_rx_rst_2.value = 0 + self.dut.qsfp_1_tx_rst_2.value = 0 + self.dut.qsfp_1_rx_rst_3.value = 0 + self.dut.qsfp_1_tx_rst_3.value = 0 @cocotb.test() diff --git a/fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml b/fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml index d7688d46a..bd104f64f 100644 --- a/fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml +++ b/fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml @@ -9,14 +9,14 @@ jobs: strategy: matrix: - python-version: [3.9] + python-version: ["3.10"] group: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10] steps: - - uses: actions/checkout@v1 + - uses: actions/checkout@v3 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v2 + uses: actions/setup-python@v4 with: python-version: ${{ matrix.python-version }} @@ -30,4 +30,4 @@ jobs: pip install tox tox-gh-actions - name: Test with tox - run: tox -- --splits 10 --group ${{ matrix.group }} + run: tox -- -n auto --verbose --splits 10 --group ${{ matrix.group }} diff --git a/fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile b/fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile index 621657d76..9f9110dca 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile @@ -49,18 +49,7 @@ export PARAM_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).S_DATA_WIDTH=$(PARAM_S_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_DATA_WIDTH=$(PARAM_M_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -69,18 +58,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GS_DATA_WIDTH=$(PARAM_S_DATA_WIDTH) - COMPILE_ARGS += -GS_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE) - COMPILE_ARGS += -GS_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH) - COMPILE_ARGS += -GM_DATA_WIDTH=$(PARAM_M_DATA_WIDTH) - COMPILE_ARGS += -GM_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) - COMPILE_ARGS += -GM_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile b/fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile index 936f22b1c..194d8975e 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile @@ -56,20 +56,7 @@ export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).M_ID_WIDTH=$(PARAM_M_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_ID_WIDTH=$(PARAM_S_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).UPDATE_TID=$(PARAM_UPDATE_TID) - COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN) - COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -78,20 +65,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GM_ID_WIDTH=$(PARAM_M_ID_WIDTH) - COMPILE_ARGS += -GS_ID_WIDTH=$(PARAM_S_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GUPDATE_TID=$(PARAM_UPDATE_TID) - COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN) - COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile index 1b871e0e2..792f5532c 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile @@ -55,25 +55,7 @@ export PARAM_DROP_WHEN_FULL ?= 0 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).OUTPUT_FIFO_ENABLE=$(PARAM_OUTPUT_FIFO_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO=$(PARAM_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_OVERSIZE_FRAME=$(PARAM_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -82,25 +64,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -GOUTPUT_FIFO_ENABLE=$(PARAM_OUTPUT_FIFO_ENABLE) - COMPILE_ARGS += -GFRAME_FIFO=$(PARAM_FRAME_FIFO) - COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -GDROP_OVERSIZE_FRAME=$(PARAM_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GDROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -GDROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile b/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile index 7f4ba7431..7c7d65f93 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile @@ -60,27 +60,7 @@ export PARAM_DROP_WHEN_FULL ?= 0 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_DATA_WIDTH=$(PARAM_S_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_DATA_WIDTH=$(PARAM_M_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).OUTPUT_FIFO_ENABLE=$(PARAM_OUTPUT_FIFO_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO=$(PARAM_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_OVERSIZE_FRAME=$(PARAM_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -89,27 +69,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -GS_DATA_WIDTH=$(PARAM_S_DATA_WIDTH) - COMPILE_ARGS += -GS_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE) - COMPILE_ARGS += -GS_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH) - COMPILE_ARGS += -GM_DATA_WIDTH=$(PARAM_M_DATA_WIDTH) - COMPILE_ARGS += -GM_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) - COMPILE_ARGS += -GM_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -GOUTPUT_FIFO_ENABLE=$(PARAM_OUTPUT_FIFO_ENABLE) - COMPILE_ARGS += -GFRAME_FIFO=$(PARAM_FRAME_FIFO) - COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -GDROP_OVERSIZE_FRAME=$(PARAM_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GDROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -GDROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile b/fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile index 7b66215cd..afef17eca 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile @@ -50,16 +50,7 @@ export PARAM_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -68,16 +59,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile b/fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile index 713851756..535c69dbe 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile @@ -37,7 +37,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - #COMPILE_ARGS += -P $(TOPLEVEL).APPEND_ZERO=$(PARAM_APPEND_ZERO) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -46,7 +46,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - #COMPILE_ARGS += -GAPPEND_ZERO=$(PARAM_APPEND_ZERO) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile b/fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile index f52acd1c3..e0b47bc58 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile @@ -38,7 +38,7 @@ export PARAM_APPEND_ZERO ?= 0 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).APPEND_ZERO=$(PARAM_APPEND_ZERO) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -47,7 +47,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GAPPEND_ZERO=$(PARAM_APPEND_ZERO) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_demux/Makefile b/fpga/lib/eth/lib/axis/tb/axis_demux/Makefile index 8822019d2..1a304bffc 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_demux/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_demux/Makefile @@ -51,17 +51,7 @@ export PARAM_TDEST_ROUTE ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).S_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TDEST_ROUTE=$(PARAM_TDEST_ROUTE) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -70,17 +60,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GS_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) - COMPILE_ARGS += -GM_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GTDEST_ROUTE=$(PARAM_TDEST_ROUTE) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile index b9efb186a..cd64ead7e 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile @@ -55,25 +55,7 @@ export PARAM_DROP_WHEN_FULL ?= 0 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).OUTPUT_FIFO_ENABLE=$(PARAM_OUTPUT_FIFO_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO=$(PARAM_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_OVERSIZE_FRAME=$(PARAM_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -82,25 +64,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -GOUTPUT_FIFO_ENABLE=$(PARAM_OUTPUT_FIFO_ENABLE) - COMPILE_ARGS += -GFRAME_FIFO=$(PARAM_FRAME_FIFO) - COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -GDROP_OVERSIZE_FRAME=$(PARAM_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GDROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -GDROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile b/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile index c6957a5f6..bda1e8c98 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile @@ -60,27 +60,7 @@ export PARAM_DROP_WHEN_FULL ?= 0 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_DATA_WIDTH=$(PARAM_S_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_DATA_WIDTH=$(PARAM_M_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).OUTPUT_FIFO_ENABLE=$(PARAM_OUTPUT_FIFO_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO=$(PARAM_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_OVERSIZE_FRAME=$(PARAM_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -89,27 +69,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -GS_DATA_WIDTH=$(PARAM_S_DATA_WIDTH) - COMPILE_ARGS += -GS_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE) - COMPILE_ARGS += -GS_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH) - COMPILE_ARGS += -GM_DATA_WIDTH=$(PARAM_M_DATA_WIDTH) - COMPILE_ARGS += -GM_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) - COMPILE_ARGS += -GM_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -GOUTPUT_FIFO_ENABLE=$(PARAM_OUTPUT_FIFO_ENABLE) - COMPILE_ARGS += -GFRAME_FIFO=$(PARAM_FRAME_FIFO) - COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -GDROP_OVERSIZE_FRAME=$(PARAM_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GDROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -GDROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile b/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile index abe6052c3..60983e25a 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile @@ -46,16 +46,7 @@ export PARAM_LEN_WIDTH ?= 16 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -64,16 +55,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile index 59b5d822c..aac62b210 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile @@ -50,18 +50,7 @@ export PARAM_HEADER_FIFO_DEPTH ?= 8 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).FRAME_FIFO_DEPTH=$(PARAM_FRAME_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).HEADER_FIFO_DEPTH=$(PARAM_HEADER_FIFO_DEPTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -70,18 +59,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) - COMPILE_ARGS += -GFRAME_FIFO_DEPTH=$(PARAM_FRAME_FIFO_DEPTH) - COMPILE_ARGS += -GHEADER_FIFO_DEPTH=$(PARAM_HEADER_FIFO_DEPTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_mux/Makefile b/fpga/lib/eth/lib/axis/tb/axis_mux/Makefile index 247a0784c..c5d945d34 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_mux/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_mux/Makefile @@ -49,15 +49,7 @@ export PARAM_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -66,15 +58,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile index a356a55e1..f60a41da1 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile @@ -47,17 +47,7 @@ export PARAM_LENGTH ?= 2 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LENGTH=$(PARAM_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -66,17 +56,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GLENGTH=$(PARAM_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile b/fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile index 13e6e6cf5..a36c6995e 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile @@ -49,18 +49,7 @@ export PARAM_LENGTH ?= 2 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).REG_TYPE=$(PARAM_REG_TYPE) - COMPILE_ARGS += -P $(TOPLEVEL).LENGTH=$(PARAM_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -69,18 +58,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GREG_TYPE=$(PARAM_REG_TYPE) - COMPILE_ARGS += -GLENGTH=$(PARAM_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile b/fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile index 6b07dabe7..674c2bed2 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile @@ -68,30 +68,7 @@ export PARAM_RAM_PIPELINE ?= 2 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).FIFO_DEPTH=$(PARAM_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).CMD_FIFO_DEPTH=$(PARAM_CMD_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).SPEEDUP=$(PARAM_SPEEDUP) - COMPILE_ARGS += -P $(TOPLEVEL).S_DATA_WIDTH=$(PARAM_S_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_DATA_WIDTH=$(PARAM_M_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).S_ID_WIDTH=$(PARAM_S_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_ID_WIDTH=$(PARAM_M_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).DROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).UPDATE_TID=$(PARAM_UPDATE_TID) - COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN) - COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -100,30 +77,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GFIFO_DEPTH=$(PARAM_FIFO_DEPTH) - COMPILE_ARGS += -GCMD_FIFO_DEPTH=$(PARAM_CMD_FIFO_DEPTH) - COMPILE_ARGS += -GSPEEDUP=$(PARAM_SPEEDUP) - COMPILE_ARGS += -GS_DATA_WIDTH=$(PARAM_S_DATA_WIDTH) - COMPILE_ARGS += -GS_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE) - COMPILE_ARGS += -GS_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH) - COMPILE_ARGS += -GM_DATA_WIDTH=$(PARAM_M_DATA_WIDTH) - COMPILE_ARGS += -GM_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) - COMPILE_ARGS += -GM_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GS_ID_WIDTH=$(PARAM_S_ID_WIDTH) - COMPILE_ARGS += -GM_ID_WIDTH=$(PARAM_M_ID_WIDTH) - COMPILE_ARGS += -GS_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) - COMPILE_ARGS += -GM_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) - COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK) - COMPILE_ARGS += -GDROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME) - COMPILE_ARGS += -GDROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL) - COMPILE_ARGS += -GUPDATE_TID=$(PARAM_UPDATE_TID) - COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN) - COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY) - COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile b/fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile index 002d611ce..858372c43 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile @@ -46,16 +46,7 @@ export PARAM_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -64,16 +55,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_register/Makefile b/fpga/lib/eth/lib/axis/tb/axis_register/Makefile index 0a2e2e9de..9015a57c9 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_register/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_register/Makefile @@ -47,17 +47,7 @@ export PARAM_REG_TYPE ?= 2 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).REG_TYPE=$(PARAM_REG_TYPE) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -66,17 +56,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GREG_TYPE=$(PARAM_REG_TYPE) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile index 43b43716c..2d25adf0d 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile @@ -46,16 +46,7 @@ export PARAM_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -64,16 +55,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDEPTH=$(PARAM_DEPTH) - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile b/fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile index d7c66b764..7a6e63cf1 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile @@ -46,16 +46,7 @@ export PARAM_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -64,16 +55,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_switch/Makefile b/fpga/lib/eth/lib/axis/tb/axis_switch/Makefile index a59fb3dbe..229f5f8c8 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_switch/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_switch/Makefile @@ -59,21 +59,7 @@ export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).S_ID_WIDTH=$(PARAM_S_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_ID_WIDTH=$(PARAM_M_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).S_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).M_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).UPDATE_TID=$(PARAM_UPDATE_TID) - COMPILE_ARGS += -P $(TOPLEVEL).S_REG_TYPE=$(PARAM_S_REG_TYPE) - COMPILE_ARGS += -P $(TOPLEVEL).M_REG_TYPE=$(PARAM_M_REG_TYPE) - COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN) - COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -82,21 +68,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GS_ID_WIDTH=$(PARAM_S_ID_WIDTH) - COMPILE_ARGS += -GM_ID_WIDTH=$(PARAM_M_ID_WIDTH) - COMPILE_ARGS += -GS_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) - COMPILE_ARGS += -GM_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) - COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) - COMPILE_ARGS += -GUPDATE_TID=$(PARAM_UPDATE_TID) - COMPILE_ARGS += -GS_REG_TYPE=$(PARAM_S_REG_TYPE) - COMPILE_ARGS += -GM_REG_TYPE=$(PARAM_M_REG_TYPE) - COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN) - COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/lib/axis/tox.ini b/fpga/lib/eth/lib/axis/tox.ini index a1f6a3e40..fe68aa7a1 100644 --- a/fpga/lib/eth/lib/axis/tox.ini +++ b/fpga/lib/eth/lib/axis/tox.ini @@ -7,21 +7,21 @@ requires = virtualenv >= 16.1 [gh-actions] python = - 3.9: py3 + 3.10: py3 [testenv] deps = - pytest == 7.1.3 - pytest-xdist == 2.5.0 + pytest == 7.2.1 + pytest-xdist == 3.1.0 pytest-split == 0.8.0 - cocotb == 1.7.0 + cocotb == 1.7.2 cocotb-bus == 0.2.1 - cocotb-test == 0.2.2 - cocotbext-axi == 0.1.18 + cocotb-test == 0.2.4 + cocotbext-axi == 0.1.20 jinja2 == 3.1.2 commands = - pytest -n auto {posargs} + pytest {posargs:-n auto --verbose} # pytest configuration [pytest] diff --git a/fpga/lib/eth/tb/arp/Makefile b/fpga/lib/eth/tb/arp/Makefile index 009b3a5b1..e0e93714b 100644 --- a/fpga/lib/eth/tb/arp/Makefile +++ b/fpga/lib/eth/tb/arp/Makefile @@ -47,13 +47,7 @@ export PARAM_REQUEST_TIMEOUT ?= 800 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CACHE_ADDR_WIDTH=$(PARAM_CACHE_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).REQUEST_RETRY_COUNT=$(PARAM_REQUEST_RETRY_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).REQUEST_RETRY_INTERVAL=$(PARAM_REQUEST_RETRY_INTERVAL) - COMPILE_ARGS += -P $(TOPLEVEL).REQUEST_TIMEOUT=$(PARAM_REQUEST_TIMEOUT) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -62,13 +56,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GCACHE_ADDR_WIDTH=$(PARAM_CACHE_ADDR_WIDTH) - COMPILE_ARGS += -GREQUEST_RETRY_COUNT=$(PARAM_REQUEST_RETRY_COUNT) - COMPILE_ARGS += -GREQUEST_RETRY_INTERVAL=$(PARAM_REQUEST_RETRY_INTERVAL) - COMPILE_ARGS += -GREQUEST_TIMEOUT=$(PARAM_REQUEST_TIMEOUT) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/arp_cache/Makefile b/fpga/lib/eth/tb/arp_cache/Makefile index bbeaa754a..ccb5334b3 100644 --- a/fpga/lib/eth/tb/arp_cache/Makefile +++ b/fpga/lib/eth/tb/arp_cache/Makefile @@ -38,7 +38,7 @@ export PARAM_CACHE_ADDR_WIDTH ?= 2 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).CACHE_ADDR_WIDTH=$(PARAM_CACHE_ADDR_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -47,7 +47,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GCACHE_ADDR_WIDTH=$(PARAM_CACHE_ADDR_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/arp_eth_rx/Makefile b/fpga/lib/eth/tb/arp_eth_rx/Makefile index 876b4d15c..f8fe08abd 100644 --- a/fpga/lib/eth/tb/arp_eth_rx/Makefile +++ b/fpga/lib/eth/tb/arp_eth_rx/Makefile @@ -39,9 +39,7 @@ export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -50,9 +48,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/arp_eth_tx/Makefile b/fpga/lib/eth/tb/arp_eth_tx/Makefile index ab9a33b24..fb605e5d6 100644 --- a/fpga/lib/eth/tb/arp_eth_tx/Makefile +++ b/fpga/lib/eth/tb/arp_eth_tx/Makefile @@ -39,9 +39,7 @@ export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -50,9 +48,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/axis_baser_rx_64/Makefile b/fpga/lib/eth/tb/axis_baser_rx_64/Makefile index 5df88fe8f..654a8683e 100644 --- a/fpga/lib/eth/tb/axis_baser_rx_64/Makefile +++ b/fpga/lib/eth/tb/axis_baser_rx_64/Makefile @@ -43,12 +43,7 @@ export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -57,12 +52,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/axis_baser_tx_64/Makefile b/fpga/lib/eth/tb/axis_baser_tx_64/Makefile index e2ce3228a..76dece3f2 100644 --- a/fpga/lib/eth/tb/axis_baser_tx_64/Makefile +++ b/fpga/lib/eth/tb/axis_baser_tx_64/Makefile @@ -48,17 +48,7 @@ export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_ENABLE=$(PARAM_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -67,17 +57,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GPTP_TAG_ENABLE=$(PARAM_PTP_TAG_ENABLE) - COMPILE_ARGS += -GPTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/axis_gmii_rx/Makefile b/fpga/lib/eth/tb/axis_gmii_rx/Makefile index 0b1bd171c..2a87edb7f 100644 --- a/fpga/lib/eth/tb/axis_gmii_rx/Makefile +++ b/fpga/lib/eth/tb/axis_gmii_rx/Makefile @@ -42,10 +42,7 @@ export PARAM_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -54,10 +51,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/axis_gmii_tx/Makefile b/fpga/lib/eth/tb/axis_gmii_tx/Makefile index 29c2209fe..f97bec4ab 100644 --- a/fpga/lib/eth/tb/axis_gmii_tx/Makefile +++ b/fpga/lib/eth/tb/axis_gmii_tx/Makefile @@ -46,14 +46,7 @@ export PARAM_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_ENABLE=$(PARAM_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -62,14 +55,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GPTP_TAG_ENABLE=$(PARAM_PTP_TAG_ENABLE) - COMPILE_ARGS += -GPTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile b/fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile index 54735d907..1e978b020 100644 --- a/fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile @@ -43,12 +43,7 @@ export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -57,12 +52,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile b/fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile index 3c2ce8680..8f0d9b226 100644 --- a/fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile @@ -43,12 +43,7 @@ export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -57,12 +52,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile b/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile index dc2bb353f..3e0a0c89a 100644 --- a/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile @@ -48,17 +48,7 @@ export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_ENABLE=$(PARAM_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -67,17 +57,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GPTP_TAG_ENABLE=$(PARAM_PTP_TAG_ENABLE) - COMPILE_ARGS += -GPTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile b/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile index 3973927ed..86797aeab 100644 --- a/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile @@ -48,17 +48,7 @@ export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_ENABLE=$(PARAM_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -67,17 +57,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GPTP_TAG_ENABLE=$(PARAM_PTP_TAG_ENABLE) - COMPILE_ARGS += -GPTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_axis_rx/Makefile b/fpga/lib/eth/tb/eth_axis_rx/Makefile index 81ca7d90e..e13de5252 100644 --- a/fpga/lib/eth/tb/eth_axis_rx/Makefile +++ b/fpga/lib/eth/tb/eth_axis_rx/Makefile @@ -39,9 +39,7 @@ export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -50,9 +48,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_axis_tx/Makefile b/fpga/lib/eth/tb/eth_axis_tx/Makefile index c77d90dee..e290f7f9c 100644 --- a/fpga/lib/eth/tb/eth_axis_tx/Makefile +++ b/fpga/lib/eth/tb/eth_axis_tx/Makefile @@ -39,9 +39,7 @@ export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -50,9 +48,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_10g/Makefile b/fpga/lib/eth/tb/eth_mac_10g/Makefile index 05dc044e1..a09e617c8 100644 --- a/fpga/lib/eth/tb/eth_mac_10g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_10g/Makefile @@ -57,22 +57,7 @@ export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$ ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_WIDTH=$(PARAM_TX_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_WIDTH=$(PARAM_TX_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_WIDTH=$(PARAM_RX_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -81,22 +66,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GPTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS) - COMPILE_ARGS += -GPTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS) - COMPILE_ARGS += -GTX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -GTX_PTP_TS_WIDTH=$(PARAM_TX_PTP_TS_WIDTH) - COMPILE_ARGS += -GTX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -GTX_PTP_TAG_WIDTH=$(PARAM_TX_PTP_TAG_WIDTH) - COMPILE_ARGS += -GRX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -GRX_PTP_TS_WIDTH=$(PARAM_RX_PTP_TS_WIDTH) - COMPILE_ARGS += -GTX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -GRX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile index 493f8c194..18680e338 100644 --- a/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile @@ -77,37 +77,7 @@ export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$ ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_RAM_PIPELINE=$(PARAM_TX_FIFO_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_RAM_PIPELINE=$(PARAM_RX_FIFO_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -116,37 +86,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GTX_FIFO_RAM_PIPELINE=$(PARAM_TX_FIFO_RAM_PIPELINE) - COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FIFO_RAM_PIPELINE=$(PARAM_RX_FIFO_RAM_PIPELINE) - COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -GRX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) - COMPILE_ARGS += -GPTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS) - COMPILE_ARGS += -GPTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS) - COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) - COMPILE_ARGS += -GTX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -GRX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GTX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -GPTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -GTX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -GRX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_1g/Makefile b/fpga/lib/eth/tb/eth_mac_1g/Makefile index 4bc6be7eb..5d88a876b 100644 --- a/fpga/lib/eth/tb/eth_mac_1g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g/Makefile @@ -52,17 +52,7 @@ export PARAM_RX_USER_WIDTH ?= 1 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_WIDTH=$(PARAM_TX_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_WIDTH=$(PARAM_TX_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_WIDTH=$(PARAM_RX_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -71,17 +61,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GTX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -GTX_PTP_TS_WIDTH=$(PARAM_TX_PTP_TS_WIDTH) - COMPILE_ARGS += -GTX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -GTX_PTP_TAG_WIDTH=$(PARAM_TX_PTP_TAG_WIDTH) - COMPILE_ARGS += -GRX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -GRX_PTP_TS_WIDTH=$(PARAM_RX_PTP_TS_WIDTH) - COMPILE_ARGS += -GTX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -GRX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile index c83b4f9e3..c84ed34ec 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile @@ -58,21 +58,7 @@ export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -81,21 +67,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -GRX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile b/fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile index fed90e2ac..b8cbfe8e6 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile @@ -46,8 +46,7 @@ export PARAM_MIN_FRAME_LENGTH ?= 64 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -56,8 +55,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile index 1ce8e15e3..2494ee7c3 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile @@ -63,21 +63,7 @@ export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -86,21 +72,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -GRX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile b/fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile index 05de52f63..5fc298f0d 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile @@ -46,8 +46,7 @@ export PARAM_MIN_FRAME_LENGTH ?= 64 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -56,8 +55,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile index f3fcf8f7e..7c63de480 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile @@ -63,21 +63,7 @@ export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -86,21 +72,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -GRX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_mii/Makefile b/fpga/lib/eth/tb/eth_mac_mii/Makefile index 51720f230..d24b60470 100644 --- a/fpga/lib/eth/tb/eth_mac_mii/Makefile +++ b/fpga/lib/eth/tb/eth_mac_mii/Makefile @@ -44,8 +44,7 @@ export PARAM_MIN_FRAME_LENGTH ?= 64 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -54,8 +53,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile index 8c7619ad7..8f54d6512 100644 --- a/fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile @@ -61,21 +61,7 @@ export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -84,21 +70,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -GRX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile b/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile index 4d263e960..161b0f7de 100644 --- a/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile @@ -70,30 +70,7 @@ export PARAM_COUNT_125US ?= 195 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_WIDTH=$(PARAM_TX_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_WIDTH=$(PARAM_TX_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_WIDTH=$(PARAM_RX_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).BIT_REVERSE=$(PARAM_BIT_REVERSE) - COMPILE_ARGS += -P $(TOPLEVEL).SCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PRBS31_ENABLE=$(PARAM_PRBS31_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES) - COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES) - COMPILE_ARGS += -P $(TOPLEVEL).COUNT_125US=$(PARAM_COUNT_125US) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -102,30 +79,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) - COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GPTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS) - COMPILE_ARGS += -GPTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS) - COMPILE_ARGS += -GTX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -GTX_PTP_TS_WIDTH=$(PARAM_TX_PTP_TS_WIDTH) - COMPILE_ARGS += -GTX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -GTX_PTP_TAG_WIDTH=$(PARAM_TX_PTP_TAG_WIDTH) - COMPILE_ARGS += -GRX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -GRX_PTP_TS_WIDTH=$(PARAM_RX_PTP_TS_WIDTH) - COMPILE_ARGS += -GTX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -GRX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) - COMPILE_ARGS += -GBIT_REVERSE=$(PARAM_BIT_REVERSE) - COMPILE_ARGS += -GSCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE) - COMPILE_ARGS += -GPRBS31_ENABLE=$(PARAM_PRBS31_ENABLE) - COMPILE_ARGS += -GTX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE) - COMPILE_ARGS += -GRX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE) - COMPILE_ARGS += -GBITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES) - COMPILE_ARGS += -GBITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES) - COMPILE_ARGS += -GCOUNT_125US=$(PARAM_COUNT_125US) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile index c99e99b62..9da48b437 100644 --- a/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile @@ -90,45 +90,7 @@ export PARAM_COUNT_125US ?= 195 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_RAM_PIPELINE=$(PARAM_TX_FIFO_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_RAM_PIPELINE=$(PARAM_RX_FIFO_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).BIT_REVERSE=$(PARAM_BIT_REVERSE) - COMPILE_ARGS += -P $(TOPLEVEL).SCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PRBS31_ENABLE=$(PARAM_PRBS31_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES) - COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES) - COMPILE_ARGS += -P $(TOPLEVEL).COUNT_125US=$(PARAM_COUNT_125US) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -137,45 +99,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) - COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) - COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) - COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING) - COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) - COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) - COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GTX_FIFO_RAM_PIPELINE=$(PARAM_TX_FIFO_RAM_PIPELINE) - COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) - COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) - COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) - COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FIFO_RAM_PIPELINE=$(PARAM_RX_FIFO_RAM_PIPELINE) - COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) - COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) - COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) - COMPILE_ARGS += -GRX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL) - COMPILE_ARGS += -GPTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS) - COMPILE_ARGS += -GPTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS) - COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) - COMPILE_ARGS += -GTX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE) - COMPILE_ARGS += -GRX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE) - COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH) - COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH) - COMPILE_ARGS += -GTX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE) - COMPILE_ARGS += -GPTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH) - COMPILE_ARGS += -GTX_USER_WIDTH=$(PARAM_TX_USER_WIDTH) - COMPILE_ARGS += -GRX_USER_WIDTH=$(PARAM_RX_USER_WIDTH) - COMPILE_ARGS += -GBIT_REVERSE=$(PARAM_BIT_REVERSE) - COMPILE_ARGS += -GSCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE) - COMPILE_ARGS += -GPRBS31_ENABLE=$(PARAM_PRBS31_ENABLE) - COMPILE_ARGS += -GTX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE) - COMPILE_ARGS += -GRX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE) - COMPILE_ARGS += -GBITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES) - COMPILE_ARGS += -GBITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES) - COMPILE_ARGS += -GCOUNT_125US=$(PARAM_COUNT_125US) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/eth_phy_10g/Makefile b/fpga/lib/eth/tb/eth_phy_10g/Makefile index 18fc426bb..3ef854740 100644 --- a/fpga/lib/eth/tb/eth_phy_10g/Makefile +++ b/fpga/lib/eth/tb/eth_phy_10g/Makefile @@ -58,17 +58,7 @@ export PARAM_COUNT_125US ?= 195 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).BIT_REVERSE=$(PARAM_BIT_REVERSE) - COMPILE_ARGS += -P $(TOPLEVEL).SCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PRBS31_ENABLE=$(PARAM_PRBS31_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES) - COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES) - COMPILE_ARGS += -P $(TOPLEVEL).COUNT_125US=$(PARAM_COUNT_125US) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -77,17 +67,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH) - COMPILE_ARGS += -GBIT_REVERSE=$(PARAM_BIT_REVERSE) - COMPILE_ARGS += -GSCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE) - COMPILE_ARGS += -GPRBS31_ENABLE=$(PARAM_PRBS31_ENABLE) - COMPILE_ARGS += -GTX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE) - COMPILE_ARGS += -GRX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE) - COMPILE_ARGS += -GBITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES) - COMPILE_ARGS += -GBITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES) - COMPILE_ARGS += -GCOUNT_125US=$(PARAM_COUNT_125US) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/ptp_clock/Makefile b/fpga/lib/eth/tb/ptp_clock/Makefile index 96bd292aa..5adaf22ef 100644 --- a/fpga/lib/eth/tb/ptp_clock/Makefile +++ b/fpga/lib/eth/tb/ptp_clock/Makefile @@ -47,17 +47,7 @@ export PARAM_PIPELINE_OUTPUT ?= 0 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).PERIOD_NS_WIDTH=$(PARAM_PERIOD_NS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).OFFSET_NS_WIDTH=$(PARAM_OFFSET_NS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DRIFT_NS_WIDTH=$(PARAM_DRIFT_NS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).FNS_WIDTH=$(PARAM_FNS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PERIOD_NS=$(PARAM_PERIOD_NS) - COMPILE_ARGS += -P $(TOPLEVEL).PERIOD_FNS=$(PARAM_PERIOD_FNS) - COMPILE_ARGS += -P $(TOPLEVEL).DRIFT_ENABLE=$(PARAM_DRIFT_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DRIFT_NS=$(PARAM_DRIFT_NS) - COMPILE_ARGS += -P $(TOPLEVEL).DRIFT_FNS=$(PARAM_DRIFT_FNS) - COMPILE_ARGS += -P $(TOPLEVEL).DRIFT_RATE=$(PARAM_DRIFT_RATE) - COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -66,17 +56,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GPERIOD_NS_WIDTH=$(PARAM_PERIOD_NS_WIDTH) - COMPILE_ARGS += -GOFFSET_NS_WIDTH=$(PARAM_OFFSET_NS_WIDTH) - COMPILE_ARGS += -GDRIFT_NS_WIDTH=$(PARAM_DRIFT_NS_WIDTH) - COMPILE_ARGS += -GFNS_WIDTH=$(PARAM_FNS_WIDTH) - COMPILE_ARGS += -GPERIOD_NS=$(PARAM_PERIOD_NS) - COMPILE_ARGS += -GPERIOD_FNS=$(PARAM_PERIOD_FNS) - COMPILE_ARGS += -GDRIFT_ENABLE=$(PARAM_DRIFT_ENABLE) - COMPILE_ARGS += -GDRIFT_NS=$(PARAM_DRIFT_NS) - COMPILE_ARGS += -GDRIFT_FNS=$(PARAM_DRIFT_FNS) - COMPILE_ARGS += -GDRIFT_RATE=$(PARAM_DRIFT_RATE) - COMPILE_ARGS += -GPIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/ptp_clock_cdc/Makefile b/fpga/lib/eth/tb/ptp_clock_cdc/Makefile index eac841e16..62b4d3d0a 100644 --- a/fpga/lib/eth/tb/ptp_clock_cdc/Makefile +++ b/fpga/lib/eth/tb/ptp_clock_cdc/Makefile @@ -42,12 +42,7 @@ export PARAM_PIPELINE_OUTPUT ?= 0 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).TS_WIDTH=$(PARAM_TS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).NS_WIDTH=$(PARAM_NS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).FNS_WIDTH=$(PARAM_FNS_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).USE_SAMPLE_CLOCK=$(PARAM_USE_SAMPLE_CLOCK) - COMPILE_ARGS += -P $(TOPLEVEL).LOG_RATE=$(PARAM_LOG_RATE) - COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -56,12 +51,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GTS_WIDTH=$(PARAM_TS_WIDTH) - COMPILE_ARGS += -GNS_WIDTH=$(PARAM_NS_WIDTH) - COMPILE_ARGS += -GFNS_WIDTH=$(PARAM_FNS_WIDTH) - COMPILE_ARGS += -GUSE_SAMPLE_CLOCK=$(PARAM_USE_SAMPLE_CLOCK) - COMPILE_ARGS += -GLOG_RATE=$(PARAM_LOG_RATE) - COMPILE_ARGS += -GPIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/ptp_perout/Makefile b/fpga/lib/eth/tb/ptp_perout/Makefile index 7a6f15cb3..08536e377 100644 --- a/fpga/lib/eth/tb/ptp_perout/Makefile +++ b/fpga/lib/eth/tb/ptp_perout/Makefile @@ -46,16 +46,7 @@ export PARAM_OUT_WIDTH_FNS ?= 0 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).FNS_ENABLE=$(PARAM_FNS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_START_S=$(PARAM_OUT_START_S) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_START_NS=$(PARAM_OUT_START_NS) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_START_FNS=$(PARAM_OUT_START_FNS) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_PERIOD_S=$(PARAM_OUT_PERIOD_S) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_PERIOD_NS=$(PARAM_OUT_PERIOD_NS) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_PERIOD_FNS=$(PARAM_OUT_PERIOD_FNS) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_WIDTH_S=$(PARAM_OUT_WIDTH_S) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_WIDTH_NS=$(PARAM_OUT_WIDTH_NS) - COMPILE_ARGS += -P $(TOPLEVEL).OUT_WIDTH_FNS=$(PARAM_OUT_WIDTH_FNS) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -64,16 +55,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GFNS_ENABLE=$(PARAM_FNS_ENABLE) - COMPILE_ARGS += -GOUT_START_S=$(PARAM_OUT_START_S) - COMPILE_ARGS += -GOUT_START_NS=$(PARAM_OUT_START_NS) - COMPILE_ARGS += -GOUT_START_FNS=$(PARAM_OUT_START_FNS) - COMPILE_ARGS += -GOUT_PERIOD_S=$(PARAM_OUT_PERIOD_S) - COMPILE_ARGS += -GOUT_PERIOD_NS=$(PARAM_OUT_PERIOD_NS) - COMPILE_ARGS += -GOUT_PERIOD_FNS=$(PARAM_OUT_PERIOD_FNS) - COMPILE_ARGS += -GOUT_WIDTH_S=$(PARAM_OUT_WIDTH_S) - COMPILE_ARGS += -GOUT_WIDTH_NS=$(PARAM_OUT_WIDTH_NS) - COMPILE_ARGS += -GOUT_WIDTH_FNS=$(PARAM_OUT_WIDTH_FNS) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile b/fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile index e42536aa1..8e023a764 100644 --- a/fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile +++ b/fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile @@ -39,9 +39,7 @@ export PARAM_HDR_WIDTH ?= 2 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -50,9 +48,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile b/fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile index 81be5c525..57bf5ec22 100644 --- a/fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile +++ b/fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile @@ -39,9 +39,7 @@ export PARAM_HDR_WIDTH ?= 2 ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).CTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v @@ -50,9 +48,7 @@ ifeq ($(SIM), icarus) else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH) - COMPILE_ARGS += -GCTRL_WIDTH=$(PARAM_CTRL_WIDTH) - COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst diff --git a/fpga/lib/eth/tox.ini b/fpga/lib/eth/tox.ini index dac036b90..476b0951b 100644 --- a/fpga/lib/eth/tox.ini +++ b/fpga/lib/eth/tox.ini @@ -7,23 +7,23 @@ requires = virtualenv >= 16.1 [gh-actions] python = - 3.9: py3 + 3.10: py3 [testenv] deps = - pytest == 7.1.3 - pytest-xdist == 2.5.0 + pytest == 7.2.1 + pytest-xdist == 3.1.0 pytest-split == 0.8.0 - cocotb == 1.7.0 + cocotb == 1.7.2 cocotb-bus == 0.2.1 - cocotb-test == 0.2.2 - cocotbext-axi == 0.1.18 - cocotbext-eth == 0.1.18 - scapy == 2.4.5 + cocotb-test == 0.2.4 + cocotbext-axi == 0.1.20 + cocotbext-eth == 0.1.20 + scapy == 2.5.0 jinja2 == 3.1.2 commands = - pytest -n auto {posargs} + pytest {posargs:-n auto --verbose} # pytest configuration [pytest]