From d24c53a2add0c0981bd0c568247a5f2b3f1afddc Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 9 Sep 2021 16:01:26 -0700 Subject: [PATCH] Add application section --- fpga/app/template/lib | 1 + fpga/app/template/rtl/common | 1 + fpga/app/template/rtl/mqnic_app_block.v | 589 +++++ .../template/tb/mqnic_core_pcie_us/Makefile | 405 ++++ .../template/tb/mqnic_core_pcie_us/mqnic.py | 1 + .../test_mqnic_core_pcie_us.py | 724 +++++++ fpga/common/rtl/mqnic_core.v | 1914 +++++++++++++++-- fpga/common/rtl/mqnic_core_pcie.v | 387 +++- fpga/common/rtl/mqnic_core_pcie_us.v | 26 + fpga/common/tb/mqnic.py | 13 + fpga/common/tb/mqnic_core_pcie_us/Makefile | 40 +- .../test_mqnic_core_pcie_us.py | 44 +- fpga/mqnic/fb2CG/fpga_100g/app | 1 + fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile | 19 +- fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl | 16 + fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v | 26 + fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v | 26 + .../fb2CG/fpga_100g/tb/fpga_core/Makefile | 50 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 35 +- fpga/mqnic/fb2CG/fpga_10g/app | 1 + fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile | 19 +- fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl | 16 + fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v | 26 + fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v | 26 + .../fb2CG/fpga_10g/tb/fpga_core/Makefile | 50 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 35 +- fpga/mqnic/fb2CG/fpga_25g/app | 1 + fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile | 19 +- fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl | 16 + fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v | 26 + fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 26 + .../fb2CG/fpga_25g/tb/fpga_core/Makefile | 50 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 35 +- tox.ini | 1 + 34 files changed, 4350 insertions(+), 315 deletions(-) create mode 120000 fpga/app/template/lib create mode 120000 fpga/app/template/rtl/common create mode 100644 fpga/app/template/rtl/mqnic_app_block.v create mode 100644 fpga/app/template/tb/mqnic_core_pcie_us/Makefile create mode 120000 fpga/app/template/tb/mqnic_core_pcie_us/mqnic.py create mode 100644 fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py create mode 120000 fpga/mqnic/fb2CG/fpga_100g/app create mode 120000 fpga/mqnic/fb2CG/fpga_10g/app create mode 120000 fpga/mqnic/fb2CG/fpga_25g/app diff --git a/fpga/app/template/lib b/fpga/app/template/lib new file mode 120000 index 000000000..bc1a1ee04 --- /dev/null +++ b/fpga/app/template/lib @@ -0,0 +1 @@ +../../lib/ \ No newline at end of file diff --git a/fpga/app/template/rtl/common b/fpga/app/template/rtl/common new file mode 120000 index 000000000..e60fada70 --- /dev/null +++ b/fpga/app/template/rtl/common @@ -0,0 +1 @@ +../../../common/rtl/ \ No newline at end of file diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v new file mode 100644 index 000000000..b9c3c01a6 --- /dev/null +++ b/fpga/app/template/rtl/mqnic_app_block.v @@ -0,0 +1,589 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Application block + */ +module mqnic_app_block # +( + // Structural configuration + parameter IF_COUNT = 1, + parameter PORTS_PER_IF = 1, + + parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + + // PTP configuration + parameter PTP_TS_WIDTH = 96, + parameter PTP_TAG_WIDTH = 16, + parameter PTP_PERIOD_NS_WIDTH = 4, + parameter PTP_OFFSET_NS_WIDTH = 32, + parameter PTP_FNS_WIDTH = 32, + parameter PTP_PERIOD_NS = 4'd4, + parameter PTP_PERIOD_FNS = 32'd0, + parameter PTP_USE_SAMPLE_CLOCK = 0, + parameter PTP_PEROUT_ENABLE = 0, + parameter PTP_PEROUT_COUNT = 1, + parameter PTP_TS_ENABLE = 1, + + // Application configuration + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_ADDR_WIDTH = 64, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_SEG_COUNT = 2, + parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT, + parameter RAM_SEG_ADDR_WIDTH = 12, + parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, + parameter RAM_SEL_WIDTH = 4, + parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), + parameter RAM_PIPELINE = 2, + + // AXI lite interface (application control from host) + parameter AXIL_APP_CTRL_DATA_WIDTH = 32, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 16, + parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8), + + // AXI lite interface (control to NIC) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 16, + parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8), + + // Ethernet interface configuration (direct, async) + parameter AXIS_DATA_WIDTH = 512, + parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, + parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, + parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + parameter AXIS_RX_USE_READY = 0, + + // Ethernet interface configuration (direct, sync) + parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH, + parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/8, + parameter AXIS_SYNC_TX_USER_WIDTH = AXIS_TX_USER_WIDTH, + parameter AXIS_SYNC_RX_USER_WIDTH = AXIS_RX_USER_WIDTH, + + // Ethernet interface configuration (interface) + parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH, + parameter AXIS_IF_KEEP_WIDTH = AXIS_IF_DATA_WIDTH/8, + parameter AXIS_IF_TX_USER_WIDTH = AXIS_SYNC_TX_USER_WIDTH, + parameter AXIS_IF_RX_USER_WIDTH = AXIS_SYNC_RX_USER_WIDTH, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + input wire clk, + input wire rst, + + /* + * AXI-Lite slave interface (control from host) + */ + input wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] s_axil_app_ctrl_awaddr, + input wire [2:0] s_axil_app_ctrl_awprot, + input wire s_axil_app_ctrl_awvalid, + output wire s_axil_app_ctrl_awready, + input wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] s_axil_app_ctrl_wdata, + input wire [AXIL_APP_CTRL_STRB_WIDTH-1:0] s_axil_app_ctrl_wstrb, + input wire s_axil_app_ctrl_wvalid, + output wire s_axil_app_ctrl_wready, + output wire [1:0] s_axil_app_ctrl_bresp, + output wire s_axil_app_ctrl_bvalid, + input wire s_axil_app_ctrl_bready, + input wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] s_axil_app_ctrl_araddr, + input wire [2:0] s_axil_app_ctrl_arprot, + input wire s_axil_app_ctrl_arvalid, + output wire s_axil_app_ctrl_arready, + output wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] s_axil_app_ctrl_rdata, + output wire [1:0] s_axil_app_ctrl_rresp, + output wire s_axil_app_ctrl_rvalid, + input wire s_axil_app_ctrl_rready, + + /* + * AXI-Lite master interface (control to NIC) + */ + output wire [AXIL_CTRL_ADDR_WIDTH-1:0] m_axil_ctrl_awaddr, + output wire [2:0] m_axil_ctrl_awprot, + output wire m_axil_ctrl_awvalid, + input wire m_axil_ctrl_awready, + output wire [AXIL_CTRL_DATA_WIDTH-1:0] m_axil_ctrl_wdata, + output wire [AXIL_CTRL_STRB_WIDTH-1:0] m_axil_ctrl_wstrb, + output wire m_axil_ctrl_wvalid, + input wire m_axil_ctrl_wready, + input wire [1:0] m_axil_ctrl_bresp, + input wire m_axil_ctrl_bvalid, + output wire m_axil_ctrl_bready, + output wire [AXIL_CTRL_ADDR_WIDTH-1:0] m_axil_ctrl_araddr, + output wire [2:0] m_axil_ctrl_arprot, + output wire m_axil_ctrl_arvalid, + input wire m_axil_ctrl_arready, + input wire [AXIL_CTRL_DATA_WIDTH-1:0] m_axil_ctrl_rdata, + input wire [1:0] m_axil_ctrl_rresp, + input wire m_axil_ctrl_rvalid, + output wire m_axil_ctrl_rready, + + /* + * DMA read descriptor output (control) + */ + output wire [DMA_ADDR_WIDTH-1:0] m_axis_ctrl_dma_read_desc_dma_addr, + output wire [RAM_SEL_WIDTH-1:0] m_axis_ctrl_dma_read_desc_ram_sel, + output wire [RAM_ADDR_WIDTH-1:0] m_axis_ctrl_dma_read_desc_ram_addr, + output wire [DMA_LEN_WIDTH-1:0] m_axis_ctrl_dma_read_desc_len, + output wire [DMA_TAG_WIDTH-1:0] m_axis_ctrl_dma_read_desc_tag, + output wire m_axis_ctrl_dma_read_desc_valid, + input wire m_axis_ctrl_dma_read_desc_ready, + + /* + * DMA read descriptor status input (control) + */ + input wire [DMA_TAG_WIDTH-1:0] s_axis_ctrl_dma_read_desc_status_tag, + input wire [3:0] s_axis_ctrl_dma_read_desc_status_error, + input wire s_axis_ctrl_dma_read_desc_status_valid, + + /* + * DMA write descriptor output (control) + */ + output wire [DMA_ADDR_WIDTH-1:0] m_axis_ctrl_dma_write_desc_dma_addr, + output wire [RAM_SEL_WIDTH-1:0] m_axis_ctrl_dma_write_desc_ram_sel, + output wire [RAM_ADDR_WIDTH-1:0] m_axis_ctrl_dma_write_desc_ram_addr, + output wire [DMA_LEN_WIDTH-1:0] m_axis_ctrl_dma_write_desc_len, + output wire [DMA_TAG_WIDTH-1:0] m_axis_ctrl_dma_write_desc_tag, + output wire m_axis_ctrl_dma_write_desc_valid, + input wire m_axis_ctrl_dma_write_desc_ready, + + /* + * DMA write descriptor status input (control) + */ + input wire [DMA_TAG_WIDTH-1:0] s_axis_ctrl_dma_write_desc_status_tag, + input wire [3:0] s_axis_ctrl_dma_write_desc_status_error, + input wire s_axis_ctrl_dma_write_desc_status_valid, + + /* + * DMA read descriptor output (data) + */ + output wire [DMA_ADDR_WIDTH-1:0] m_axis_data_dma_read_desc_dma_addr, + output wire [RAM_SEL_WIDTH-1:0] m_axis_data_dma_read_desc_ram_sel, + output wire [RAM_ADDR_WIDTH-1:0] m_axis_data_dma_read_desc_ram_addr, + output wire [DMA_LEN_WIDTH-1:0] m_axis_data_dma_read_desc_len, + output wire [DMA_TAG_WIDTH-1:0] m_axis_data_dma_read_desc_tag, + output wire m_axis_data_dma_read_desc_valid, + input wire m_axis_data_dma_read_desc_ready, + + /* + * DMA read descriptor status input (data) + */ + input wire [DMA_TAG_WIDTH-1:0] s_axis_data_dma_read_desc_status_tag, + input wire [3:0] s_axis_data_dma_read_desc_status_error, + input wire s_axis_data_dma_read_desc_status_valid, + + /* + * DMA write descriptor output (data) + */ + output wire [DMA_ADDR_WIDTH-1:0] m_axis_data_dma_write_desc_dma_addr, + output wire [RAM_SEL_WIDTH-1:0] m_axis_data_dma_write_desc_ram_sel, + output wire [RAM_ADDR_WIDTH-1:0] m_axis_data_dma_write_desc_ram_addr, + output wire [DMA_LEN_WIDTH-1:0] m_axis_data_dma_write_desc_len, + output wire [DMA_TAG_WIDTH-1:0] m_axis_data_dma_write_desc_tag, + output wire m_axis_data_dma_write_desc_valid, + input wire m_axis_data_dma_write_desc_ready, + + /* + * DMA write descriptor status input (data) + */ + input wire [DMA_TAG_WIDTH-1:0] s_axis_data_dma_write_desc_status_tag, + input wire [3:0] s_axis_data_dma_write_desc_status_error, + input wire s_axis_data_dma_write_desc_status_valid, + + /* + * DMA RAM interface (control) + */ + input wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ctrl_dma_ram_wr_cmd_sel, + input wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be, + input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr, + input wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data, + input wire [RAM_SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid, + output wire [RAM_SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready, + output wire [RAM_SEG_COUNT-1:0] ctrl_dma_ram_wr_done, + input wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ctrl_dma_ram_rd_cmd_sel, + input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr, + input wire [RAM_SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid, + output wire [RAM_SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready, + output wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data, + output wire [RAM_SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid, + input wire [RAM_SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready, + + /* + * DMA RAM interface (data) + */ + input wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] data_dma_ram_wr_cmd_sel, + input wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be, + input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr, + input wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data, + input wire [RAM_SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid, + output wire [RAM_SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready, + output wire [RAM_SEG_COUNT-1:0] data_dma_ram_wr_done, + input wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] data_dma_ram_rd_cmd_sel, + input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr, + input wire [RAM_SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid, + output wire [RAM_SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready, + output wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data, + output wire [RAM_SEG_COUNT-1:0] data_dma_ram_rd_resp_valid, + input wire [RAM_SEG_COUNT-1:0] data_dma_ram_rd_resp_ready, + + /* + * PTP clock + */ + input wire ptp_sample_clk, + input wire ptp_pps, + input wire [PTP_TS_WIDTH-1:0] ptp_ts_96, + input wire ptp_ts_step, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, + + /* + * Ethernet (direct MAC interface - lowest latency raw traffic) + */ + input wire [PORT_COUNT-1:0] direct_tx_clk, + input wire [PORT_COUNT-1:0] direct_tx_rst, + + input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_direct_tx_tdata, + input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_direct_tx_tkeep, + input wire [PORT_COUNT-1:0] s_axis_direct_tx_tvalid, + output wire [PORT_COUNT-1:0] s_axis_direct_tx_tready, + input wire [PORT_COUNT-1:0] s_axis_direct_tx_tlast, + input wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] s_axis_direct_tx_tuser, + + output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_direct_tx_tdata, + output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_direct_tx_tkeep, + output wire [PORT_COUNT-1:0] m_axis_direct_tx_tvalid, + input wire [PORT_COUNT-1:0] m_axis_direct_tx_tready, + output wire [PORT_COUNT-1:0] m_axis_direct_tx_tlast, + output wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] m_axis_direct_tx_tuser, + + input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_direct_tx_ptp_ts, + input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_direct_tx_ptp_ts_tag, + input wire [PORT_COUNT-1:0] s_axis_direct_tx_ptp_ts_valid, + output wire [PORT_COUNT-1:0] s_axis_direct_tx_ptp_ts_ready, + + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_direct_tx_ptp_ts, + output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_direct_tx_ptp_ts_tag, + output wire [PORT_COUNT-1:0] m_axis_direct_tx_ptp_ts_valid, + input wire [PORT_COUNT-1:0] m_axis_direct_tx_ptp_ts_ready, + + input wire [PORT_COUNT-1:0] direct_rx_clk, + input wire [PORT_COUNT-1:0] direct_rx_rst, + + input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_direct_rx_tdata, + input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_direct_rx_tkeep, + input wire [PORT_COUNT-1:0] s_axis_direct_rx_tvalid, + output wire [PORT_COUNT-1:0] s_axis_direct_rx_tready, + input wire [PORT_COUNT-1:0] s_axis_direct_rx_tlast, + input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_direct_rx_tuser, + + output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_direct_rx_tdata, + output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_direct_rx_tkeep, + output wire [PORT_COUNT-1:0] m_axis_direct_rx_tvalid, + input wire [PORT_COUNT-1:0] m_axis_direct_rx_tready, + output wire [PORT_COUNT-1:0] m_axis_direct_rx_tlast, + output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] m_axis_direct_rx_tuser, + + /* + * Ethernet (synchronous MAC interface - low latency raw traffic) + */ + input wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] s_axis_sync_tx_tdata, + input wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_sync_tx_tkeep, + input wire [PORT_COUNT-1:0] s_axis_sync_tx_tvalid, + output wire [PORT_COUNT-1:0] s_axis_sync_tx_tready, + input wire [PORT_COUNT-1:0] s_axis_sync_tx_tlast, + input wire [PORT_COUNT*AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_sync_tx_tuser, + + output wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] m_axis_sync_tx_tdata, + output wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_sync_tx_tkeep, + output wire [PORT_COUNT-1:0] m_axis_sync_tx_tvalid, + input wire [PORT_COUNT-1:0] m_axis_sync_tx_tready, + output wire [PORT_COUNT-1:0] m_axis_sync_tx_tlast, + output wire [PORT_COUNT*AXIS_SYNC_TX_USER_WIDTH-1:0] m_axis_sync_tx_tuser, + + input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_sync_tx_ptp_ts, + input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_sync_tx_ptp_ts_tag, + input wire [PORT_COUNT-1:0] s_axis_sync_tx_ptp_ts_valid, + output wire [PORT_COUNT-1:0] s_axis_sync_tx_ptp_ts_ready, + + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_sync_tx_ptp_ts, + output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_sync_tx_ptp_ts_tag, + output wire [PORT_COUNT-1:0] m_axis_sync_tx_ptp_ts_valid, + input wire [PORT_COUNT-1:0] m_axis_sync_tx_ptp_ts_ready, + + input wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] s_axis_sync_rx_tdata, + input wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_sync_rx_tkeep, + input wire [PORT_COUNT-1:0] s_axis_sync_rx_tvalid, + output wire [PORT_COUNT-1:0] s_axis_sync_rx_tready, + input wire [PORT_COUNT-1:0] s_axis_sync_rx_tlast, + input wire [PORT_COUNT*AXIS_SYNC_RX_USER_WIDTH-1:0] s_axis_sync_rx_tuser, + + output wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] m_axis_sync_rx_tdata, + output wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_sync_rx_tkeep, + output wire [PORT_COUNT-1:0] m_axis_sync_rx_tvalid, + input wire [PORT_COUNT-1:0] m_axis_sync_rx_tready, + output wire [PORT_COUNT-1:0] m_axis_sync_rx_tlast, + output wire [PORT_COUNT*AXIS_SYNC_RX_USER_WIDTH-1:0] m_axis_sync_rx_tuser, + + /* + * Ethernet (internal at interface module) + */ + input wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_tx_tdata, + input wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_tx_tkeep, + input wire [PORT_COUNT-1:0] s_axis_if_tx_tvalid, + output wire [PORT_COUNT-1:0] s_axis_if_tx_tready, + input wire [PORT_COUNT-1:0] s_axis_if_tx_tlast, + input wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser, + + output wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_tx_tdata, + output wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_tx_tkeep, + output wire [PORT_COUNT-1:0] m_axis_if_tx_tvalid, + input wire [PORT_COUNT-1:0] m_axis_if_tx_tready, + output wire [PORT_COUNT-1:0] m_axis_if_tx_tlast, + output wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] m_axis_if_tx_tuser, + + input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_ptp_ts, + input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_if_tx_ptp_ts_tag, + input wire [PORT_COUNT-1:0] s_axis_if_tx_ptp_ts_valid, + output wire [PORT_COUNT-1:0] s_axis_if_tx_ptp_ts_ready, + + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts, + output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag, + output wire [PORT_COUNT-1:0] m_axis_if_tx_ptp_ts_valid, + input wire [PORT_COUNT-1:0] m_axis_if_tx_ptp_ts_ready, + + input wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_rx_tdata, + input wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_rx_tkeep, + input wire [PORT_COUNT-1:0] s_axis_if_rx_tvalid, + output wire [PORT_COUNT-1:0] s_axis_if_rx_tready, + input wire [PORT_COUNT-1:0] s_axis_if_rx_tlast, + input wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] s_axis_if_rx_tuser, + + output wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_rx_tdata, + output wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_rx_tkeep, + output wire [PORT_COUNT-1:0] m_axis_if_rx_tvalid, + input wire [PORT_COUNT-1:0] m_axis_if_rx_tready, + output wire [PORT_COUNT-1:0] m_axis_if_rx_tlast, + output wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser, + + /* + * Statistics increment output + */ + output wire [STAT_INC_WIDTH-1:0] m_axis_stat_tdata, + output wire [STAT_ID_WIDTH-1:0] m_axis_stat_tid, + output wire m_axis_stat_tvalid, + input wire m_axis_stat_tready +); + +/* + * AXI-Lite slave interface (control from host) + */ +axil_ram #( + .DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .ADDR_WIDTH(12), + .STRB_WIDTH(AXIL_APP_CTRL_STRB_WIDTH), + .PIPELINE_OUTPUT(1) +) +ram_inst ( + .clk(clk), + .rst(rst), + + .s_axil_awaddr(s_axil_app_ctrl_awaddr), + .s_axil_awprot(s_axil_app_ctrl_awprot), + .s_axil_awvalid(s_axil_app_ctrl_awvalid), + .s_axil_awready(s_axil_app_ctrl_awready), + .s_axil_wdata(s_axil_app_ctrl_wdata), + .s_axil_wstrb(s_axil_app_ctrl_wstrb), + .s_axil_wvalid(s_axil_app_ctrl_wvalid), + .s_axil_wready(s_axil_app_ctrl_wready), + .s_axil_bresp(s_axil_app_ctrl_bresp), + .s_axil_bvalid(s_axil_app_ctrl_bvalid), + .s_axil_bready(s_axil_app_ctrl_bready), + .s_axil_araddr(s_axil_app_ctrl_araddr), + .s_axil_arprot(s_axil_app_ctrl_arprot), + .s_axil_arvalid(s_axil_app_ctrl_arvalid), + .s_axil_arready(s_axil_app_ctrl_arready), + .s_axil_rdata(s_axil_app_ctrl_rdata), + .s_axil_rresp(s_axil_app_ctrl_rresp), + .s_axil_rvalid(s_axil_app_ctrl_rvalid), + .s_axil_rready(s_axil_app_ctrl_rready) +); + +/* + * AXI-Lite master interface (control to NIC) + */ +assign m_axil_ctrl_awaddr = 0; +assign m_axil_ctrl_awprot = 0; +assign m_axil_ctrl_awvalid = 1'b0; +assign m_axil_ctrl_wdata = 0; +assign m_axil_ctrl_wstrb = 0; +assign m_axil_ctrl_wvalid = 1'b0; +assign m_axil_ctrl_bready = 1'b1; +assign m_axil_ctrl_araddr = 0; +assign m_axil_ctrl_arprot = 0; +assign m_axil_ctrl_arvalid = 1'b0; +assign m_axil_ctrl_rready = 1'b1; + +/* + * Ethernet (direct MAC interface - lowest latency raw traffic) + */ +assign m_axis_direct_tx_tdata = s_axis_direct_tx_tdata; +assign m_axis_direct_tx_tkeep = s_axis_direct_tx_tkeep; +assign m_axis_direct_tx_tvalid = s_axis_direct_tx_tvalid; +assign s_axis_direct_tx_tready = m_axis_direct_tx_tready; +assign m_axis_direct_tx_tlast = s_axis_direct_tx_tlast; +assign m_axis_direct_tx_tuser = s_axis_direct_tx_tuser; + +assign m_axis_direct_tx_ptp_ts = s_axis_direct_tx_ptp_ts; +assign m_axis_direct_tx_ptp_ts_tag = s_axis_direct_tx_ptp_ts_tag; +assign m_axis_direct_tx_ptp_ts_valid = s_axis_direct_tx_ptp_ts_valid; +assign s_axis_direct_tx_ptp_ts_ready = m_axis_direct_tx_ptp_ts_ready; + +assign m_axis_direct_rx_tdata = s_axis_direct_rx_tdata; +assign m_axis_direct_rx_tkeep = s_axis_direct_rx_tkeep; +assign m_axis_direct_rx_tvalid = s_axis_direct_rx_tvalid; +assign s_axis_direct_rx_tready = m_axis_direct_rx_tready; +assign m_axis_direct_rx_tlast = s_axis_direct_rx_tlast; +assign m_axis_direct_rx_tuser = s_axis_direct_rx_tuser; + +/* + * Ethernet (synchronous MAC interface - low latency raw traffic) + */ +assign m_axis_sync_tx_tdata = s_axis_sync_tx_tdata; +assign m_axis_sync_tx_tkeep = s_axis_sync_tx_tkeep; +assign m_axis_sync_tx_tvalid = s_axis_sync_tx_tvalid; +assign s_axis_sync_tx_tready = m_axis_sync_tx_tready; +assign m_axis_sync_tx_tlast = s_axis_sync_tx_tlast; +assign m_axis_sync_tx_tuser = s_axis_sync_tx_tuser; + +assign m_axis_sync_tx_ptp_ts = s_axis_sync_tx_ptp_ts; +assign m_axis_sync_tx_ptp_ts_tag = s_axis_sync_tx_ptp_ts_tag; +assign m_axis_sync_tx_ptp_ts_valid = s_axis_sync_tx_ptp_ts_valid; +assign s_axis_sync_tx_ptp_ts_ready = m_axis_sync_tx_ptp_ts_ready; + +assign m_axis_sync_rx_tdata = s_axis_sync_rx_tdata; +assign m_axis_sync_rx_tkeep = s_axis_sync_rx_tkeep; +assign m_axis_sync_rx_tvalid = s_axis_sync_rx_tvalid; +assign s_axis_sync_rx_tready = m_axis_sync_rx_tready; +assign m_axis_sync_rx_tlast = s_axis_sync_rx_tlast; +assign m_axis_sync_rx_tuser = s_axis_sync_rx_tuser; + +/* + * Ethernet (internal at interface module) + */ +assign m_axis_if_tx_tdata = s_axis_if_tx_tdata; +assign m_axis_if_tx_tkeep = s_axis_if_tx_tkeep; +assign m_axis_if_tx_tvalid = s_axis_if_tx_tvalid; +assign s_axis_if_tx_tready = m_axis_if_tx_tready; +assign m_axis_if_tx_tlast = s_axis_if_tx_tlast; +assign m_axis_if_tx_tuser = s_axis_if_tx_tuser; + +assign m_axis_if_tx_ptp_ts = s_axis_if_tx_ptp_ts; +assign m_axis_if_tx_ptp_ts_tag = s_axis_if_tx_ptp_ts_tag; +assign m_axis_if_tx_ptp_ts_valid = s_axis_if_tx_ptp_ts_valid; +assign s_axis_if_tx_ptp_ts_ready = m_axis_if_tx_ptp_ts_ready; + +assign m_axis_if_rx_tdata = s_axis_if_rx_tdata; +assign m_axis_if_rx_tkeep = s_axis_if_rx_tkeep; +assign m_axis_if_rx_tvalid = s_axis_if_rx_tvalid; +assign s_axis_if_rx_tready = m_axis_if_rx_tready; +assign m_axis_if_rx_tlast = s_axis_if_rx_tlast; +assign m_axis_if_rx_tuser = s_axis_if_rx_tuser; + +/* + * DMA interface (control) + */ +assign m_axis_ctrl_dma_read_desc_dma_addr = 0; +assign m_axis_ctrl_dma_read_desc_ram_sel = 0; +assign m_axis_ctrl_dma_read_desc_ram_addr = 0; +assign m_axis_ctrl_dma_read_desc_len = 0; +assign m_axis_ctrl_dma_read_desc_tag = 0; +assign m_axis_ctrl_dma_read_desc_valid = 1'b0; +assign m_axis_ctrl_dma_write_desc_dma_addr = 0; +assign m_axis_ctrl_dma_write_desc_ram_sel = 0; +assign m_axis_ctrl_dma_write_desc_ram_addr = 0; +assign m_axis_ctrl_dma_write_desc_len = 0; +assign m_axis_ctrl_dma_write_desc_tag = 0; +assign m_axis_ctrl_dma_write_desc_valid = 1'b0; + +assign ctrl_dma_ram_wr_cmd_ready = 1'b1; +assign ctrl_dma_ram_wr_done = ctrl_dma_ram_wr_cmd_valid; +assign ctrl_dma_ram_rd_cmd_ready = ctrl_dma_ram_rd_resp_ready; +assign ctrl_dma_ram_rd_resp_data = 0; +assign ctrl_dma_ram_rd_resp_valid = ctrl_dma_ram_rd_cmd_valid; + +/* + * DMA interface (data) + */ +assign m_axis_data_dma_read_desc_dma_addr = 0; +assign m_axis_data_dma_read_desc_ram_sel = 0; +assign m_axis_data_dma_read_desc_ram_addr = 0; +assign m_axis_data_dma_read_desc_len = 0; +assign m_axis_data_dma_read_desc_tag = 0; +assign m_axis_data_dma_read_desc_valid = 1'b0; +assign m_axis_data_dma_write_desc_dma_addr = 0; +assign m_axis_data_dma_write_desc_ram_sel = 0; +assign m_axis_data_dma_write_desc_ram_addr = 0; +assign m_axis_data_dma_write_desc_len = 0; +assign m_axis_data_dma_write_desc_tag = 0; +assign m_axis_data_dma_write_desc_valid = 1'b0; + +assign data_dma_ram_wr_cmd_ready = 1'b1; +assign data_dma_ram_wr_done = data_dma_ram_wr_cmd_valid; +assign data_dma_ram_rd_cmd_ready = data_dma_ram_rd_resp_ready; +assign data_dma_ram_rd_resp_data = 0; +assign data_dma_ram_rd_resp_valid = data_dma_ram_rd_cmd_valid; + +/* + * Statistics increment output + */ +assign m_axis_stat_tdata = 0; +assign m_axis_stat_tid = 0; +assign m_axis_stat_tvalid = 1'b0; + +endmodule diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile new file mode 100644 index 000000000..5ad370b7a --- /dev/null +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -0,0 +1,405 @@ +# Copyright 2021, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = mqnic_core_pcie_us +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/common/$(DUT).v +VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v +VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/cpl_write.v +VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v +VERILOG_SOURCES += ../../rtl/common/desc_fetch.v +VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/common/event_mux.v +VERILOG_SOURCES += ../../rtl/common/queue_manager.v +VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_engine.v +VERILOG_SOURCES += ../../rtl/common/rx_engine.v +VERILOG_SOURCES += ../../rtl/common/tx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rx_hash.v +VERILOG_SOURCES += ../../rtl/common/rx_checksum.v +VERILOG_SOURCES += ../../rtl/common/stats_counter.v +VERILOG_SOURCES += ../../rtl/common/stats_collect.v +VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v +VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v +VERILOG_SOURCES += ../../rtl/mqnic_app_block.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_ts_extract.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_ram.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v +VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v + +# module parameters + +# Structural configuration +export PARAM_IF_COUNT ?= 1 +export PARAM_PORTS_PER_IF ?= 1 + +# PTP configuration +export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0 +export PARAM_PTP_PEROUT_ENABLE ?= 0 +export PARAM_PTP_PEROUT_COUNT ?= 1 + +# Queue manager configuration (interface) +export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32 +export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32 +export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 +export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) +export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) +export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 +export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 +export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) +export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH) +export PARAM_EVENT_QUEUE_PIPELINE ?= 3 +export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE) + +# TX and RX engine configuration (port) +export PARAM_TX_DESC_TABLE_SIZE ?= 32 +export PARAM_RX_DESC_TABLE_SIZE ?= 32 + +# Scheduler configuration (port) +export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE) +export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_TDMA_INDEX_WIDTH ?= 6 + +# Timestamping configuration (port) +export PARAM_PTP_TS_ENABLE ?= 1 +export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32 +export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32 + +# Interface configuration (port) +export PARAM_TX_CHECKSUM_ENABLE ?= 1 +export PARAM_RX_RSS_ENABLE ?= 1 +export PARAM_RX_HASH_ENABLE ?= 1 +export PARAM_RX_CHECKSUM_ENABLE ?= 1 +export PARAM_TX_FIFO_DEPTH ?= 32768 +export PARAM_RX_FIFO_DEPTH ?= 131072 +export PARAM_MAX_TX_SIZE ?= 9214 +export PARAM_MAX_RX_SIZE ?= 9214 +export PARAM_TX_RAM_SIZE ?= 131072 +export PARAM_RX_RAM_SIZE ?= 131072 + +# Application block configuration +export PARAM_APP_ENABLE ?= 1 +export PARAM_APP_CTRL_ENABLE ?= 1 +export PARAM_APP_DMA_ENABLE ?= 1 +export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1 +export PARAM_APP_AXIS_SYNC_ENABLE ?= 1 +export PARAM_APP_AXIS_IF_ENABLE ?= 1 +export PARAM_APP_STAT_ENABLE ?= 1 + +# DMA interface configuration +export PARAM_DMA_LEN_WIDTH ?= 16 +export PARAM_DMA_TAG_WIDTH ?= 16 +export PARAM_RAM_PIPELINE ?= 2 + +# PCIe interface configuration +export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 +export PARAM_PF_COUNT ?= 1 +export PARAM_VF_COUNT ?= 0 +export PARAM_PCIE_TAG_COUNT ?= 64 +export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) +export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16 +export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1 +export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16 +export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 +export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 +export PARAM_MSI_COUNT ?= 32 + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 +export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 +export PARAM_AXIL_CSR_PASSTHROUGH_ENABLE ?= 0 + +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24 + +# Ethernet interface configuration +export PARAM_AXIS_ETH_DATA_WIDTH ?= 512 +export PARAM_AXIS_ETH_SYNC_DATA_WIDTH ?= $(PARAM_AXIS_ETH_DATA_WIDTH) +export PARAM_AXIS_ETH_RX_USE_READY ?= 0 +export PARAM_AXIS_ETH_TX_PIPELINE ?= 0 +export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2 +export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 0 +export PARAM_AXIS_ETH_RX_PIPELINE ?= 0 +export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 2 + +# Statistics counter subsystem +export PARAM_STAT_ENABLE ?= 1 +export PARAM_STAT_DMA_ENABLE ?= 1 +export PARAM_STAT_PCIE_ENABLE ?= 1 +export PARAM_STAT_INC_WIDTH ?= 24 +export PARAM_STAT_ID_WIDTH ?= 12 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH) + COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) + COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) + COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).VF_COUNT=$(PARAM_VF_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT) + COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) + COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).MSI_COUNT=$(PARAM_MSI_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_DATA_WIDTH=$(PARAM_AXIS_ETH_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_SYNC_DATA_WIDTH=$(PARAM_AXIS_ETH_SYNC_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_USE_READY=$(PARAM_AXIS_ETH_RX_USE_READY) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) + COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) + COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) + COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE) + COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT) + COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE) + COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE) + COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE) + COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE) + COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE) + COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE) + COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE) + COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE) + COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE) + COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH) + COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) + COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH) + COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH) + COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) + COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) + COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) + COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) + COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) + COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) + COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE) + COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) + COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) + COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) + COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) + COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) + COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) + COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH) + COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT) + COMPILE_ARGS += -GVF_COUNT=$(PARAM_VF_COUNT) + COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) + COMPILE_ARGS += -GPCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE) + COMPILE_ARGS += -GPCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT) + COMPILE_ARGS += -GPCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE) + COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) + COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) + COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) + COMPILE_ARGS += -GMSI_COUNT=$(PARAM_MSI_COUNT) + COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) + COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) + COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -GAXIS_ETH_DATA_WIDTH=$(PARAM_AXIS_ETH_DATA_WIDTH) + COMPILE_ARGS += -GAXIS_ETH_SYNC_DATA_WIDTH=$(PARAM_AXIS_ETH_SYNC_DATA_WIDTH) + COMPILE_ARGS += -GAXIS_ETH_RX_USE_READY=$(PARAM_AXIS_ETH_RX_USE_READY) + COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) + COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) + COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) + COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE) + COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE) + COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE) + COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE) + COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE) + COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH) + COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/mqnic.py b/fpga/app/template/tb/mqnic_core_pcie_us/mqnic.py new file mode 120000 index 000000000..f2c96aec4 --- /dev/null +++ b/fpga/app/template/tb/mqnic_core_pcie_us/mqnic.py @@ -0,0 +1 @@ +../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py new file mode 100644 index 000000000..54221149e --- /dev/null +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -0,0 +1,724 @@ +""" + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +""" + +import logging +import os +import sys + +import scapy.utils +from scapy.layers.l2 import Ether +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer + +from cocotbext.axi import AxiStreamBus +from cocotbext.eth import EthMac +from cocotbext.pcie.core import RootComplex +from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice + +try: + import mqnic +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + import mqnic + finally: + del sys.path[0] + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # PCIe + self.rc = RootComplex() + + self.rc.max_payload_size = 0x1 # 256 bytes + self.rc.max_read_request_size = 0x2 # 512 bytes + + self.dev = UltraScalePlusPcieDevice( + # configuration options + pcie_generation=3, + # pcie_link_width=16, + user_clk_frequency=250e6, + alignment="dword", + cq_cc_straddle=False, + rq_rc_straddle=False, + rc_4tlp_straddle=False, + enable_pf1=False, + enable_client_tag=True, + enable_extended_tag=True, + enable_parity=False, + enable_rx_msg_interface=False, + enable_sriov=False, + enable_extended_configuration=False, + + enable_pf0_msi=True, + enable_pf1_msi=False, + + # signals + # Clock and Reset Interface + user_clk=dut.clk, + user_reset=dut.rst, + # user_lnk_up + # sys_clk + # sys_clk_gt + # sys_reset + # phy_rdy_out + + # Requester reQuest Interface + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), + pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, + pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, + pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, + pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, + # pcie_rq_tag0 + # pcie_rq_tag1 + # pcie_rq_tag_av + # pcie_rq_tag_vld0 + # pcie_rq_tag_vld1 + + # Requester Completion Interface + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), + + # Completer reQuest Interface + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), + # pcie_cq_np_req + # pcie_cq_np_req_count + + # Completer Completion Interface + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), + + # Transmit Flow Control Interface + # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, + # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, + + # Configuration Management Interface + cfg_mgmt_addr=dut.cfg_mgmt_addr, + cfg_mgmt_function_number=dut.cfg_mgmt_function_number, + cfg_mgmt_write=dut.cfg_mgmt_write, + cfg_mgmt_write_data=dut.cfg_mgmt_write_data, + cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, + cfg_mgmt_read=dut.cfg_mgmt_read, + cfg_mgmt_read_data=dut.cfg_mgmt_read_data, + cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, + # cfg_mgmt_debug_access + + # Configuration Status Interface + # cfg_phy_link_down + # cfg_phy_link_status + # cfg_negotiated_width + # cfg_current_speed + cfg_max_payload=dut.cfg_max_payload, + cfg_max_read_req=dut.cfg_max_read_req, + # cfg_function_status + # cfg_vf_status + # cfg_function_power_state + # cfg_vf_power_state + # cfg_link_power_state + # cfg_err_cor_out + # cfg_err_nonfatal_out + # cfg_err_fatal_out + # cfg_local_error_out + # cfg_local_error_valid + # cfg_rx_pm_state + # cfg_tx_pm_state + # cfg_ltssm_state + # cfg_rcb_status + # cfg_obff_enable + # cfg_pl_status_change + # cfg_tph_requester_enable + # cfg_tph_st_mode + # cfg_vf_tph_requester_enable + # cfg_vf_tph_st_mode + + # Configuration Received Message Interface + # cfg_msg_received + # cfg_msg_received_data + # cfg_msg_received_type + + # Configuration Transmit Message Interface + # cfg_msg_transmit + # cfg_msg_transmit_type + # cfg_msg_transmit_data + # cfg_msg_transmit_done + + # Configuration Flow Control Interface + cfg_fc_ph=dut.cfg_fc_ph, + cfg_fc_pd=dut.cfg_fc_pd, + cfg_fc_nph=dut.cfg_fc_nph, + cfg_fc_npd=dut.cfg_fc_npd, + cfg_fc_cplh=dut.cfg_fc_cplh, + cfg_fc_cpld=dut.cfg_fc_cpld, + cfg_fc_sel=dut.cfg_fc_sel, + + # Configuration Control Interface + # cfg_hot_reset_in + # cfg_hot_reset_out + # cfg_config_space_enable + # cfg_dsn + # cfg_bus_number + # cfg_ds_port_number + # cfg_ds_bus_number + # cfg_ds_device_number + # cfg_ds_function_number + # cfg_power_state_change_ack + # cfg_power_state_change_interrupt + cfg_err_cor_in=dut.status_error_cor, + cfg_err_uncor_in=dut.status_error_uncor, + # cfg_flr_in_process + # cfg_flr_done + # cfg_vf_flr_in_process + # cfg_vf_flr_func_num + # cfg_vf_flr_done + # cfg_pm_aspm_l1_entry_reject + # cfg_pm_aspm_tx_l0s_entry_disable + # cfg_req_pm_transition_l23_ready + # cfg_link_training_enable + + # Configuration Interrupt Controller Interface + # cfg_interrupt_int + # cfg_interrupt_sent + # cfg_interrupt_pending + cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, + cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, + # cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, + cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, + cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, + # cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, + # cfg_interrupt_msix_enable + # cfg_interrupt_msix_mask + # cfg_interrupt_msix_vf_enable + # cfg_interrupt_msix_vf_mask + # cfg_interrupt_msix_address + # cfg_interrupt_msix_data + # cfg_interrupt_msix_int + # cfg_interrupt_msix_vec_pending + # cfg_interrupt_msix_vec_pending_status + cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, + # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, + # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, + + # Configuration Extend Interface + # cfg_ext_read_received + # cfg_ext_write_received + # cfg_ext_register_number + # cfg_ext_function_number + # cfg_ext_write_data + # cfg_ext_write_byte_enable + # cfg_ext_read_data + # cfg_ext_read_data_valid + ) + + # self.dev.log.setLevel(logging.DEBUG) + + self.rc.make_port().connect(self.dev) + + self.driver = mqnic.Driver(self.rc) + + self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 + + self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + + # Ethernet + self.port_mac = [] + + clock_period = 3.102 + speed = 10e9 + + if len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 64: + # 10G + clock_period = 6.4 + speed = 10e9 + elif len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 128: + # 25G + clock_period = 2.56 + speed = 25e9 + elif len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 512: + # 100G + clock_period = 3.102 + speed = 100e9 + + for iface in dut.core_pcie_inst.core_inst.iface: + for port in iface.port: + cocotb.fork(Clock(port.rx_async_fifo_inst.s_clk, clock_period, units="ns").start()) + cocotb.fork(Clock(port.tx_async_fifo_inst.m_clk, clock_period, units="ns").start()) + + port.rx_async_fifo_inst.s_rst.setimmediatevalue(0) + port.tx_async_fifo_inst.m_rst.setimmediatevalue(0) + + mac = EthMac( + tx_clk=port.tx_async_fifo_inst.m_clk, + tx_rst=port.tx_async_fifo_inst.m_rst, + tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"), + tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts, + tx_ptp_ts=port.ptp.axis_tx_ptp_ts, + tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag, + tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid, + rx_clk=port.rx_async_fifo_inst.s_clk, + rx_rst=port.rx_async_fifo_inst.s_rst, + rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"), + rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts, + ifg=12, speed=speed + ) + + self.port_mac.append(mac) + + dut.ctrl_reg_wr_wait.setimmediatevalue(0) + dut.ctrl_reg_wr_ack.setimmediatevalue(0) + dut.ctrl_reg_rd_data.setimmediatevalue(0) + dut.ctrl_reg_rd_wait.setimmediatevalue(0) + dut.ctrl_reg_rd_ack.setimmediatevalue(0) + + dut.ptp_sample_clk.setimmediatevalue(0) + + dut.s_axis_stat_tdata.setimmediatevalue(0) + dut.s_axis_stat_tid.setimmediatevalue(0) + dut.s_axis_stat_tvalid.setimmediatevalue(0) + + self.loopback_enable = False + cocotb.fork(self._run_loopback()) + + async def init(self): + + for mac in self.port_mac: + mac.rx.reset.setimmediatevalue(0) + mac.tx.reset.setimmediatevalue(0) + + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + for mac in self.port_mac: + mac.rx.reset.setimmediatevalue(1) + mac.tx.reset.setimmediatevalue(1) + + await FallingEdge(self.dut.rst) + await Timer(100, 'ns') + + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + for mac in self.port_mac: + mac.rx.reset.setimmediatevalue(0) + mac.tx.reset.setimmediatevalue(0) + + await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) + + async def _run_loopback(self): + while True: + await RisingEdge(self.dut.clk) + + if self.loopback_enable: + for mac in self.port_mac: + if not mac.tx.empty(): + await mac.rx.send(await mac.tx.recv()) + + +@cocotb.test() +async def run_test_nic(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("Init driver") + await tb.driver.init_dev(tb.dev.functions[0].pcie_id) + await tb.driver.interfaces[0].open() + + # enable queues + tb.log.info("Enable queues") + await tb.rc.mem_write_dword(tb.driver.interfaces[0].ports[0].hw_addr+mqnic.MQNIC_PORT_REG_SCHED_ENABLE, 0x00000001) + for k in range(tb.driver.interfaces[0].tx_queue_count): + await tb.rc.mem_write_dword(tb.driver.interfaces[0].ports[0].schedulers[0].hw_addr+4*k, 0x00000003) + + # wait for all writes to complete + await tb.rc.mem_read(tb.driver.hw_addr, 4) + tb.log.info("Init complete") + + tb.log.info("Send and receive single packet") + + data = bytearray([x % 256 for x in range(1024)]) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.port_mac[0].tx.recv() + tb.log.info("Packet: %s", pkt) + + await tb.port_mac[0].rx.send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.log.info("RX and TX checksum tests") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=2) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + pkt = await tb.port_mac[0].tx.recv() + tb.log.info("Packet: %s", pkt) + + await tb.port_mac[0].rx.send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert Ether(pkt.data).build() == test_pkt.build() + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + tb.log.info("Multiple large packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + tb.log.info("Jumbo frames") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(9014)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + tb.log.info("Read statistics counters") + + await Timer(2000, 'ns') + + lst = [] + + for k in range(64): + lst.append(await tb.rc.mem_read_dword(tb.driver.hw_addr+0x010000+k*8)) + + print(lst) + + tb.log.info("Test AXI lite interface to application") + + await tb.rc.mem_write_dword(tb.driver.app_hw_addr, 0x11223344) + + print(await tb.rc.mem_read_dword(tb.driver.app_hw_addr)) + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.dirname(__file__) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) +pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) + + +@pytest.mark.parametrize(("axis_pcie_data_width", "axis_eth_data_width", "axis_eth_sync_data_width"), + [(256, 64, 64), (256, 64, 128), (512, 64, 64), (512, 64, 128), (512, 512, 512)]) +def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width, axis_eth_sync_data_width): + dut = "mqnic_core_pcie_us" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, "common", f"{dut}.v"), + os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "common", "mqnic_interface.v"), + os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "cpl_write.v"), + os.path.join(rtl_dir, "common", "cpl_op_mux.v"), + os.path.join(rtl_dir, "common", "desc_fetch.v"), + os.path.join(rtl_dir, "common", "desc_op_mux.v"), + os.path.join(rtl_dir, "common", "event_mux.v"), + os.path.join(rtl_dir, "common", "queue_manager.v"), + os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_engine.v"), + os.path.join(rtl_dir, "common", "rx_engine.v"), + os.path.join(rtl_dir, "common", "tx_checksum.v"), + os.path.join(rtl_dir, "common", "rx_hash.v"), + os.path.join(rtl_dir, "common", "rx_checksum.v"), + os.path.join(rtl_dir, "common", "stats_counter.v"), + os.path.join(rtl_dir, "common", "stats_collect.v"), + os.path.join(rtl_dir, "common", "stats_pcie_if.v"), + os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), + os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), + os.path.join(rtl_dir, "common", "stats_dma_latency.v"), + os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), + os.path.join(rtl_dir, "mqnic_app_block.v"), + os.path.join(eth_rtl_dir, "ptp_clock.v"), + os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_perout.v"), + os.path.join(eth_rtl_dir, "ptp_ts_extract.v"), + os.path.join(axi_rtl_dir, "axil_crossbar.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), + os.path.join(axi_rtl_dir, "axil_ram.v"), + os.path.join(axi_rtl_dir, "axil_reg_if.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), + os.path.join(axi_rtl_dir, "axil_register_rd.v"), + os.path.join(axi_rtl_dir, "axil_register_wr.v"), + os.path.join(axi_rtl_dir, "arbiter.v"), + os.path.join(axi_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_adapter.v"), + os.path.join(axis_rtl_dir, "axis_arb_mux.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), + os.path.join(axis_rtl_dir, "axis_register.v"), + os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_psdpram.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), + os.path.join(pcie_rtl_dir, "pcie_us_msi.v"), + os.path.join(pcie_rtl_dir, "pulse_merge.v"), + ] + + parameters = {} + + # Structural configuration + parameters['IF_COUNT'] = 1 + parameters['PORTS_PER_IF'] = 1 + + # PTP configuration + parameters['PTP_USE_SAMPLE_CLOCK'] = 0 + parameters['PTP_PEROUT_ENABLE'] = 0 + parameters['PTP_PEROUT_COUNT'] = 1 + + # Queue manager configuration (interface) + parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] + parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] + parameters['TX_QUEUE_INDEX_WIDTH'] = 13 + parameters['RX_QUEUE_INDEX_WIDTH'] = 8 + parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] + parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] + parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + + # TX and RX engine configuration (port) + parameters['TX_DESC_TABLE_SIZE'] = 32 + parameters['RX_DESC_TABLE_SIZE'] = 32 + + # Scheduler configuration (port) + parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] + parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['TDMA_INDEX_WIDTH'] = 6 + + # Timestamping configuration (port) + parameters['PTP_TS_ENABLE'] = 1 + parameters['TX_PTP_TS_FIFO_DEPTH'] = 32 + parameters['RX_PTP_TS_FIFO_DEPTH'] = 32 + + # Interface configuration (port) + parameters['TX_CHECKSUM_ENABLE'] = 1 + parameters['RX_RSS_ENABLE'] = 1 + parameters['RX_HASH_ENABLE'] = 1 + parameters['RX_CHECKSUM_ENABLE'] = 1 + parameters['TX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 131072 + parameters['MAX_TX_SIZE'] = 9214 + parameters['MAX_RX_SIZE'] = 9214 + parameters['TX_RAM_SIZE'] = 131072 + parameters['RX_RAM_SIZE'] = 131072 + + # Application block configuration + parameters['APP_ENABLE'] = 1 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + + # DMA interface configuration + parameters['DMA_LEN_WIDTH'] = 16 + parameters['DMA_TAG_WIDTH'] = 16 + parameters['RAM_PIPELINE'] = 2 + + # PCIe interface configuration + parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width + parameters['PF_COUNT'] = 1 + parameters['VF_COUNT'] = 0 + parameters['PCIE_TAG_COUNT'] = 64 + parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT'] + parameters['PCIE_DMA_READ_TX_LIMIT'] = 16 + parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1 + parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16 + parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 + parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 + parameters['MSI_COUNT'] = 32 + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_WIDTH'] = 32 + parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 + parameters['AXIL_CSR_PASSTHROUGH_ENABLE'] = 0 + + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + + # Ethernet interface configuration + parameters['AXIS_ETH_DATA_WIDTH'] = axis_eth_data_width + parameters['AXIS_ETH_SYNC_DATA_WIDTH'] = axis_eth_sync_data_width + parameters['AXIS_ETH_RX_USE_READY'] = 0 + parameters['AXIS_ETH_TX_PIPELINE'] = 0 + parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 + parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0 + parameters['AXIS_ETH_RX_PIPELINE'] = 0 + parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2 + + # Statistics counter subsystem + parameters['STAT_ENABLE'] = 1 + parameters['STAT_DMA_ENABLE'] = 1 + parameters['STAT_PCIE_ENABLE'] = 1 + parameters['STAT_INC_WIDTH'] = 24 + parameters['STAT_ID_WIDTH'] = 12 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 3ab5229b5..db6e2f3e9 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -106,6 +106,15 @@ module mqnic_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_ADDR_WIDTH = 64, parameter DMA_LEN_WIDTH = 16, @@ -115,7 +124,7 @@ module mqnic_core # parameter RAM_SEG_ADDR_WIDTH = 12, parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1, - parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1, + parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1, parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), parameter RAM_PIPELINE = 2, @@ -129,6 +138,11 @@ module mqnic_core # parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8), parameter AXIL_CSR_PASSTHROUGH_ENABLE = 0, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 16, + parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8), + // Ethernet interface configuration parameter AXIS_DATA_WIDTH = 512, parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, @@ -174,6 +188,29 @@ module mqnic_core # output wire s_axil_ctrl_rvalid, input wire s_axil_ctrl_rready, + /* + * AXI-Lite slave interface (application control) + */ + input wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] s_axil_app_ctrl_awaddr, + input wire [2:0] s_axil_app_ctrl_awprot, + input wire s_axil_app_ctrl_awvalid, + output wire s_axil_app_ctrl_awready, + input wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] s_axil_app_ctrl_wdata, + input wire [AXIL_APP_CTRL_STRB_WIDTH-1:0] s_axil_app_ctrl_wstrb, + input wire s_axil_app_ctrl_wvalid, + output wire s_axil_app_ctrl_wready, + output wire [1:0] s_axil_app_ctrl_bresp, + output wire s_axil_app_ctrl_bvalid, + input wire s_axil_app_ctrl_bready, + input wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] s_axil_app_ctrl_araddr, + input wire [2:0] s_axil_app_ctrl_arprot, + input wire s_axil_app_ctrl_arvalid, + output wire s_axil_app_ctrl_arready, + output wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] s_axil_app_ctrl_rdata, + output wire [1:0] s_axil_app_ctrl_rresp, + output wire s_axil_app_ctrl_rvalid, + input wire s_axil_app_ctrl_rready, + /* * AXI-Lite master interface (passthrough for NIC control and status) */ @@ -325,10 +362,17 @@ module mqnic_core # output wire s_axis_stat_tready ); -parameter IF_DMA_TAG_WIDTH = DMA_TAG_WIDTH-$clog2(IF_COUNT)-1; +parameter IF_COUNT_INT = IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0); + +parameter IF_DMA_TAG_WIDTH = DMA_TAG_WIDTH-$clog2(IF_COUNT_INT)-1; parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/(AXIS_DATA_WIDTH/AXIS_KEEP_WIDTH); +parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH; +parameter AXIS_IF_KEEP_WIDTH = AXIS_SYNC_KEEP_WIDTH; +parameter AXIS_IF_TX_USER_WIDTH = AXIS_TX_USER_WIDTH; +parameter AXIS_IF_RX_USER_WIDTH = AXIS_RX_USER_WIDTH; + // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -375,6 +419,26 @@ wire [1:0] axil_stats_rresp; wire axil_stats_rvalid; wire axil_stats_rready; +wire [AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_app_awaddr; +wire [2:0] axil_ctrl_app_awprot; +wire axil_ctrl_app_awvalid; +wire axil_ctrl_app_awready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_ctrl_app_wdata; +wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_ctrl_app_wstrb; +wire axil_ctrl_app_wvalid; +wire axil_ctrl_app_wready; +wire [1:0] axil_ctrl_app_bresp; +wire axil_ctrl_app_bvalid; +wire axil_ctrl_app_bready; +wire [AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_app_araddr; +wire [2:0] axil_ctrl_app_arprot; +wire axil_ctrl_app_arvalid; +wire axil_ctrl_app_arready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_ctrl_app_rdata; +wire [1:0] axil_ctrl_app_rresp; +wire axil_ctrl_app_rvalid; +wire axil_ctrl_app_rready; + // control registers wire ctrl_reg_wr_wait_int; wire ctrl_reg_wr_ack_int; @@ -526,6 +590,89 @@ mqnic_ptp_inst ( .ptp_perout_pulse(ptp_perout_pulse) ); +localparam CTRL_XBAR_MAIN_OFFSET = 0; +localparam CTRL_XBAR_APP_OFFSET = CTRL_XBAR_MAIN_OFFSET + 1; +localparam CTRL_XBAR_S_COUNT = CTRL_XBAR_APP_OFFSET + (APP_ENABLE && APP_CTRL_ENABLE ? 1 : 0); + +wire [CTRL_XBAR_S_COUNT*AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_xbar_awaddr; +wire [CTRL_XBAR_S_COUNT*3-1:0] axil_ctrl_xbar_awprot; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_awvalid; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_awready; +wire [CTRL_XBAR_S_COUNT*AXIL_CTRL_DATA_WIDTH-1:0] axil_ctrl_xbar_wdata; +wire [CTRL_XBAR_S_COUNT*AXIL_CTRL_STRB_WIDTH-1:0] axil_ctrl_xbar_wstrb; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_wvalid; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_wready; +wire [CTRL_XBAR_S_COUNT*2-1:0] axil_ctrl_xbar_bresp; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_bvalid; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_bready; +wire [CTRL_XBAR_S_COUNT*AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_xbar_araddr; +wire [CTRL_XBAR_S_COUNT*3-1:0] axil_ctrl_xbar_arprot; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_arvalid; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_arready; +wire [CTRL_XBAR_S_COUNT*AXIL_CTRL_DATA_WIDTH-1:0] axil_ctrl_xbar_rdata; +wire [CTRL_XBAR_S_COUNT*2-1:0] axil_ctrl_xbar_rresp; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_rvalid; +wire [CTRL_XBAR_S_COUNT-1:0] axil_ctrl_xbar_rready; + +generate + +assign axil_ctrl_xbar_awaddr[CTRL_XBAR_MAIN_OFFSET*AXIL_CTRL_ADDR_WIDTH +: AXIL_CTRL_ADDR_WIDTH] = s_axil_ctrl_awaddr; +assign axil_ctrl_xbar_awprot[CTRL_XBAR_MAIN_OFFSET*3 +: 3] = s_axil_ctrl_awprot; +assign axil_ctrl_xbar_awvalid[CTRL_XBAR_MAIN_OFFSET +: 1] = s_axil_ctrl_awvalid; +assign s_axil_ctrl_awready = axil_ctrl_xbar_awready[CTRL_XBAR_MAIN_OFFSET +: 1]; +assign axil_ctrl_xbar_wdata[CTRL_XBAR_MAIN_OFFSET*AXIL_CTRL_DATA_WIDTH +: AXIL_CTRL_DATA_WIDTH] = s_axil_ctrl_wdata; +assign axil_ctrl_xbar_wstrb[CTRL_XBAR_MAIN_OFFSET*AXIL_CTRL_STRB_WIDTH +: AXIL_CTRL_STRB_WIDTH] = s_axil_ctrl_wstrb; +assign axil_ctrl_xbar_wvalid[CTRL_XBAR_MAIN_OFFSET +: 1] = s_axil_ctrl_wvalid; +assign s_axil_ctrl_wready = axil_ctrl_xbar_wready[CTRL_XBAR_MAIN_OFFSET +: 1]; +assign s_axil_ctrl_bresp = axil_ctrl_xbar_bresp[CTRL_XBAR_MAIN_OFFSET*2 +: 2]; +assign s_axil_ctrl_bvalid = axil_ctrl_xbar_bvalid[CTRL_XBAR_MAIN_OFFSET +: 1]; +assign axil_ctrl_xbar_bready[CTRL_XBAR_MAIN_OFFSET +: 1] = s_axil_ctrl_bready; +assign axil_ctrl_xbar_araddr[CTRL_XBAR_MAIN_OFFSET*AXIL_CTRL_ADDR_WIDTH +: AXIL_CTRL_ADDR_WIDTH] = s_axil_ctrl_araddr; +assign axil_ctrl_xbar_arprot[CTRL_XBAR_MAIN_OFFSET*3 +: 3] = s_axil_ctrl_arprot; +assign axil_ctrl_xbar_arvalid[CTRL_XBAR_MAIN_OFFSET +: 1] = s_axil_ctrl_arvalid; +assign s_axil_ctrl_arready = axil_ctrl_xbar_arready[CTRL_XBAR_MAIN_OFFSET +: 1]; +assign s_axil_ctrl_rdata = axil_ctrl_xbar_rdata[CTRL_XBAR_MAIN_OFFSET*AXIL_CTRL_DATA_WIDTH +: AXIL_CTRL_DATA_WIDTH]; +assign s_axil_ctrl_rresp = axil_ctrl_xbar_rresp[CTRL_XBAR_MAIN_OFFSET*2 +: 2]; +assign s_axil_ctrl_rvalid = axil_ctrl_xbar_rvalid[CTRL_XBAR_MAIN_OFFSET +: 1]; +assign axil_ctrl_xbar_rready[CTRL_XBAR_MAIN_OFFSET +: 1] = s_axil_ctrl_rready; + +if (APP_ENABLE && APP_CTRL_ENABLE) begin + + assign axil_ctrl_xbar_awaddr[CTRL_XBAR_APP_OFFSET*AXIL_CTRL_ADDR_WIDTH +: AXIL_CTRL_ADDR_WIDTH] = axil_ctrl_app_awaddr; + assign axil_ctrl_xbar_awprot[CTRL_XBAR_APP_OFFSET*3 +: 3] = axil_ctrl_app_awprot; + assign axil_ctrl_xbar_awvalid[CTRL_XBAR_APP_OFFSET +: 1] = axil_ctrl_app_awvalid; + assign axil_ctrl_app_awready = axil_ctrl_xbar_awready[CTRL_XBAR_APP_OFFSET +: 1]; + assign axil_ctrl_xbar_wdata[CTRL_XBAR_APP_OFFSET*AXIL_CTRL_DATA_WIDTH +: AXIL_CTRL_DATA_WIDTH] = axil_ctrl_app_wdata; + assign axil_ctrl_xbar_wstrb[CTRL_XBAR_APP_OFFSET*AXIL_CTRL_STRB_WIDTH +: AXIL_CTRL_STRB_WIDTH] = axil_ctrl_app_wstrb; + assign axil_ctrl_xbar_wvalid[CTRL_XBAR_APP_OFFSET +: 1] = axil_ctrl_app_wvalid; + assign axil_ctrl_app_wready = axil_ctrl_xbar_wready[CTRL_XBAR_APP_OFFSET +: 1]; + assign axil_ctrl_app_bresp = axil_ctrl_xbar_bresp[CTRL_XBAR_APP_OFFSET*2 +: 2]; + assign axil_ctrl_app_bvalid = axil_ctrl_xbar_bvalid[CTRL_XBAR_APP_OFFSET +: 1]; + assign axil_ctrl_xbar_bready[CTRL_XBAR_APP_OFFSET +: 1] = axil_ctrl_app_bready; + assign axil_ctrl_xbar_araddr[CTRL_XBAR_APP_OFFSET*AXIL_CTRL_ADDR_WIDTH +: AXIL_CTRL_ADDR_WIDTH] = axil_ctrl_app_araddr; + assign axil_ctrl_xbar_arprot[CTRL_XBAR_APP_OFFSET*3 +: 3] = axil_ctrl_app_arprot; + assign axil_ctrl_xbar_arvalid[CTRL_XBAR_APP_OFFSET +: 1] = axil_ctrl_app_arvalid; + assign axil_ctrl_app_arready = axil_ctrl_xbar_arready[CTRL_XBAR_APP_OFFSET +: 1]; + assign axil_ctrl_app_rdata = axil_ctrl_xbar_rdata[CTRL_XBAR_APP_OFFSET*AXIL_CTRL_DATA_WIDTH +: AXIL_CTRL_DATA_WIDTH]; + assign axil_ctrl_app_rresp = axil_ctrl_xbar_rresp[CTRL_XBAR_APP_OFFSET*2 +: 2]; + assign axil_ctrl_app_rvalid = axil_ctrl_xbar_rvalid[CTRL_XBAR_APP_OFFSET +: 1]; + assign axil_ctrl_xbar_rready[CTRL_XBAR_APP_OFFSET +: 1] = axil_ctrl_app_rready; + +end else begin + + assign axil_ctrl_app_awready = 0; + assign axil_ctrl_app_wready = 0; + assign axil_ctrl_app_bresp = 0; + assign axil_ctrl_app_bvalid = 0; + assign axil_ctrl_app_arready = 0; + assign axil_ctrl_app_rdata = 0; + assign axil_ctrl_app_rresp = 0; + assign axil_ctrl_app_rvalid = 0; + +end + +endgenerate + wire [IF_COUNT*AXIL_CTRL_ADDR_WIDTH-1:0] axil_if_ctrl_awaddr; wire [IF_COUNT*3-1:0] axil_if_ctrl_awprot; wire [IF_COUNT-1:0] axil_if_ctrl_awvalid; @@ -546,58 +693,38 @@ wire [IF_COUNT*2-1:0] axil_if_ctrl_rresp; wire [IF_COUNT-1:0] axil_if_ctrl_rvalid; wire [IF_COUNT-1:0] axil_if_ctrl_rready; -wire [IF_COUNT*AXIL_CSR_ADDR_WIDTH-1:0] axil_if_csr_awaddr; -wire [IF_COUNT*3-1:0] axil_if_csr_awprot; -wire [IF_COUNT-1:0] axil_if_csr_awvalid; -wire [IF_COUNT-1:0] axil_if_csr_awready; -wire [IF_COUNT*AXIL_CTRL_DATA_WIDTH-1:0] axil_if_csr_wdata; -wire [IF_COUNT*AXIL_CTRL_STRB_WIDTH-1:0] axil_if_csr_wstrb; -wire [IF_COUNT-1:0] axil_if_csr_wvalid; -wire [IF_COUNT-1:0] axil_if_csr_wready; -wire [IF_COUNT*2-1:0] axil_if_csr_bresp; -wire [IF_COUNT-1:0] axil_if_csr_bvalid; -wire [IF_COUNT-1:0] axil_if_csr_bready; -wire [IF_COUNT*AXIL_CSR_ADDR_WIDTH-1:0] axil_if_csr_araddr; -wire [IF_COUNT*3-1:0] axil_if_csr_arprot; -wire [IF_COUNT-1:0] axil_if_csr_arvalid; -wire [IF_COUNT-1:0] axil_if_csr_arready; -wire [IF_COUNT*AXIL_CTRL_DATA_WIDTH-1:0] axil_if_csr_rdata; -wire [IF_COUNT*2-1:0] axil_if_csr_rresp; -wire [IF_COUNT-1:0] axil_if_csr_rvalid; -wire [IF_COUNT-1:0] axil_if_csr_rready; - axil_crossbar #( .DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .S_COUNT(1), + .S_COUNT(CTRL_XBAR_S_COUNT), .M_COUNT(IF_COUNT), .M_BASE_ADDR(0), .M_ADDR_WIDTH({IF_COUNT{w_32(AXIL_IF_CTRL_ADDR_WIDTH)}}), - .M_CONNECT_READ({IF_COUNT{1'b1}}), - .M_CONNECT_WRITE({IF_COUNT{1'b1}}) + .M_CONNECT_READ({IF_COUNT{{CTRL_XBAR_S_COUNT{1'b1}}}}), + .M_CONNECT_WRITE({IF_COUNT{{CTRL_XBAR_S_COUNT{1'b1}}}}) ) axil_crossbar_inst ( .clk(clk), .rst(rst), - .s_axil_awaddr(s_axil_ctrl_awaddr), - .s_axil_awprot(s_axil_ctrl_awprot), - .s_axil_awvalid(s_axil_ctrl_awvalid), - .s_axil_awready(s_axil_ctrl_awready), - .s_axil_wdata(s_axil_ctrl_wdata), - .s_axil_wstrb(s_axil_ctrl_wstrb), - .s_axil_wvalid(s_axil_ctrl_wvalid), - .s_axil_wready(s_axil_ctrl_wready), - .s_axil_bresp(s_axil_ctrl_bresp), - .s_axil_bvalid(s_axil_ctrl_bvalid), - .s_axil_bready(s_axil_ctrl_bready), - .s_axil_araddr(s_axil_ctrl_araddr), - .s_axil_arprot(s_axil_ctrl_arprot), - .s_axil_arvalid(s_axil_ctrl_arvalid), - .s_axil_arready(s_axil_ctrl_arready), - .s_axil_rdata(s_axil_ctrl_rdata), - .s_axil_rresp(s_axil_ctrl_rresp), - .s_axil_rvalid(s_axil_ctrl_rvalid), - .s_axil_rready(s_axil_ctrl_rready), + .s_axil_awaddr(axil_ctrl_xbar_awaddr), + .s_axil_awprot(axil_ctrl_xbar_awprot), + .s_axil_awvalid(axil_ctrl_xbar_awvalid), + .s_axil_awready(axil_ctrl_xbar_awready), + .s_axil_wdata(axil_ctrl_xbar_wdata), + .s_axil_wstrb(axil_ctrl_xbar_wstrb), + .s_axil_wvalid(axil_ctrl_xbar_wvalid), + .s_axil_wready(axil_ctrl_xbar_wready), + .s_axil_bresp(axil_ctrl_xbar_bresp), + .s_axil_bvalid(axil_ctrl_xbar_bvalid), + .s_axil_bready(axil_ctrl_xbar_bready), + .s_axil_araddr(axil_ctrl_xbar_araddr), + .s_axil_arprot(axil_ctrl_xbar_arprot), + .s_axil_arvalid(axil_ctrl_xbar_arvalid), + .s_axil_arready(axil_ctrl_xbar_arready), + .s_axil_rdata(axil_ctrl_xbar_rdata), + .s_axil_rresp(axil_ctrl_xbar_rresp), + .s_axil_rvalid(axil_ctrl_xbar_rvalid), + .s_axil_rready(axil_ctrl_xbar_rready), .m_axil_awaddr(axil_if_ctrl_awaddr), .m_axil_awprot(axil_if_ctrl_awprot), .m_axil_awvalid(axil_if_ctrl_awvalid), @@ -619,6 +746,26 @@ axil_crossbar_inst ( .m_axil_rready(axil_if_ctrl_rready) ); +wire [IF_COUNT*AXIL_CSR_ADDR_WIDTH-1:0] axil_if_csr_awaddr; +wire [IF_COUNT*3-1:0] axil_if_csr_awprot; +wire [IF_COUNT-1:0] axil_if_csr_awvalid; +wire [IF_COUNT-1:0] axil_if_csr_awready; +wire [IF_COUNT*AXIL_CTRL_DATA_WIDTH-1:0] axil_if_csr_wdata; +wire [IF_COUNT*AXIL_CTRL_STRB_WIDTH-1:0] axil_if_csr_wstrb; +wire [IF_COUNT-1:0] axil_if_csr_wvalid; +wire [IF_COUNT-1:0] axil_if_csr_wready; +wire [IF_COUNT*2-1:0] axil_if_csr_bresp; +wire [IF_COUNT-1:0] axil_if_csr_bvalid; +wire [IF_COUNT-1:0] axil_if_csr_bready; +wire [IF_COUNT*AXIL_CSR_ADDR_WIDTH-1:0] axil_if_csr_araddr; +wire [IF_COUNT*3-1:0] axil_if_csr_arprot; +wire [IF_COUNT-1:0] axil_if_csr_arvalid; +wire [IF_COUNT-1:0] axil_if_csr_arready; +wire [IF_COUNT*AXIL_CTRL_DATA_WIDTH-1:0] axil_if_csr_rdata; +wire [IF_COUNT*2-1:0] axil_if_csr_rresp; +wire [IF_COUNT-1:0] axil_if_csr_rvalid; +wire [IF_COUNT-1:0] axil_if_csr_rready; + localparam CSR_XBAR_CSR_OFFSET = 0; localparam CSR_XBAR_STAT_OFFSET = CSR_XBAR_CSR_OFFSET + 1; localparam CSR_XBAR_PASSTHROUGH_OFFSET = CSR_XBAR_STAT_OFFSET + (STAT_ENABLE ? 1 : 0); @@ -700,6 +847,20 @@ if (STAT_ENABLE) begin assign axil_csr_xbar_rvalid[CSR_XBAR_STAT_OFFSET +: 1] = axil_stats_rvalid; assign axil_stats_rready = axil_csr_xbar_rready[CSR_XBAR_STAT_OFFSET +: 1]; +end else begin + + assign axil_stats_awaddr = 0; + assign axil_stats_awprot = 0; + assign axil_stats_awvalid = 0; + assign axil_stats_wdata = 0; + assign axil_stats_wstrb = 0; + assign axil_stats_wvalid = 0; + assign axil_stats_bready = 0; + assign axil_stats_araddr = 0; + assign axil_stats_arprot = 0; + assign axil_stats_arvalid = 0; + assign axil_stats_rready = 0; + end if (AXIL_CSR_PASSTHROUGH_ENABLE) begin @@ -724,6 +885,20 @@ if (AXIL_CSR_PASSTHROUGH_ENABLE) begin assign axil_csr_xbar_rvalid[CSR_XBAR_PASSTHROUGH_OFFSET +: 1] = m_axil_csr_rvalid; assign m_axil_csr_rready = axil_csr_xbar_rready[CSR_XBAR_PASSTHROUGH_OFFSET +: 1]; +end else begin + + assign m_axil_csr_awaddr = 0; + assign m_axil_csr_awprot = 0; + assign m_axil_csr_awvalid = 0; + assign m_axil_csr_wdata = 0; + assign m_axil_csr_wstrb = 0; + assign m_axil_csr_wvalid = 0; + assign m_axil_csr_bready = 0; + assign m_axil_csr_araddr = 0; + assign m_axil_csr_arprot = 0; + assign m_axil_csr_arvalid = 0; + assign m_axil_csr_rready = 0; + end endgenerate @@ -781,8 +956,72 @@ axil_csr_crossbar_inst ( .m_axil_rready(axil_csr_xbar_rready) ); +wire [STAT_INC_WIDTH-1:0] axis_stat_tdata; +wire [STAT_ID_WIDTH-1:0] axis_stat_tid; +wire axis_stat_tvalid; +wire axis_stat_tready; + +wire [STAT_INC_WIDTH-1:0] axis_app_stat_tdata; +wire [STAT_ID_WIDTH-1:0] axis_app_stat_tid; +wire axis_app_stat_tvalid; +wire axis_app_stat_tready; + generate +if (STAT_ENABLE && (APP_ENABLE && APP_STAT_ENABLE)) begin + + axis_arb_mux #( + .S_COUNT(2), + .DATA_WIDTH(STAT_INC_WIDTH), + .KEEP_ENABLE(0), + .ID_ENABLE(1), + .ID_WIDTH(STAT_ID_WIDTH), + .DEST_ENABLE(0), + .USER_ENABLE(0), + .LAST_ENABLE(0), + .ARB_TYPE_ROUND_ROBIN(1), + .ARB_LSB_HIGH_PRIORITY(1) + ) + axis_stat_mux_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI Stream inputs + */ + .s_axis_tdata({axis_app_stat_tdata, s_axis_stat_tdata}), + .s_axis_tkeep(0), + .s_axis_tvalid({axis_app_stat_tvalid, s_axis_stat_tvalid}), + .s_axis_tready({axis_app_stat_tready, s_axis_stat_tready}), + .s_axis_tlast(0), + .s_axis_tid({axis_app_stat_tid, s_axis_stat_tid}), + .s_axis_tdest(0), + .s_axis_tuser(0), + + /* + * AXI Stream output + */ + .m_axis_tdata(axis_stat_tdata), + .m_axis_tkeep(), + .m_axis_tvalid(axis_stat_tvalid), + .m_axis_tready(axis_stat_tready), + .m_axis_tlast(), + .m_axis_tid(axis_stat_tid), + .m_axis_tdest(), + .m_axis_tuser() + ); + +end else begin + + assign axis_stat_tdata = s_axis_stat_tdata; + assign axis_stat_tid = s_axis_stat_tid; + assign axis_stat_tvalid = s_axis_stat_tvalid; + assign s_axis_stat_tready = axis_stat_tready; + + assign axis_app_stat_tready = 1'b1; + +end + if (STAT_ENABLE) begin stats_counter #( @@ -800,10 +1039,10 @@ if (STAT_ENABLE) begin /* * Statistics increment input */ - .s_axis_stat_tdata(s_axis_stat_tdata), - .s_axis_stat_tid(s_axis_stat_tid), - .s_axis_stat_tvalid(s_axis_stat_tvalid), - .s_axis_stat_tready(s_axis_stat_tready), + .s_axis_stat_tdata(axis_stat_tdata), + .s_axis_stat_tid(axis_stat_tid), + .s_axis_stat_tvalid(axis_stat_tvalid), + .s_axis_stat_tready(axis_stat_tready), /* * AXI Lite register interface @@ -837,6 +1076,7 @@ end endgenerate +// data/control DMA mux (priority) wire [DMA_ADDR_WIDTH-1:0] ctrl_dma_read_desc_dma_addr; wire [RAM_SEL_WIDTH-2:0] ctrl_dma_read_desc_ram_sel; wire [RAM_ADDR_WIDTH-1:0] ctrl_dma_read_desc_ram_addr; @@ -1044,90 +1284,91 @@ dma_if_mux_inst ( .ram_rd_resp_ready({data_dma_ram_rd_resp_ready, ctrl_dma_ram_rd_resp_ready}) ); -wire [IF_COUNT*DMA_ADDR_WIDTH-1:0] if_ctrl_dma_read_desc_dma_addr; -wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_read_desc_ram_sel; -wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_ctrl_dma_read_desc_ram_addr; -wire [IF_COUNT*DMA_LEN_WIDTH-1:0] if_ctrl_dma_read_desc_len; -wire [IF_COUNT*IF_DMA_TAG_WIDTH-1:0] if_ctrl_dma_read_desc_tag; -wire [IF_COUNT-1:0] if_ctrl_dma_read_desc_valid; -wire [IF_COUNT-1:0] if_ctrl_dma_read_desc_ready; +// interface DMA mux (round-robin) +wire [IF_COUNT_INT*DMA_ADDR_WIDTH-1:0] if_ctrl_dma_read_desc_dma_addr; +wire [IF_COUNT_INT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_read_desc_ram_sel; +wire [IF_COUNT_INT*RAM_ADDR_WIDTH-1:0] if_ctrl_dma_read_desc_ram_addr; +wire [IF_COUNT_INT*DMA_LEN_WIDTH-1:0] if_ctrl_dma_read_desc_len; +wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0] if_ctrl_dma_read_desc_tag; +wire [IF_COUNT_INT-1:0] if_ctrl_dma_read_desc_valid; +wire [IF_COUNT_INT-1:0] if_ctrl_dma_read_desc_ready; -wire [IF_COUNT*IF_DMA_TAG_WIDTH-1:0] if_ctrl_dma_read_desc_status_tag; -wire [IF_COUNT*4-1:0] if_ctrl_dma_read_desc_status_error; -wire [IF_COUNT-1:0] if_ctrl_dma_read_desc_status_valid; +wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0] if_ctrl_dma_read_desc_status_tag; +wire [IF_COUNT_INT*4-1:0] if_ctrl_dma_read_desc_status_error; +wire [IF_COUNT_INT-1:0] if_ctrl_dma_read_desc_status_valid; -wire [IF_COUNT*DMA_ADDR_WIDTH-1:0] if_ctrl_dma_write_desc_dma_addr; -wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_write_desc_ram_sel; -wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_ctrl_dma_write_desc_ram_addr; -wire [IF_COUNT*DMA_LEN_WIDTH-1:0] if_ctrl_dma_write_desc_len; -wire [IF_COUNT*IF_DMA_TAG_WIDTH-1:0] if_ctrl_dma_write_desc_tag; -wire [IF_COUNT-1:0] if_ctrl_dma_write_desc_valid; -wire [IF_COUNT-1:0] if_ctrl_dma_write_desc_ready; +wire [IF_COUNT_INT*DMA_ADDR_WIDTH-1:0] if_ctrl_dma_write_desc_dma_addr; +wire [IF_COUNT_INT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_write_desc_ram_sel; +wire [IF_COUNT_INT*RAM_ADDR_WIDTH-1:0] if_ctrl_dma_write_desc_ram_addr; +wire [IF_COUNT_INT*DMA_LEN_WIDTH-1:0] if_ctrl_dma_write_desc_len; +wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0] if_ctrl_dma_write_desc_tag; +wire [IF_COUNT_INT-1:0] if_ctrl_dma_write_desc_valid; +wire [IF_COUNT_INT-1:0] if_ctrl_dma_write_desc_ready; -wire [IF_COUNT*IF_DMA_TAG_WIDTH-1:0] if_ctrl_dma_write_desc_status_tag; -wire [IF_COUNT*4-1:0] if_ctrl_dma_write_desc_status_error; -wire [IF_COUNT-1:0] if_ctrl_dma_write_desc_status_valid; +wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0] if_ctrl_dma_write_desc_status_tag; +wire [IF_COUNT_INT*4-1:0] if_ctrl_dma_write_desc_status_error; +wire [IF_COUNT_INT-1:0] if_ctrl_dma_write_desc_status_valid; -wire [IF_COUNT*DMA_ADDR_WIDTH-1:0] if_data_dma_read_desc_dma_addr; -wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_read_desc_ram_sel; -wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_data_dma_read_desc_ram_addr; -wire [IF_COUNT*DMA_LEN_WIDTH-1:0] if_data_dma_read_desc_len; -wire [IF_COUNT*IF_DMA_TAG_WIDTH-1:0] if_data_dma_read_desc_tag; -wire [IF_COUNT-1:0] if_data_dma_read_desc_valid; -wire [IF_COUNT-1:0] if_data_dma_read_desc_ready; +wire [IF_COUNT_INT*DMA_ADDR_WIDTH-1:0] if_data_dma_read_desc_dma_addr; +wire [IF_COUNT_INT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_read_desc_ram_sel; +wire [IF_COUNT_INT*RAM_ADDR_WIDTH-1:0] if_data_dma_read_desc_ram_addr; +wire [IF_COUNT_INT*DMA_LEN_WIDTH-1:0] if_data_dma_read_desc_len; +wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0] if_data_dma_read_desc_tag; +wire [IF_COUNT_INT-1:0] if_data_dma_read_desc_valid; +wire [IF_COUNT_INT-1:0] if_data_dma_read_desc_ready; -wire [IF_COUNT*IF_DMA_TAG_WIDTH-1:0] if_data_dma_read_desc_status_tag; -wire [IF_COUNT*4-1:0] if_data_dma_read_desc_status_error; -wire [IF_COUNT-1:0] if_data_dma_read_desc_status_valid; +wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0] if_data_dma_read_desc_status_tag; +wire [IF_COUNT_INT*4-1:0] if_data_dma_read_desc_status_error; +wire [IF_COUNT_INT-1:0] if_data_dma_read_desc_status_valid; -wire [IF_COUNT*DMA_ADDR_WIDTH-1:0] if_data_dma_write_desc_dma_addr; -wire [IF_COUNT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_write_desc_ram_sel; -wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_data_dma_write_desc_ram_addr; -wire [IF_COUNT*DMA_LEN_WIDTH-1:0] if_data_dma_write_desc_len; -wire [IF_COUNT*IF_DMA_TAG_WIDTH-1:0] if_data_dma_write_desc_tag; -wire [IF_COUNT-1:0] if_data_dma_write_desc_valid; -wire [IF_COUNT-1:0] if_data_dma_write_desc_ready; +wire [IF_COUNT_INT*DMA_ADDR_WIDTH-1:0] if_data_dma_write_desc_dma_addr; +wire [IF_COUNT_INT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_write_desc_ram_sel; +wire [IF_COUNT_INT*RAM_ADDR_WIDTH-1:0] if_data_dma_write_desc_ram_addr; +wire [IF_COUNT_INT*DMA_LEN_WIDTH-1:0] if_data_dma_write_desc_len; +wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0] if_data_dma_write_desc_tag; +wire [IF_COUNT_INT-1:0] if_data_dma_write_desc_valid; +wire [IF_COUNT_INT-1:0] if_data_dma_write_desc_ready; -wire [IF_COUNT*IF_DMA_TAG_WIDTH-1:0] if_data_dma_write_desc_status_tag; -wire [IF_COUNT*4-1:0] if_data_dma_write_desc_status_error; -wire [IF_COUNT-1:0] if_data_dma_write_desc_status_valid; +wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0] if_data_dma_write_desc_status_tag; +wire [IF_COUNT_INT*4-1:0] if_data_dma_write_desc_status_error; +wire [IF_COUNT_INT-1:0] if_data_dma_write_desc_status_valid; -wire [IF_COUNT*RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_be; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_addr; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_data; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_wr_cmd_valid; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_wr_cmd_ready; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_wr_done; -wire [IF_COUNT*RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_rd_cmd_sel; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] if_ctrl_dma_ram_rd_cmd_addr; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_rd_cmd_valid; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_rd_cmd_ready; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] if_ctrl_dma_ram_rd_resp_data; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_rd_resp_valid; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_rd_resp_ready; +wire [IF_COUNT_INT*RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_be; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_addr; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_data; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_wr_cmd_valid; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_wr_cmd_ready; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_wr_done; +wire [IF_COUNT_INT*RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_rd_cmd_sel; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] if_ctrl_dma_ram_rd_cmd_addr; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_rd_cmd_valid; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_rd_cmd_ready; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] if_ctrl_dma_ram_rd_resp_data; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_rd_resp_valid; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_ctrl_dma_ram_rd_resp_ready; -wire [IF_COUNT*RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_ram_wr_cmd_sel; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] if_data_dma_ram_wr_cmd_be; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] if_data_dma_ram_wr_cmd_addr; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] if_data_dma_ram_wr_cmd_data; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_data_dma_ram_wr_cmd_valid; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_data_dma_ram_wr_cmd_ready; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_data_dma_ram_wr_done; -wire [IF_COUNT*RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_ram_rd_cmd_sel; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] if_data_dma_ram_rd_cmd_addr; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_data_dma_ram_rd_cmd_valid; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_data_dma_ram_rd_cmd_ready; -wire [IF_COUNT*RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] if_data_dma_ram_rd_resp_data; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_data_dma_ram_rd_resp_valid; -wire [IF_COUNT*RAM_SEG_COUNT-1:0] if_data_dma_ram_rd_resp_ready; +wire [IF_COUNT_INT*RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_ram_wr_cmd_sel; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] if_data_dma_ram_wr_cmd_be; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] if_data_dma_ram_wr_cmd_addr; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] if_data_dma_ram_wr_cmd_data; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_data_dma_ram_wr_cmd_valid; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_data_dma_ram_wr_cmd_ready; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_data_dma_ram_wr_done; +wire [IF_COUNT_INT*RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_data_dma_ram_rd_cmd_sel; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] if_data_dma_ram_rd_cmd_addr; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_data_dma_ram_rd_cmd_valid; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_data_dma_ram_rd_cmd_ready; +wire [IF_COUNT_INT*RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] if_data_dma_ram_rd_resp_data; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_data_dma_ram_rd_resp_valid; +wire [IF_COUNT_INT*RAM_SEG_COUNT-1:0] if_data_dma_ram_rd_resp_ready; generate -if (IF_COUNT > 1) begin : dma_if_mux +if (IF_COUNT_INT > 1) begin : dma_if_mux dma_if_mux #( - .PORTS(IF_COUNT), + .PORTS(IF_COUNT_INT), .SEG_COUNT(RAM_SEG_COUNT), .SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), .SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), @@ -1256,7 +1497,7 @@ if (IF_COUNT > 1) begin : dma_if_mux ); dma_if_mux #( - .PORTS(IF_COUNT), + .PORTS(IF_COUNT_INT), .SEG_COUNT(RAM_SEG_COUNT), .SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), .SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), @@ -1468,6 +1709,216 @@ end endgenerate +wire [DMA_ADDR_WIDTH-1:0] app_ctrl_dma_read_desc_dma_addr; +wire [IF_RAM_SEL_WIDTH-1:0] app_ctrl_dma_read_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] app_ctrl_dma_read_desc_ram_addr; +wire [DMA_LEN_WIDTH-1:0] app_ctrl_dma_read_desc_len; +wire [IF_DMA_TAG_WIDTH-1:0] app_ctrl_dma_read_desc_tag; +wire app_ctrl_dma_read_desc_valid; +wire app_ctrl_dma_read_desc_ready; + +wire [IF_DMA_TAG_WIDTH-1:0] app_ctrl_dma_read_desc_status_tag; +wire [3:0] app_ctrl_dma_read_desc_status_error; +wire app_ctrl_dma_read_desc_status_valid; + +wire [DMA_ADDR_WIDTH-1:0] app_ctrl_dma_write_desc_dma_addr; +wire [IF_RAM_SEL_WIDTH-1:0] app_ctrl_dma_write_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] app_ctrl_dma_write_desc_ram_addr; +wire [DMA_LEN_WIDTH-1:0] app_ctrl_dma_write_desc_len; +wire [IF_DMA_TAG_WIDTH-1:0] app_ctrl_dma_write_desc_tag; +wire app_ctrl_dma_write_desc_valid; +wire app_ctrl_dma_write_desc_ready; + +wire [IF_DMA_TAG_WIDTH-1:0] app_ctrl_dma_write_desc_status_tag; +wire [3:0] app_ctrl_dma_write_desc_status_error; +wire app_ctrl_dma_write_desc_status_valid; + +wire [DMA_ADDR_WIDTH-1:0] app_data_dma_read_desc_dma_addr; +wire [IF_RAM_SEL_WIDTH-1:0] app_data_dma_read_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] app_data_dma_read_desc_ram_addr; +wire [DMA_LEN_WIDTH-1:0] app_data_dma_read_desc_len; +wire [IF_DMA_TAG_WIDTH-1:0] app_data_dma_read_desc_tag; +wire app_data_dma_read_desc_valid; +wire app_data_dma_read_desc_ready; + +wire [IF_DMA_TAG_WIDTH-1:0] app_data_dma_read_desc_status_tag; +wire [3:0] app_data_dma_read_desc_status_error; +wire app_data_dma_read_desc_status_valid; + +wire [DMA_ADDR_WIDTH-1:0] app_data_dma_write_desc_dma_addr; +wire [IF_RAM_SEL_WIDTH-1:0] app_data_dma_write_desc_ram_sel; +wire [RAM_ADDR_WIDTH-1:0] app_data_dma_write_desc_ram_addr; +wire [DMA_LEN_WIDTH-1:0] app_data_dma_write_desc_len; +wire [IF_DMA_TAG_WIDTH-1:0] app_data_dma_write_desc_tag; +wire app_data_dma_write_desc_valid; +wire app_data_dma_write_desc_ready; + +wire [IF_DMA_TAG_WIDTH-1:0] app_data_dma_write_desc_status_tag; +wire [3:0] app_data_dma_write_desc_status_error; +wire app_data_dma_write_desc_status_valid; + +wire [RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] app_ctrl_dma_ram_wr_cmd_sel; +wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] app_ctrl_dma_ram_wr_cmd_be; +wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] app_ctrl_dma_ram_wr_cmd_addr; +wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] app_ctrl_dma_ram_wr_cmd_data; +wire [RAM_SEG_COUNT-1:0] app_ctrl_dma_ram_wr_cmd_valid; +wire [RAM_SEG_COUNT-1:0] app_ctrl_dma_ram_wr_cmd_ready; +wire [RAM_SEG_COUNT-1:0] app_ctrl_dma_ram_wr_done; +wire [RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] app_ctrl_dma_ram_rd_cmd_sel; +wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] app_ctrl_dma_ram_rd_cmd_addr; +wire [RAM_SEG_COUNT-1:0] app_ctrl_dma_ram_rd_cmd_valid; +wire [RAM_SEG_COUNT-1:0] app_ctrl_dma_ram_rd_cmd_ready; +wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] app_ctrl_dma_ram_rd_resp_data; +wire [RAM_SEG_COUNT-1:0] app_ctrl_dma_ram_rd_resp_valid; +wire [RAM_SEG_COUNT-1:0] app_ctrl_dma_ram_rd_resp_ready; + +wire [RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] app_data_dma_ram_wr_cmd_sel; +wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] app_data_dma_ram_wr_cmd_be; +wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] app_data_dma_ram_wr_cmd_addr; +wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] app_data_dma_ram_wr_cmd_data; +wire [RAM_SEG_COUNT-1:0] app_data_dma_ram_wr_cmd_valid; +wire [RAM_SEG_COUNT-1:0] app_data_dma_ram_wr_cmd_ready; +wire [RAM_SEG_COUNT-1:0] app_data_dma_ram_wr_done; +wire [RAM_SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] app_data_dma_ram_rd_cmd_sel; +wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] app_data_dma_ram_rd_cmd_addr; +wire [RAM_SEG_COUNT-1:0] app_data_dma_ram_rd_cmd_valid; +wire [RAM_SEG_COUNT-1:0] app_data_dma_ram_rd_cmd_ready; +wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] app_data_dma_ram_rd_resp_data; +wire [RAM_SEG_COUNT-1:0] app_data_dma_ram_rd_resp_valid; +wire [RAM_SEG_COUNT-1:0] app_data_dma_ram_rd_resp_ready; + +generate + +if (APP_ENABLE && APP_DMA_ENABLE) begin + + assign if_ctrl_dma_read_desc_dma_addr[IF_COUNT*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH] = app_ctrl_dma_read_desc_dma_addr; + assign if_ctrl_dma_read_desc_ram_sel[IF_COUNT*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH] = app_ctrl_dma_read_desc_ram_sel; + assign if_ctrl_dma_read_desc_ram_addr[IF_COUNT*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = app_ctrl_dma_read_desc_ram_addr; + assign if_ctrl_dma_read_desc_len[IF_COUNT*DMA_LEN_WIDTH +: DMA_LEN_WIDTH] = app_ctrl_dma_read_desc_len; + assign if_ctrl_dma_read_desc_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH] = app_ctrl_dma_read_desc_tag; + assign if_ctrl_dma_read_desc_valid[IF_COUNT] = app_ctrl_dma_read_desc_valid; + assign app_ctrl_dma_read_desc_ready = if_ctrl_dma_read_desc_ready[IF_COUNT]; + + assign app_ctrl_dma_read_desc_status_tag = if_ctrl_dma_read_desc_status_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH]; + assign app_ctrl_dma_read_desc_status_error = if_ctrl_dma_read_desc_status_error[IF_COUNT*4 +: 4]; + assign app_ctrl_dma_read_desc_status_valid = if_ctrl_dma_read_desc_status_valid[IF_COUNT]; + + assign if_ctrl_dma_write_desc_dma_addr[IF_COUNT*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH] = app_ctrl_dma_write_desc_dma_addr; + assign if_ctrl_dma_write_desc_ram_sel[IF_COUNT*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH] = app_ctrl_dma_write_desc_ram_sel; + assign if_ctrl_dma_write_desc_ram_addr[IF_COUNT*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = app_ctrl_dma_write_desc_ram_addr; + assign if_ctrl_dma_write_desc_len[IF_COUNT*DMA_LEN_WIDTH +: DMA_LEN_WIDTH] = app_ctrl_dma_write_desc_len; + assign if_ctrl_dma_write_desc_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH] = app_ctrl_dma_write_desc_tag; + assign if_ctrl_dma_write_desc_valid[IF_COUNT] = app_ctrl_dma_write_desc_valid; + assign app_ctrl_dma_write_desc_ready = if_ctrl_dma_write_desc_ready[IF_COUNT]; + + assign app_ctrl_dma_write_desc_status_tag = if_ctrl_dma_write_desc_status_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH]; + assign app_ctrl_dma_write_desc_status_error = if_ctrl_dma_write_desc_status_error[IF_COUNT*4 +: 4]; + assign app_ctrl_dma_write_desc_status_valid = if_ctrl_dma_write_desc_status_valid[IF_COUNT]; + + assign if_data_dma_read_desc_dma_addr[IF_COUNT*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH] = app_data_dma_read_desc_dma_addr; + assign if_data_dma_read_desc_ram_sel[IF_COUNT*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH] = app_data_dma_read_desc_ram_sel; + assign if_data_dma_read_desc_ram_addr[IF_COUNT*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = app_data_dma_read_desc_ram_addr; + assign if_data_dma_read_desc_len[IF_COUNT*DMA_LEN_WIDTH +: DMA_LEN_WIDTH] = app_data_dma_read_desc_len; + assign if_data_dma_read_desc_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH] = app_data_dma_read_desc_tag; + assign if_data_dma_read_desc_valid[IF_COUNT] = app_data_dma_read_desc_valid; + assign app_data_dma_read_desc_ready = if_data_dma_read_desc_ready[IF_COUNT]; + + assign app_data_dma_read_desc_status_tag = if_data_dma_read_desc_status_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH]; + assign app_data_dma_read_desc_status_error = if_data_dma_read_desc_status_error[IF_COUNT*4 +: 4]; + assign app_data_dma_read_desc_status_valid = if_data_dma_read_desc_status_valid[IF_COUNT]; + + assign if_data_dma_write_desc_dma_addr[IF_COUNT*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH] = app_data_dma_write_desc_dma_addr; + assign if_data_dma_write_desc_ram_sel[IF_COUNT*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH] = app_data_dma_write_desc_ram_sel; + assign if_data_dma_write_desc_ram_addr[IF_COUNT*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = app_data_dma_write_desc_ram_addr; + assign if_data_dma_write_desc_len[IF_COUNT*DMA_LEN_WIDTH +: DMA_LEN_WIDTH] = app_data_dma_write_desc_len; + assign if_data_dma_write_desc_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH] = app_data_dma_write_desc_tag; + assign if_data_dma_write_desc_valid[IF_COUNT] = app_data_dma_write_desc_valid; + assign app_data_dma_write_desc_ready = if_data_dma_write_desc_ready[IF_COUNT]; + + assign app_data_dma_write_desc_status_tag = if_data_dma_write_desc_status_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH]; + assign app_data_dma_write_desc_status_error = if_data_dma_write_desc_status_error[IF_COUNT*4 +: 4]; + assign app_data_dma_write_desc_status_valid = if_data_dma_write_desc_status_valid[IF_COUNT]; + + assign app_ctrl_dma_ram_wr_cmd_sel = if_ctrl_dma_ram_wr_cmd_sel[RAM_SEG_COUNT*IF_RAM_SEL_WIDTH*IF_COUNT +: RAM_SEG_COUNT*IF_RAM_SEL_WIDTH]; + assign app_ctrl_dma_ram_wr_cmd_be = if_ctrl_dma_ram_wr_cmd_be[RAM_SEG_COUNT*RAM_SEG_BE_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_BE_WIDTH]; + assign app_ctrl_dma_ram_wr_cmd_addr = if_ctrl_dma_ram_wr_cmd_addr[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH]; + assign app_ctrl_dma_ram_wr_cmd_data = if_ctrl_dma_ram_wr_cmd_data[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH]; + assign app_ctrl_dma_ram_wr_cmd_valid = if_ctrl_dma_ram_wr_cmd_valid[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT]; + assign if_ctrl_dma_ram_wr_cmd_ready[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT] = app_ctrl_dma_ram_wr_cmd_ready; + assign if_ctrl_dma_ram_wr_done[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT] = app_ctrl_dma_ram_wr_done; + assign app_ctrl_dma_ram_rd_cmd_sel = if_ctrl_dma_ram_rd_cmd_sel[RAM_SEG_COUNT*IF_RAM_SEL_WIDTH*IF_COUNT +: RAM_SEG_COUNT*IF_RAM_SEL_WIDTH]; + assign app_ctrl_dma_ram_rd_cmd_addr = if_ctrl_dma_ram_rd_cmd_addr[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH]; + assign app_ctrl_dma_ram_rd_cmd_valid = if_ctrl_dma_ram_rd_cmd_valid[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT]; + assign if_ctrl_dma_ram_rd_cmd_ready[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT] = app_ctrl_dma_ram_rd_cmd_ready; + assign if_ctrl_dma_ram_rd_resp_data[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH] = app_ctrl_dma_ram_rd_resp_data; + assign if_ctrl_dma_ram_rd_resp_valid[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT] = app_ctrl_dma_ram_rd_resp_valid; + assign app_ctrl_dma_ram_rd_resp_ready = if_ctrl_dma_ram_rd_resp_ready[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT]; + + assign app_data_dma_ram_wr_cmd_sel = if_data_dma_ram_wr_cmd_sel[RAM_SEG_COUNT*IF_RAM_SEL_WIDTH*IF_COUNT +: RAM_SEG_COUNT*IF_RAM_SEL_WIDTH]; + assign app_data_dma_ram_wr_cmd_be = if_data_dma_ram_wr_cmd_be[RAM_SEG_COUNT*RAM_SEG_BE_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_BE_WIDTH]; + assign app_data_dma_ram_wr_cmd_addr = if_data_dma_ram_wr_cmd_addr[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH]; + assign app_data_dma_ram_wr_cmd_data = if_data_dma_ram_wr_cmd_data[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH]; + assign app_data_dma_ram_wr_cmd_valid = if_data_dma_ram_wr_cmd_valid[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT]; + assign if_data_dma_ram_wr_cmd_ready[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT] = app_data_dma_ram_wr_cmd_ready; + assign if_data_dma_ram_wr_done[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT] = app_data_dma_ram_wr_done; + assign app_data_dma_ram_rd_cmd_sel = if_data_dma_ram_rd_cmd_sel[RAM_SEG_COUNT*IF_RAM_SEL_WIDTH*IF_COUNT +: RAM_SEG_COUNT*IF_RAM_SEL_WIDTH]; + assign app_data_dma_ram_rd_cmd_addr = if_data_dma_ram_rd_cmd_addr[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH]; + assign app_data_dma_ram_rd_cmd_valid = if_data_dma_ram_rd_cmd_valid[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT]; + assign if_data_dma_ram_rd_cmd_ready[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT] = app_data_dma_ram_rd_cmd_ready; + assign if_data_dma_ram_rd_resp_data[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH*IF_COUNT +: RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH] = app_data_dma_ram_rd_resp_data; + assign if_data_dma_ram_rd_resp_valid[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT] = app_data_dma_ram_rd_resp_valid; + assign app_data_dma_ram_rd_resp_ready = if_data_dma_ram_rd_resp_ready[RAM_SEG_COUNT*IF_COUNT +: RAM_SEG_COUNT]; + +end else begin + + assign app_ctrl_dma_read_desc_ready = 0; + + assign app_ctrl_dma_read_desc_status_tag = 0; + assign app_ctrl_dma_read_desc_status_error = 0; + assign app_ctrl_dma_read_desc_status_valid = 0; + + assign app_ctrl_dma_write_desc_ready = 0; + + assign app_ctrl_dma_write_desc_status_tag = 0; + assign app_ctrl_dma_write_desc_status_error = 0; + assign app_ctrl_dma_write_desc_status_valid = 0; + + assign app_data_dma_read_desc_ready = 0; + + assign app_data_dma_read_desc_status_tag = 0; + assign app_data_dma_read_desc_status_error = 0; + assign app_data_dma_read_desc_status_valid = 0; + + assign app_data_dma_write_desc_ready = 0; + + assign app_data_dma_write_desc_status_tag = 0; + assign app_data_dma_write_desc_status_error = 0; + assign app_data_dma_write_desc_status_valid = 0; + + assign app_ctrl_dma_ram_wr_cmd_sel = 0; + assign app_ctrl_dma_ram_wr_cmd_be = 0; + assign app_ctrl_dma_ram_wr_cmd_addr = 0; + assign app_ctrl_dma_ram_wr_cmd_data = 0; + assign app_ctrl_dma_ram_wr_cmd_valid = 0; + assign app_ctrl_dma_ram_rd_cmd_sel = 0; + assign app_ctrl_dma_ram_rd_cmd_addr = 0; + assign app_ctrl_dma_ram_rd_cmd_valid = 0; + assign app_ctrl_dma_ram_rd_resp_ready = 0; + + assign app_data_dma_ram_wr_cmd_sel = 0; + assign app_data_dma_ram_wr_cmd_be = 0; + assign app_data_dma_ram_wr_cmd_addr = 0; + assign app_data_dma_ram_wr_cmd_data = 0; + assign app_data_dma_ram_wr_cmd_valid = 0; + assign app_data_dma_ram_rd_cmd_sel = 0; + assign app_data_dma_ram_rd_cmd_addr = 0; + assign app_data_dma_ram_rd_cmd_valid = 0; + assign app_data_dma_ram_rd_resp_ready = 0; + +end + +endgenerate + wire [MSI_COUNT-1:0] if_msi_irq[IF_COUNT-1:0]; reg [MSI_COUNT-1:0] msi_irq_cmb = 0; @@ -1482,6 +1933,127 @@ always @* begin end end +// streaming connections to application +wire [PORT_COUNT-1:0] app_direct_tx_clk = tx_clk; +wire [PORT_COUNT-1:0] app_direct_tx_rst = tx_rst; + +wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] app_s_axis_direct_tx_tdata; +wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] app_s_axis_direct_tx_tkeep; +wire [PORT_COUNT-1:0] app_s_axis_direct_tx_tvalid; +wire [PORT_COUNT-1:0] app_s_axis_direct_tx_tready; +wire [PORT_COUNT-1:0] app_s_axis_direct_tx_tlast; +wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] app_s_axis_direct_tx_tuser; + +wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] app_m_axis_direct_tx_tdata; +wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] app_m_axis_direct_tx_tkeep; +wire [PORT_COUNT-1:0] app_m_axis_direct_tx_tvalid; +wire [PORT_COUNT-1:0] app_m_axis_direct_tx_tready; +wire [PORT_COUNT-1:0] app_m_axis_direct_tx_tlast; +wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] app_m_axis_direct_tx_tuser; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_direct_tx_ptp_ts; +wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_s_axis_direct_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] app_s_axis_direct_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] app_s_axis_direct_tx_ptp_ts_ready; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_direct_tx_ptp_ts; +wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_direct_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] app_m_axis_direct_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] app_m_axis_direct_tx_ptp_ts_ready; + +wire [PORT_COUNT-1:0] app_direct_rx_clk = rx_clk; +wire [PORT_COUNT-1:0] app_direct_rx_rst = rx_rst; + +wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] app_s_axis_direct_rx_tdata; +wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] app_s_axis_direct_rx_tkeep; +wire [PORT_COUNT-1:0] app_s_axis_direct_rx_tvalid; +wire [PORT_COUNT-1:0] app_s_axis_direct_rx_tready; +wire [PORT_COUNT-1:0] app_s_axis_direct_rx_tlast; +wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] app_s_axis_direct_rx_tuser; + +wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] app_m_axis_direct_rx_tdata; +wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] app_m_axis_direct_rx_tkeep; +wire [PORT_COUNT-1:0] app_m_axis_direct_rx_tvalid; +wire [PORT_COUNT-1:0] app_m_axis_direct_rx_tready; +wire [PORT_COUNT-1:0] app_m_axis_direct_rx_tlast; +wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] app_m_axis_direct_rx_tuser; + +wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] app_s_axis_sync_tx_tdata; +wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] app_s_axis_sync_tx_tkeep; +wire [PORT_COUNT-1:0] app_s_axis_sync_tx_tvalid; +wire [PORT_COUNT-1:0] app_s_axis_sync_tx_tready; +wire [PORT_COUNT-1:0] app_s_axis_sync_tx_tlast; +wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] app_s_axis_sync_tx_tuser; + +wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] app_m_axis_sync_tx_tdata; +wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] app_m_axis_sync_tx_tkeep; +wire [PORT_COUNT-1:0] app_m_axis_sync_tx_tvalid; +wire [PORT_COUNT-1:0] app_m_axis_sync_tx_tready; +wire [PORT_COUNT-1:0] app_m_axis_sync_tx_tlast; +wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] app_m_axis_sync_tx_tuser; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_sync_tx_ptp_ts; +wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_s_axis_sync_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] app_s_axis_sync_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] app_s_axis_sync_tx_ptp_ts_ready; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_sync_tx_ptp_ts; +wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_sync_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] app_m_axis_sync_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] app_m_axis_sync_tx_ptp_ts_ready; + +wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] app_s_axis_sync_rx_tdata; +wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] app_s_axis_sync_rx_tkeep; +wire [PORT_COUNT-1:0] app_s_axis_sync_rx_tvalid; +wire [PORT_COUNT-1:0] app_s_axis_sync_rx_tready; +wire [PORT_COUNT-1:0] app_s_axis_sync_rx_tlast; +wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] app_s_axis_sync_rx_tuser; + +wire [PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0] app_m_axis_sync_rx_tdata; +wire [PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0] app_m_axis_sync_rx_tkeep; +wire [PORT_COUNT-1:0] app_m_axis_sync_rx_tvalid; +wire [PORT_COUNT-1:0] app_m_axis_sync_rx_tready; +wire [PORT_COUNT-1:0] app_m_axis_sync_rx_tlast; +wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] app_m_axis_sync_rx_tuser; + +wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_s_axis_if_tx_tdata; +wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_s_axis_if_tx_tkeep; +wire [PORT_COUNT-1:0] app_s_axis_if_tx_tvalid; +wire [PORT_COUNT-1:0] app_s_axis_if_tx_tready; +wire [PORT_COUNT-1:0] app_s_axis_if_tx_tlast; +wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] app_s_axis_if_tx_tuser; + +wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_m_axis_if_tx_tdata; +wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_m_axis_if_tx_tkeep; +wire [PORT_COUNT-1:0] app_m_axis_if_tx_tvalid; +wire [PORT_COUNT-1:0] app_m_axis_if_tx_tready; +wire [PORT_COUNT-1:0] app_m_axis_if_tx_tlast; +wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] app_m_axis_if_tx_tuser; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_if_tx_ptp_ts; +wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_s_axis_if_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] app_s_axis_if_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] app_s_axis_if_tx_ptp_ts_ready; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_if_tx_ptp_ts; +wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_if_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] app_m_axis_if_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] app_m_axis_if_tx_ptp_ts_ready; + +wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_s_axis_if_rx_tdata; +wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_s_axis_if_rx_tkeep; +wire [PORT_COUNT-1:0] app_s_axis_if_rx_tvalid; +wire [PORT_COUNT-1:0] app_s_axis_if_rx_tready; +wire [PORT_COUNT-1:0] app_s_axis_if_rx_tlast; +wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] app_s_axis_if_rx_tuser; + +wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_m_axis_if_rx_tdata; +wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_m_axis_if_rx_tkeep; +wire [PORT_COUNT-1:0] app_m_axis_if_rx_tvalid; +wire [PORT_COUNT-1:0] app_m_axis_if_rx_tready; +wire [PORT_COUNT-1:0] app_m_axis_if_rx_tlast; +wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] app_m_axis_if_rx_tuser; + generate genvar m, n; @@ -1813,10 +2385,62 @@ generate ); // PTP TS FIFO (TX) - wire [PTP_TS_WIDTH-1:0] tx_pipe_ptp_ts; - wire [PTP_TAG_WIDTH-1:0] tx_pipe_ptp_ts_tag; - wire tx_pipe_ptp_ts_valid; - wire tx_pipe_ptp_ts_ready; + wire [PTP_TS_WIDTH-1:0] axis_tx_ptp_ts; + wire [PTP_TAG_WIDTH-1:0] axis_tx_ptp_ts_tag; + wire axis_tx_ptp_ts_valid; + wire axis_tx_ptp_ts_ready; + + wire [PTP_TS_WIDTH-1:0] axis_tx_in_ptp_ts; + wire [PTP_TAG_WIDTH-1:0] axis_tx_in_ptp_ts_tag; + wire axis_tx_in_ptp_ts_valid; + wire axis_tx_in_ptp_ts_ready; + + wire [PTP_TS_WIDTH-1:0] axis_tx_fifo_ptp_ts; + wire [PTP_TAG_WIDTH-1:0] axis_tx_fifo_ptp_ts_tag; + wire axis_tx_fifo_ptp_ts_valid; + wire axis_tx_fifo_ptp_ts_ready; + + wire [PTP_TS_WIDTH-1:0] axis_tx_pipe_ptp_ts; + wire [PTP_TAG_WIDTH-1:0] axis_tx_pipe_ptp_ts_tag; + wire axis_tx_pipe_ptp_ts_valid; + wire axis_tx_pipe_ptp_ts_ready; + + wire [PTP_TS_WIDTH-1:0] axis_tx_pipe_2_ptp_ts; + wire [PTP_TAG_WIDTH-1:0] axis_tx_pipe_2_ptp_ts_tag; + wire axis_tx_pipe_2_ptp_ts_valid; + wire axis_tx_pipe_2_ptp_ts_ready; + + assign axis_tx_ptp_ts = s_axis_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH]; + assign axis_tx_ptp_ts_tag = s_axis_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; + assign axis_tx_ptp_ts_valid = s_axis_tx_ptp_ts_valid[n*PORTS_PER_IF+m +: 1]; + assign s_axis_tx_ptp_ts_ready[n*PORTS_PER_IF+m +: 1] = axis_tx_ptp_ts_ready; + + if (APP_ENABLE && APP_AXIS_DIRECT_ENABLE) begin + + assign app_s_axis_direct_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = axis_tx_ptp_ts; + assign app_s_axis_direct_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = axis_tx_ptp_ts_tag; + assign app_s_axis_direct_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = axis_tx_ptp_ts_valid; + assign axis_tx_ptp_ts_ready = app_s_axis_direct_tx_ptp_ts_ready[n*PORTS_PER_IF+m]; + + assign axis_tx_in_ptp_ts = app_m_axis_direct_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH]; + assign axis_tx_in_ptp_ts_tag = app_m_axis_direct_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; + assign axis_tx_in_ptp_ts_valid = app_m_axis_direct_tx_ptp_ts_valid[n*PORTS_PER_IF+m]; + assign app_m_axis_direct_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = axis_tx_in_ptp_ts_ready; + + end else begin + + assign app_s_axis_direct_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign app_s_axis_direct_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign app_s_axis_direct_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; + + assign app_m_axis_direct_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; + + assign axis_tx_in_ptp_ts = axis_tx_ptp_ts; + assign axis_tx_in_ptp_ts_tag = axis_tx_ptp_ts_tag; + assign axis_tx_in_ptp_ts_valid = axis_tx_ptp_ts_valid; + assign axis_tx_ptp_ts_ready = axis_tx_in_ptp_ts_ready; + + end axis_async_fifo #( .DEPTH(TX_PTP_TS_FIFO_DEPTH), @@ -1834,23 +2458,23 @@ generate // AXI input .s_clk(tx_clk[n*PORTS_PER_IF+m]), - .s_axis_tdata(s_axis_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .s_axis_tdata(axis_tx_in_ptp_ts), .s_axis_tkeep(0), - .s_axis_tvalid(s_axis_tx_ptp_ts_valid[n*PORTS_PER_IF+m +: 1]), - .s_axis_tready(s_axis_tx_ptp_ts_ready[n*PORTS_PER_IF+m +: 1]), + .s_axis_tvalid(axis_tx_in_ptp_ts_valid), + .s_axis_tready(axis_tx_in_ptp_ts_ready), .s_axis_tlast(0), - .s_axis_tid(s_axis_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]), + .s_axis_tid(axis_tx_in_ptp_ts_tag), .s_axis_tdest(0), .s_axis_tuser(0), // AXI output .m_clk(clk), - .m_axis_tdata(tx_pipe_ptp_ts), + .m_axis_tdata(axis_tx_fifo_ptp_ts), .m_axis_tkeep(), - .m_axis_tvalid(tx_pipe_ptp_ts_valid), - .m_axis_tready(tx_pipe_ptp_ts_ready), + .m_axis_tvalid(axis_tx_fifo_ptp_ts_valid), + .m_axis_tready(axis_tx_fifo_ptp_ts_ready), .m_axis_tlast(), - .m_axis_tid(tx_pipe_ptp_ts_tag), + .m_axis_tid(axis_tx_fifo_ptp_ts_tag), .m_axis_tdest(), .m_axis_tuser(), @@ -1878,26 +2502,80 @@ generate .rst(rst), // AXI input - .s_axis_tdata(tx_pipe_ptp_ts), + .s_axis_tdata(axis_tx_fifo_ptp_ts), .s_axis_tkeep(0), - .s_axis_tvalid(tx_pipe_ptp_ts_valid), - .s_axis_tready(tx_pipe_ptp_ts_ready), + .s_axis_tvalid(axis_tx_fifo_ptp_ts_valid), + .s_axis_tready(axis_tx_fifo_ptp_ts_ready), .s_axis_tlast(0), - .s_axis_tid(tx_pipe_ptp_ts_tag), + .s_axis_tid(axis_tx_fifo_ptp_ts_tag), .s_axis_tdest(0), .s_axis_tuser(0), // AXI output - .m_axis_tdata(if_tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .m_axis_tdata(axis_tx_pipe_ptp_ts), .m_axis_tkeep(), - .m_axis_tvalid(if_tx_ptp_ts_valid[m +: 1]), - .m_axis_tready(if_tx_ptp_ts_ready[m +: 1]), + .m_axis_tvalid(axis_tx_pipe_ptp_ts_valid), + .m_axis_tready(axis_tx_pipe_ptp_ts_ready), .m_axis_tlast(), - .m_axis_tid(if_tx_ptp_ts_tag[m*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]), + .m_axis_tid(axis_tx_pipe_ptp_ts_tag), .m_axis_tdest(), .m_axis_tuser() ); + if (APP_ENABLE && APP_AXIS_SYNC_ENABLE) begin + + assign app_s_axis_sync_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = axis_tx_pipe_ptp_ts; + assign app_s_axis_sync_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = axis_tx_pipe_ptp_ts_tag; + assign app_s_axis_sync_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = axis_tx_pipe_ptp_ts_valid; + assign axis_tx_pipe_ptp_ts_ready = app_s_axis_sync_tx_ptp_ts_ready[n*PORTS_PER_IF+m]; + + assign axis_tx_pipe_2_ptp_ts = app_m_axis_sync_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH]; + assign axis_tx_pipe_2_ptp_ts_tag = app_m_axis_sync_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; + assign axis_tx_pipe_2_ptp_ts_valid = app_m_axis_sync_tx_ptp_ts_valid[n*PORTS_PER_IF+m]; + assign app_m_axis_sync_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = axis_tx_pipe_2_ptp_ts_ready; + + end else begin + + assign app_s_axis_sync_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign app_s_axis_sync_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign app_s_axis_sync_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; + + assign app_m_axis_sync_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; + + assign axis_tx_pipe_2_ptp_ts = axis_tx_pipe_ptp_ts; + assign axis_tx_pipe_2_ptp_ts_tag = axis_tx_pipe_ptp_ts_tag; + assign axis_tx_pipe_2_ptp_ts_valid = axis_tx_pipe_ptp_ts_valid; + assign axis_tx_pipe_ptp_ts_ready = axis_tx_pipe_2_ptp_ts_ready; + + end + + if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin + + assign app_s_axis_if_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = axis_tx_pipe_2_ptp_ts; + assign app_s_axis_if_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = axis_tx_pipe_2_ptp_ts_tag; + assign app_s_axis_if_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = axis_tx_pipe_2_ptp_ts_valid; + assign axis_tx_pipe_2_ptp_ts_ready = app_s_axis_if_tx_ptp_ts_ready[n*PORTS_PER_IF+m]; + + assign if_tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = app_m_axis_if_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH]; + assign if_tx_ptp_ts_tag[m*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = app_m_axis_if_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; + assign if_tx_ptp_ts_valid[m +: 1] = app_m_axis_if_tx_ptp_ts_valid[n*PORTS_PER_IF+m]; + assign app_m_axis_if_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = if_tx_ptp_ts_ready[m +: 1]; + + end else begin + + assign app_s_axis_if_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign app_s_axis_if_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign app_s_axis_if_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; + + assign app_m_axis_if_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; + + assign if_tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = axis_tx_pipe_2_ptp_ts; + assign if_tx_ptp_ts_tag[m*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = axis_tx_pipe_2_ptp_ts_tag; + assign if_tx_ptp_ts_valid[m +: 1] = axis_tx_pipe_2_ptp_ts_valid; + assign axis_tx_pipe_2_ptp_ts_ready = if_tx_ptp_ts_ready[m +: 1]; + + end + wire [PTP_TS_WIDTH-1:0] rx_ts; wire rx_ts_valid; @@ -1976,9 +2654,34 @@ generate assign if_rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}}; assign if_rx_ptp_ts_valid[m +: 1] = 1'b0; + assign app_s_axis_direct_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign app_s_axis_direct_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign app_s_axis_direct_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; + + assign app_m_axis_direct_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; + + assign app_s_axis_sync_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign app_s_axis_sync_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign app_s_axis_sync_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; + + assign app_m_axis_sync_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; + + assign app_s_axis_if_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign app_s_axis_if_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign app_s_axis_if_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; + + assign app_m_axis_if_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; + end // TX FIFOs + wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_if_tx_tdata; + wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_if_tx_tkeep; + wire axis_if_tx_tvalid; + wire axis_if_tx_tready; + wire axis_if_tx_tlast; + wire [AXIS_TX_USER_WIDTH-1:0] axis_if_tx_tuser; + wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_tx_fifo_tdata; wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_tx_fifo_tkeep; wire axis_tx_fifo_tvalid; @@ -1993,6 +2696,64 @@ generate wire axis_tx_pipe_tlast; wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_pipe_tuser; + wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_tx_async_fifo_tdata; + wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_tx_async_fifo_tkeep; + wire axis_tx_async_fifo_tvalid; + wire axis_tx_async_fifo_tready; + wire axis_tx_async_fifo_tlast; + wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_async_fifo_tuser; + + wire [AXIS_DATA_WIDTH-1:0] axis_tx_out_tdata; + wire [AXIS_KEEP_WIDTH-1:0] axis_tx_out_tkeep; + wire axis_tx_out_tvalid; + wire axis_tx_out_tready; + wire axis_tx_out_tlast; + wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_out_tuser; + + wire [AXIS_DATA_WIDTH-1:0] axis_tx_tdata; + wire [AXIS_KEEP_WIDTH-1:0] axis_tx_tkeep; + wire axis_tx_tvalid; + wire axis_tx_tready; + wire axis_tx_tlast; + wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_tuser; + + if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin + + assign app_s_axis_if_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = if_tx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; + assign app_s_axis_if_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = if_tx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; + assign app_s_axis_if_tx_tvalid[n*PORTS_PER_IF+m +: 1] = if_tx_axis_tvalid[m +: 1]; + assign if_tx_axis_tready[m +: 1] = app_s_axis_if_tx_tready[n*PORTS_PER_IF+m +: 1]; + assign app_s_axis_if_tx_tlast[n*PORTS_PER_IF+m +: 1] = if_tx_axis_tlast[m +: 1]; + // assign app_s_axis_if_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH] = if_tx_axis_tuser[m*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]; + assign app_s_axis_if_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH] = {{PTP_TAG_WIDTH{1'b0}}, if_tx_axis_tuser[m +: 1]}; + + assign axis_if_tx_tdata = app_m_axis_if_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH]; + assign axis_if_tx_tkeep = app_m_axis_if_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH]; + assign axis_if_tx_tvalid = app_m_axis_if_tx_tvalid[n*PORTS_PER_IF+m]; + assign app_m_axis_if_tx_tready[n*PORTS_PER_IF+m +: 1] = axis_if_tx_tready; + assign axis_if_tx_tlast = app_m_axis_if_tx_tlast[n*PORTS_PER_IF+m]; + assign axis_if_tx_tuser = app_m_axis_if_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH]; + + end else begin + + assign app_s_axis_if_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = 0; + assign app_s_axis_if_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = 0; + assign app_s_axis_if_tx_tvalid[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_if_tx_tlast[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_if_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH] = 0; + + assign app_m_axis_if_tx_tready[n*PORTS_PER_IF+m +: 1] = 0; + + assign axis_if_tx_tdata = if_tx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; + assign axis_if_tx_tkeep = if_tx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; + assign axis_if_tx_tvalid = if_tx_axis_tvalid[m +: 1]; + assign if_tx_axis_tready[m +: 1] = axis_if_tx_tready; + assign axis_if_tx_tlast = if_tx_axis_tlast[m +: 1]; + // assign axis_if_tx_tuser = if_tx_axis_tuser[m*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]; + assign axis_if_tx_tuser = {{PTP_TAG_WIDTH{1'b0}}, if_tx_axis_tuser[m +: 1]}; + + end + axis_fifo #( .DEPTH(TX_FIFO_DEPTH), .DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), @@ -2015,15 +2776,14 @@ generate .rst(rst), // AXI input - .s_axis_tdata(if_tx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]), - .s_axis_tkeep(if_tx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]), - .s_axis_tvalid(if_tx_axis_tvalid[m +: 1]), - .s_axis_tready(if_tx_axis_tready[m +: 1]), - .s_axis_tlast(if_tx_axis_tlast[m +: 1]), + .s_axis_tdata(axis_if_tx_tdata), + .s_axis_tkeep(axis_if_tx_tkeep), + .s_axis_tvalid(axis_if_tx_tvalid), + .s_axis_tready(axis_if_tx_tready), + .s_axis_tlast(axis_if_tx_tlast), .s_axis_tid(0), .s_axis_tdest(0), - // .s_axis_tuser(if_tx_axis_tuser[m*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]), - .s_axis_tuser({{PTP_TAG_WIDTH{1'b0}}, if_tx_axis_tuser[m +: 1]}), + .s_axis_tuser(axis_if_tx_tuser), // AXI output .m_axis_tdata(axis_tx_fifo_tdata), @@ -2041,6 +2801,41 @@ generate .status_good_frame() ); + if (APP_ENABLE && APP_AXIS_SYNC_ENABLE) begin + + assign app_s_axis_sync_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = axis_tx_fifo_tdata; + assign app_s_axis_sync_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = axis_tx_fifo_tkeep; + assign app_s_axis_sync_tx_tvalid[n*PORTS_PER_IF+m] = axis_tx_fifo_tvalid; + assign axis_tx_fifo_tready = app_s_axis_sync_tx_tready[n*PORTS_PER_IF+m +: 1]; + assign app_s_axis_sync_tx_tlast[n*PORTS_PER_IF+m] = axis_tx_fifo_tlast; + assign app_s_axis_sync_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH] = axis_tx_fifo_tuser; + + assign axis_tx_pipe_tdata = app_m_axis_sync_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; + assign axis_tx_pipe_tkeep = app_m_axis_sync_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; + assign axis_tx_pipe_tvalid = app_m_axis_sync_tx_tvalid[n*PORTS_PER_IF+m +: 1]; + assign app_m_axis_sync_tx_tready[n*PORTS_PER_IF+m +: 1] = axis_tx_pipe_tready; + assign axis_tx_pipe_tlast = app_m_axis_sync_tx_tlast[n*PORTS_PER_IF+m +: 1]; + assign axis_tx_pipe_tuser = app_m_axis_sync_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]; + + end else begin + + assign app_s_axis_sync_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = 0; + assign app_s_axis_sync_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = 0; + assign app_s_axis_sync_tx_tvalid[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_sync_tx_tlast[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_sync_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH] = 0; + + assign app_m_axis_sync_tx_tready[n*PORTS_PER_IF+m +: 1] = 0; + + assign axis_tx_pipe_tdata = axis_tx_fifo_tdata; + assign axis_tx_pipe_tkeep = axis_tx_fifo_tkeep; + assign axis_tx_pipe_tvalid = axis_tx_fifo_tvalid; + assign axis_tx_fifo_tready = axis_tx_pipe_tready; + assign axis_tx_pipe_tlast = axis_tx_fifo_tlast; + assign axis_tx_pipe_tuser = axis_tx_fifo_tuser; + + end + axis_pipeline_fifo #( .DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), .KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1), @@ -2057,24 +2852,24 @@ generate .rst(rst), // AXI input - .s_axis_tdata(axis_tx_fifo_tdata), - .s_axis_tkeep(axis_tx_fifo_tkeep), - .s_axis_tvalid(axis_tx_fifo_tvalid), - .s_axis_tready(axis_tx_fifo_tready), - .s_axis_tlast(axis_tx_fifo_tlast), + .s_axis_tdata(axis_tx_pipe_tdata), + .s_axis_tkeep(axis_tx_pipe_tkeep), + .s_axis_tvalid(axis_tx_pipe_tvalid), + .s_axis_tready(axis_tx_pipe_tready), + .s_axis_tlast(axis_tx_pipe_tlast), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser(axis_tx_fifo_tuser), + .s_axis_tuser(axis_tx_pipe_tuser), // AXI output - .m_axis_tdata(axis_tx_pipe_tdata), - .m_axis_tkeep(axis_tx_pipe_tkeep), - .m_axis_tvalid(axis_tx_pipe_tvalid), - .m_axis_tready(axis_tx_pipe_tready), - .m_axis_tlast(axis_tx_pipe_tlast), + .m_axis_tdata(axis_tx_async_fifo_tdata), + .m_axis_tkeep(axis_tx_async_fifo_tkeep), + .m_axis_tvalid(axis_tx_async_fifo_tvalid), + .m_axis_tready(axis_tx_async_fifo_tready), + .m_axis_tlast(axis_tx_async_fifo_tlast), .m_axis_tid(), .m_axis_tdest(), - .m_axis_tuser(axis_tx_pipe_tuser) + .m_axis_tuser(axis_tx_async_fifo_tuser) ); axis_async_fifo_adapter #( @@ -2099,26 +2894,26 @@ generate // AXI input .s_clk(clk), .s_rst(rst), - .s_axis_tdata(axis_tx_pipe_tdata), - .s_axis_tkeep(axis_tx_pipe_tkeep), - .s_axis_tvalid(axis_tx_pipe_tvalid), - .s_axis_tready(axis_tx_pipe_tready), - .s_axis_tlast(axis_tx_pipe_tlast), + .s_axis_tdata(axis_tx_async_fifo_tdata), + .s_axis_tkeep(axis_tx_async_fifo_tkeep), + .s_axis_tvalid(axis_tx_async_fifo_tvalid), + .s_axis_tready(axis_tx_async_fifo_tready), + .s_axis_tlast(axis_tx_async_fifo_tlast), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser(axis_tx_pipe_tuser), + .s_axis_tuser(axis_tx_async_fifo_tuser), // AXI output .m_clk(tx_clk[n*PORTS_PER_IF+m]), .m_rst(tx_rst[n*PORTS_PER_IF+m]), - .m_axis_tdata(m_axis_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), - .m_axis_tkeep(m_axis_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), - .m_axis_tvalid(m_axis_tx_tvalid[n*PORTS_PER_IF+m]), - .m_axis_tready(m_axis_tx_tready[n*PORTS_PER_IF+m]), - .m_axis_tlast(m_axis_tx_tlast[n*PORTS_PER_IF+m]), + .m_axis_tdata(axis_tx_out_tdata), + .m_axis_tkeep(axis_tx_out_tkeep), + .m_axis_tvalid(axis_tx_out_tvalid), + .m_axis_tready(axis_tx_out_tready), + .m_axis_tlast(axis_tx_out_tlast), .m_axis_tid(), .m_axis_tdest(), - .m_axis_tuser(m_axis_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]), + .m_axis_tuser(axis_tx_out_tuser), // Status .s_status_overflow(), @@ -2129,13 +2924,69 @@ generate .m_status_good_frame() ); + if (APP_ENABLE && APP_AXIS_DIRECT_ENABLE) begin + + assign app_s_axis_direct_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = axis_tx_out_tdata; + assign app_s_axis_direct_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = axis_tx_out_tkeep; + assign app_s_axis_direct_tx_tvalid[n*PORTS_PER_IF+m +: 1] = axis_tx_out_tvalid; + assign axis_tx_out_tready = app_s_axis_direct_tx_tready[n*PORTS_PER_IF+m +: 1]; + assign app_s_axis_direct_tx_tlast[n*PORTS_PER_IF+m +: 1] = axis_tx_out_tlast; + assign app_s_axis_direct_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH] = axis_tx_out_tuser; + + assign axis_tx_tdata = app_m_axis_direct_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]; + assign axis_tx_tkeep = app_m_axis_direct_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]; + assign axis_tx_tvalid = app_m_axis_direct_tx_tvalid[n*PORTS_PER_IF+m +: 1]; + assign app_m_axis_direct_tx_tready[n*PORTS_PER_IF+m +: 1] = axis_tx_tready; + assign axis_tx_tlast = app_m_axis_direct_tx_tlast[n*PORTS_PER_IF+m +: 1]; + assign axis_tx_tuser = app_m_axis_direct_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]; + + end else begin + + assign app_s_axis_direct_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = 0; + assign app_s_axis_direct_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = 0; + assign app_s_axis_direct_tx_tvalid[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_direct_tx_tlast[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_direct_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH] = 0; + + assign app_m_axis_direct_tx_tready[n*PORTS_PER_IF+m +: 1] = 0; + + assign axis_tx_tdata = axis_tx_out_tdata; + assign axis_tx_tkeep = axis_tx_out_tkeep; + assign axis_tx_tvalid = axis_tx_out_tvalid; + assign axis_tx_out_tready = axis_tx_tready; + assign axis_tx_tlast = axis_tx_out_tlast; + assign axis_tx_tuser = axis_tx_out_tuser; + + end + + assign m_axis_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = axis_tx_tdata; + assign m_axis_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = axis_tx_tkeep; + assign m_axis_tx_tvalid[n*PORTS_PER_IF+m +: 1] = axis_tx_tvalid; + assign axis_tx_tready = m_axis_tx_tready[n*PORTS_PER_IF+m +: 1]; + assign m_axis_tx_tlast[n*PORTS_PER_IF+m +: 1] = axis_tx_tlast; + assign m_axis_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH] = axis_tx_tuser; + // RX FIFOs - wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_rx_fifo_tdata; - wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_rx_fifo_tkeep; - wire axis_rx_fifo_tvalid; - wire axis_rx_fifo_tready; - wire axis_rx_fifo_tlast; - wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_fifo_tuser; + wire [AXIS_DATA_WIDTH-1:0] axis_rx_tdata; + wire [AXIS_KEEP_WIDTH-1:0] axis_rx_tkeep; + wire axis_rx_tvalid; + wire axis_rx_tready; + wire axis_rx_tlast; + wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_tuser; + + wire [AXIS_DATA_WIDTH-1:0] axis_rx_in_tdata; + wire [AXIS_KEEP_WIDTH-1:0] axis_rx_in_tkeep; + wire axis_rx_in_tvalid; + wire axis_rx_in_tready; + wire axis_rx_in_tlast; + wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_in_tuser; + + wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_rx_async_fifo_tdata; + wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_rx_async_fifo_tkeep; + wire axis_rx_async_fifo_tvalid; + wire axis_rx_async_fifo_tready; + wire axis_rx_async_fifo_tlast; + wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_async_fifo_tuser; wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_rx_pipe_tdata; wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_rx_pipe_tkeep; @@ -2144,6 +2995,62 @@ generate wire axis_rx_pipe_tlast; wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_pipe_tuser; + wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_rx_fifo_tdata; + wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_rx_fifo_tkeep; + wire axis_rx_fifo_tvalid; + wire axis_rx_fifo_tready; + wire axis_rx_fifo_tlast; + wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_fifo_tuser; + + wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_if_rx_tdata; + wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_if_rx_tkeep; + wire axis_if_rx_tvalid; + wire axis_if_rx_tready; + wire axis_if_rx_tlast; + wire [AXIS_RX_USER_WIDTH-1:0] axis_if_rx_tuser; + + assign axis_rx_tdata = s_axis_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]; + assign axis_rx_tkeep = s_axis_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]; + assign axis_rx_tvalid = s_axis_rx_tvalid[n*PORTS_PER_IF+m +: 1]; + assign s_axis_rx_tready[n*PORTS_PER_IF+m +: 1] = axis_rx_tready; + assign axis_rx_tlast = s_axis_rx_tlast[n*PORTS_PER_IF+m +: 1]; + assign axis_rx_tuser = s_axis_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]; + + if (APP_ENABLE && APP_AXIS_DIRECT_ENABLE) begin + + assign app_s_axis_direct_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = axis_rx_tdata; + assign app_s_axis_direct_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = axis_rx_tkeep; + assign app_s_axis_direct_rx_tvalid[n*PORTS_PER_IF+m +: 1] = axis_rx_tvalid; + assign axis_rx_tready = app_s_axis_direct_rx_tready[n*PORTS_PER_IF+m +: 1]; + assign app_s_axis_direct_rx_tlast[n*PORTS_PER_IF+m +: 1] = axis_rx_tlast; + assign app_s_axis_direct_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = axis_rx_tuser; + + assign axis_rx_in_tdata = app_m_axis_direct_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]; + assign axis_rx_in_tkeep = app_m_axis_direct_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]; + assign axis_rx_in_tvalid = app_m_axis_direct_rx_tvalid[n*PORTS_PER_IF+m +: 1]; + assign app_m_axis_direct_rx_tready[n*PORTS_PER_IF+m +: 1] = axis_rx_in_tready; + assign axis_rx_in_tlast = app_m_axis_direct_rx_tlast[n*PORTS_PER_IF+m +: 1]; + assign axis_rx_in_tuser = app_m_axis_direct_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]; + + end else begin + + assign app_s_axis_direct_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = 0; + assign app_s_axis_direct_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = 0; + assign app_s_axis_direct_rx_tvalid[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_direct_rx_tlast[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_direct_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = 0; + + assign app_m_axis_direct_rx_tready[n*PORTS_PER_IF+m +: 1] = 0; + + assign axis_rx_in_tdata = axis_rx_tdata; + assign axis_rx_in_tkeep = axis_rx_tkeep; + assign axis_rx_in_tvalid = axis_rx_tvalid; + assign axis_rx_tready = axis_rx_in_tready; + assign axis_rx_in_tlast = axis_rx_tlast; + assign axis_rx_in_tuser = axis_rx_tuser; + + end + axis_async_fifo_adapter #( .DEPTH(MAX_RX_SIZE), .S_DATA_WIDTH(AXIS_DATA_WIDTH), @@ -2166,26 +3073,26 @@ generate // AXI input .s_clk(rx_clk[n*PORTS_PER_IF+m]), .s_rst(rx_rst[n*PORTS_PER_IF+m]), - .s_axis_tdata(s_axis_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), - .s_axis_tkeep(s_axis_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), - .s_axis_tvalid(s_axis_rx_tvalid[n*PORTS_PER_IF+m]), - .s_axis_tready(s_axis_rx_tready[n*PORTS_PER_IF+m]), - .s_axis_tlast(s_axis_rx_tlast[n*PORTS_PER_IF+m]), + .s_axis_tdata(axis_rx_in_tdata), + .s_axis_tkeep(axis_rx_in_tkeep), + .s_axis_tvalid(axis_rx_in_tvalid), + .s_axis_tready(axis_rx_in_tready), + .s_axis_tlast(axis_rx_in_tlast), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser(s_axis_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]), + .s_axis_tuser(axis_rx_in_tuser), // AXI output .m_clk(clk), .m_rst(rst), - .m_axis_tdata(axis_rx_fifo_tdata), - .m_axis_tkeep(axis_rx_fifo_tkeep), - .m_axis_tvalid(axis_rx_fifo_tvalid), - .m_axis_tready(axis_rx_fifo_tready), - .m_axis_tlast(axis_rx_fifo_tlast), + .m_axis_tdata(axis_rx_async_fifo_tdata), + .m_axis_tkeep(axis_rx_async_fifo_tkeep), + .m_axis_tvalid(axis_rx_async_fifo_tvalid), + .m_axis_tready(axis_rx_async_fifo_tready), + .m_axis_tlast(axis_rx_async_fifo_tlast), .m_axis_tid(), .m_axis_tdest(), - .m_axis_tuser(axis_rx_fifo_tuser), + .m_axis_tuser(axis_rx_async_fifo_tuser), // Status .s_status_overflow(), @@ -2212,14 +3119,14 @@ generate .rst(rst), // AXI input - .s_axis_tdata(axis_rx_fifo_tdata), - .s_axis_tkeep(axis_rx_fifo_tkeep), - .s_axis_tvalid(axis_rx_fifo_tvalid), - .s_axis_tready(axis_rx_fifo_tready), - .s_axis_tlast(axis_rx_fifo_tlast), + .s_axis_tdata(axis_rx_async_fifo_tdata), + .s_axis_tkeep(axis_rx_async_fifo_tkeep), + .s_axis_tvalid(axis_rx_async_fifo_tvalid), + .s_axis_tready(axis_rx_async_fifo_tready), + .s_axis_tlast(axis_rx_async_fifo_tlast), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser(axis_rx_fifo_tuser), + .s_axis_tuser(axis_rx_async_fifo_tuser), // AXI output .m_axis_tdata(axis_rx_pipe_tdata), @@ -2232,6 +3139,41 @@ generate .m_axis_tuser(axis_rx_pipe_tuser) ); + if (APP_ENABLE && APP_AXIS_SYNC_ENABLE) begin + + assign app_s_axis_sync_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = axis_rx_pipe_tdata; + assign app_s_axis_sync_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = axis_rx_pipe_tkeep; + assign app_s_axis_sync_rx_tvalid[n*PORTS_PER_IF+m] = axis_rx_pipe_tvalid; + assign axis_rx_pipe_tready = app_s_axis_sync_rx_tready[n*PORTS_PER_IF+m +: 1]; + assign app_s_axis_sync_rx_tlast[n*PORTS_PER_IF+m] = axis_rx_pipe_tlast; + assign app_s_axis_sync_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = axis_rx_pipe_tuser; + + assign axis_rx_fifo_tdata = app_m_axis_sync_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; + assign axis_rx_fifo_tkeep = app_m_axis_sync_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; + assign axis_rx_fifo_tvalid = app_m_axis_sync_rx_tvalid[n*PORTS_PER_IF+m +: 1]; + assign app_m_axis_sync_rx_tready[n*PORTS_PER_IF+m +: 1] = axis_rx_fifo_tready; + assign axis_rx_fifo_tlast = app_m_axis_sync_rx_tlast[n*PORTS_PER_IF+m +: 1]; + assign axis_rx_fifo_tuser = app_m_axis_sync_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]; + + end else begin + + assign app_s_axis_sync_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = 0; + assign app_s_axis_sync_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = 0; + assign app_s_axis_sync_rx_tvalid[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_sync_rx_tlast[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_sync_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = 0; + + assign app_m_axis_sync_rx_tready[n*PORTS_PER_IF+m +: 1] = 0; + + assign axis_rx_fifo_tdata = axis_rx_pipe_tdata; + assign axis_rx_fifo_tkeep = axis_rx_pipe_tkeep; + assign axis_rx_fifo_tvalid = axis_rx_pipe_tvalid; + assign axis_rx_pipe_tready = axis_rx_fifo_tready; + assign axis_rx_fifo_tlast = axis_rx_pipe_tlast; + assign axis_rx_fifo_tuser = axis_rx_pipe_tuser; + + end + axis_fifo #( .DEPTH(RX_FIFO_DEPTH), .DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), @@ -2254,25 +3196,24 @@ generate .rst(rst), // AXI input - .s_axis_tdata(axis_rx_pipe_tdata), - .s_axis_tkeep(axis_rx_pipe_tkeep), - .s_axis_tvalid(axis_rx_pipe_tvalid), - .s_axis_tready(axis_rx_pipe_tready), - .s_axis_tlast(axis_rx_pipe_tlast), + .s_axis_tdata(axis_rx_fifo_tdata), + .s_axis_tkeep(axis_rx_fifo_tkeep), + .s_axis_tvalid(axis_rx_fifo_tvalid), + .s_axis_tready(axis_rx_fifo_tready), + .s_axis_tlast(axis_rx_fifo_tlast), .s_axis_tid(0), .s_axis_tdest(0), - .s_axis_tuser(axis_rx_pipe_tuser), + .s_axis_tuser(axis_rx_fifo_tuser), // AXI output - .m_axis_tdata(if_rx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]), - .m_axis_tkeep(if_rx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]), - .m_axis_tvalid(if_rx_axis_tvalid[m +: 1]), - .m_axis_tready(if_rx_axis_tready[m +: 1]), - .m_axis_tlast(if_rx_axis_tlast[m +: 1]), + .m_axis_tdata(axis_if_rx_tdata), + .m_axis_tkeep(axis_if_rx_tkeep), + .m_axis_tvalid(axis_if_rx_tvalid), + .m_axis_tready(axis_if_rx_tready), + .m_axis_tlast(axis_if_rx_tlast), .m_axis_tid(), .m_axis_tdest(), - // .m_axis_tuser(if_rx_axis_tuser[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]), - .m_axis_tuser(if_rx_axis_tuser_int[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]), + .m_axis_tuser(axis_if_rx_tuser), // Status .status_overflow(), @@ -2280,6 +3221,43 @@ generate .status_good_frame() ); + if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin + + assign app_s_axis_if_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = axis_if_rx_tdata; + assign app_s_axis_if_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = axis_if_rx_tkeep; + assign app_s_axis_if_rx_tvalid[n*PORTS_PER_IF+m +: 1] = axis_if_rx_tvalid; + assign axis_if_rx_tready = app_s_axis_if_rx_tready[n*PORTS_PER_IF+m +: 1]; + assign app_s_axis_if_rx_tlast[n*PORTS_PER_IF+m +: 1] = axis_if_rx_tlast; + assign app_s_axis_if_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH] = axis_if_rx_tuser; + + assign if_rx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = app_m_axis_if_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH]; + assign if_rx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = app_m_axis_if_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH]; + assign if_rx_axis_tvalid[m +: 1] = app_m_axis_if_rx_tvalid[n*PORTS_PER_IF+m +: 1]; + assign app_m_axis_if_rx_tready[n*PORTS_PER_IF+m +: 1] = if_rx_axis_tready[m +: 1]; + assign if_rx_axis_tlast[m +: 1] = app_m_axis_if_rx_tlast[n*PORTS_PER_IF+m +: 1]; + // assign if_rx_axis_tuser[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = app_m_axis_if_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH]; + assign if_rx_axis_tuser_int[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = app_m_axis_if_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH]; + + end else begin + + assign app_s_axis_if_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = 0; + assign app_s_axis_if_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = 0; + assign app_s_axis_if_rx_tvalid[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_if_rx_tlast[n*PORTS_PER_IF+m +: 1] = 0; + assign app_s_axis_if_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH] = 0; + + assign app_m_axis_if_rx_tready[n*PORTS_PER_IF+m +: 1] = 0; + + assign if_rx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = axis_if_rx_tdata; + assign if_rx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = axis_if_rx_tkeep; + assign if_rx_axis_tvalid[m +: 1] = axis_if_rx_tvalid; + assign axis_if_rx_tready = if_rx_axis_tready[m +: 1]; + assign if_rx_axis_tlast[m +: 1] = axis_if_rx_tlast; + // assign if_rx_axis_tuser[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = axis_if_rx_tuser; + assign if_rx_axis_tuser_int[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = axis_if_rx_tuser; + + end + assign if_rx_axis_tuser[m +: 1] = if_rx_axis_tuser_int[m*AXIS_RX_USER_WIDTH +: 1]; end @@ -2288,4 +3266,526 @@ generate endgenerate +generate + +if (APP_ENABLE) begin : app + + mqnic_app_block #( + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + // PTP configuration + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH), + .PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH), + .PTP_FNS_WIDTH(PTP_FNS_WIDTH), + .PTP_PERIOD_NS(PTP_PERIOD_NS), + .PTP_PERIOD_FNS(PTP_PERIOD_FNS), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + + // Application configuration + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE && STAT_ENABLE), + + // DMA interface configuration + .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(IF_DMA_TAG_WIDTH), + .RAM_SEG_COUNT(RAM_SEG_COUNT), + .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), + .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), + .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), + .RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // AXI lite interface (application control from host) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + .AXIL_APP_CTRL_STRB_WIDTH(AXIL_APP_CTRL_STRB_WIDTH), + + // AXI lite interface (control to NIC) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + + // Ethernet interface configuration (direct, async) + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH), + .AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH), + .AXIS_RX_USE_READY(AXIS_RX_USE_READY), + + // Ethernet interface configuration (direct, sync) + .AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), + .AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH), + .AXIS_SYNC_TX_USER_WIDTH(AXIS_TX_USER_WIDTH), + .AXIS_SYNC_RX_USER_WIDTH(AXIS_RX_USER_WIDTH), + + // Ethernet interface configuration (interface) + .AXIS_IF_DATA_WIDTH(AXIS_IF_DATA_WIDTH), + .AXIS_IF_KEEP_WIDTH(AXIS_IF_KEEP_WIDTH), + .AXIS_IF_TX_USER_WIDTH(AXIS_IF_TX_USER_WIDTH), + .AXIS_IF_RX_USER_WIDTH(AXIS_IF_RX_USER_WIDTH), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) + ) + app_block_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI-Lite slave interface (control from host) + */ + .s_axil_app_ctrl_awaddr(s_axil_app_ctrl_awaddr), + .s_axil_app_ctrl_awprot(s_axil_app_ctrl_awprot), + .s_axil_app_ctrl_awvalid(s_axil_app_ctrl_awvalid), + .s_axil_app_ctrl_awready(s_axil_app_ctrl_awready), + .s_axil_app_ctrl_wdata(s_axil_app_ctrl_wdata), + .s_axil_app_ctrl_wstrb(s_axil_app_ctrl_wstrb), + .s_axil_app_ctrl_wvalid(s_axil_app_ctrl_wvalid), + .s_axil_app_ctrl_wready(s_axil_app_ctrl_wready), + .s_axil_app_ctrl_bresp(s_axil_app_ctrl_bresp), + .s_axil_app_ctrl_bvalid(s_axil_app_ctrl_bvalid), + .s_axil_app_ctrl_bready(s_axil_app_ctrl_bready), + .s_axil_app_ctrl_araddr(s_axil_app_ctrl_araddr), + .s_axil_app_ctrl_arprot(s_axil_app_ctrl_arprot), + .s_axil_app_ctrl_arvalid(s_axil_app_ctrl_arvalid), + .s_axil_app_ctrl_arready(s_axil_app_ctrl_arready), + .s_axil_app_ctrl_rdata(s_axil_app_ctrl_rdata), + .s_axil_app_ctrl_rresp(s_axil_app_ctrl_rresp), + .s_axil_app_ctrl_rvalid(s_axil_app_ctrl_rvalid), + .s_axil_app_ctrl_rready(s_axil_app_ctrl_rready), + + /* + * AXI-Lite master interface (control to NIC) + */ + .m_axil_ctrl_awaddr(axil_ctrl_app_awaddr), + .m_axil_ctrl_awprot(axil_ctrl_app_awprot), + .m_axil_ctrl_awvalid(axil_ctrl_app_awvalid), + .m_axil_ctrl_awready(axil_ctrl_app_awready), + .m_axil_ctrl_wdata(axil_ctrl_app_wdata), + .m_axil_ctrl_wstrb(axil_ctrl_app_wstrb), + .m_axil_ctrl_wvalid(axil_ctrl_app_wvalid), + .m_axil_ctrl_wready(axil_ctrl_app_wready), + .m_axil_ctrl_bresp(axil_ctrl_app_bresp), + .m_axil_ctrl_bvalid(axil_ctrl_app_bvalid), + .m_axil_ctrl_bready(axil_ctrl_app_bready), + .m_axil_ctrl_araddr(axil_ctrl_app_araddr), + .m_axil_ctrl_arprot(axil_ctrl_app_arprot), + .m_axil_ctrl_arvalid(axil_ctrl_app_arvalid), + .m_axil_ctrl_arready(axil_ctrl_app_arready), + .m_axil_ctrl_rdata(axil_ctrl_app_rdata), + .m_axil_ctrl_rresp(axil_ctrl_app_rresp), + .m_axil_ctrl_rvalid(axil_ctrl_app_rvalid), + .m_axil_ctrl_rready(axil_ctrl_app_rready), + + /* + * DMA read descriptor output (control) + */ + .m_axis_ctrl_dma_read_desc_dma_addr(app_ctrl_dma_read_desc_dma_addr), + .m_axis_ctrl_dma_read_desc_ram_sel(app_ctrl_dma_read_desc_ram_sel), + .m_axis_ctrl_dma_read_desc_ram_addr(app_ctrl_dma_read_desc_ram_addr), + .m_axis_ctrl_dma_read_desc_len(app_ctrl_dma_read_desc_len), + .m_axis_ctrl_dma_read_desc_tag(app_ctrl_dma_read_desc_tag), + .m_axis_ctrl_dma_read_desc_valid(app_ctrl_dma_read_desc_valid), + .m_axis_ctrl_dma_read_desc_ready(app_ctrl_dma_read_desc_ready), + + /* + * DMA read descriptor status input (control) + */ + .s_axis_ctrl_dma_read_desc_status_tag(app_ctrl_dma_read_desc_status_tag), + .s_axis_ctrl_dma_read_desc_status_error(app_ctrl_dma_read_desc_status_error), + .s_axis_ctrl_dma_read_desc_status_valid(app_ctrl_dma_read_desc_status_valid), + + /* + * DMA write descriptor output (control) + */ + .m_axis_ctrl_dma_write_desc_dma_addr(app_ctrl_dma_write_desc_dma_addr), + .m_axis_ctrl_dma_write_desc_ram_sel(app_ctrl_dma_write_desc_ram_sel), + .m_axis_ctrl_dma_write_desc_ram_addr(app_ctrl_dma_write_desc_ram_addr), + .m_axis_ctrl_dma_write_desc_len(app_ctrl_dma_write_desc_len), + .m_axis_ctrl_dma_write_desc_tag(app_ctrl_dma_write_desc_tag), + .m_axis_ctrl_dma_write_desc_valid(app_ctrl_dma_write_desc_valid), + .m_axis_ctrl_dma_write_desc_ready(app_ctrl_dma_write_desc_ready), + + /* + * DMA write descriptor status input (control) + */ + .s_axis_ctrl_dma_write_desc_status_tag(app_ctrl_dma_write_desc_status_tag), + .s_axis_ctrl_dma_write_desc_status_error(app_ctrl_dma_write_desc_status_error), + .s_axis_ctrl_dma_write_desc_status_valid(app_ctrl_dma_write_desc_status_valid), + + /* + * DMA read descriptor output (data) + */ + .m_axis_data_dma_read_desc_dma_addr(app_data_dma_read_desc_dma_addr), + .m_axis_data_dma_read_desc_ram_sel(app_data_dma_read_desc_ram_sel), + .m_axis_data_dma_read_desc_ram_addr(app_data_dma_read_desc_ram_addr), + .m_axis_data_dma_read_desc_len(app_data_dma_read_desc_len), + .m_axis_data_dma_read_desc_tag(app_data_dma_read_desc_tag), + .m_axis_data_dma_read_desc_valid(app_data_dma_read_desc_valid), + .m_axis_data_dma_read_desc_ready(app_data_dma_read_desc_ready), + + /* + * DMA read descriptor status input (data) + */ + .s_axis_data_dma_read_desc_status_tag(app_data_dma_read_desc_status_tag), + .s_axis_data_dma_read_desc_status_error(app_data_dma_read_desc_status_error), + .s_axis_data_dma_read_desc_status_valid(app_data_dma_read_desc_status_valid), + + /* + * DMA write descriptor output (data) + */ + .m_axis_data_dma_write_desc_dma_addr(app_data_dma_write_desc_dma_addr), + .m_axis_data_dma_write_desc_ram_sel(app_data_dma_write_desc_ram_sel), + .m_axis_data_dma_write_desc_ram_addr(app_data_dma_write_desc_ram_addr), + .m_axis_data_dma_write_desc_len(app_data_dma_write_desc_len), + .m_axis_data_dma_write_desc_tag(app_data_dma_write_desc_tag), + .m_axis_data_dma_write_desc_valid(app_data_dma_write_desc_valid), + .m_axis_data_dma_write_desc_ready(app_data_dma_write_desc_ready), + + /* + * DMA write descriptor status input (data) + */ + .s_axis_data_dma_write_desc_status_tag(app_data_dma_write_desc_status_tag), + .s_axis_data_dma_write_desc_status_error(app_data_dma_write_desc_status_error), + .s_axis_data_dma_write_desc_status_valid(app_data_dma_write_desc_status_valid), + + /* + * RAM interface (control) + */ + .ctrl_dma_ram_wr_cmd_sel(app_ctrl_dma_ram_wr_cmd_sel), + .ctrl_dma_ram_wr_cmd_be(app_ctrl_dma_ram_wr_cmd_be), + .ctrl_dma_ram_wr_cmd_addr(app_ctrl_dma_ram_wr_cmd_addr), + .ctrl_dma_ram_wr_cmd_data(app_ctrl_dma_ram_wr_cmd_data), + .ctrl_dma_ram_wr_cmd_valid(app_ctrl_dma_ram_wr_cmd_valid), + .ctrl_dma_ram_wr_cmd_ready(app_ctrl_dma_ram_wr_cmd_ready), + .ctrl_dma_ram_wr_done(app_ctrl_dma_ram_wr_done), + .ctrl_dma_ram_rd_cmd_sel(app_ctrl_dma_ram_rd_cmd_sel), + .ctrl_dma_ram_rd_cmd_addr(app_ctrl_dma_ram_rd_cmd_addr), + .ctrl_dma_ram_rd_cmd_valid(app_ctrl_dma_ram_rd_cmd_valid), + .ctrl_dma_ram_rd_cmd_ready(app_ctrl_dma_ram_rd_cmd_ready), + .ctrl_dma_ram_rd_resp_data(app_ctrl_dma_ram_rd_resp_data), + .ctrl_dma_ram_rd_resp_valid(app_ctrl_dma_ram_rd_resp_valid), + .ctrl_dma_ram_rd_resp_ready(app_ctrl_dma_ram_rd_resp_ready), + + /* + * RAM interface (data) + */ + .data_dma_ram_wr_cmd_sel(app_data_dma_ram_wr_cmd_sel), + .data_dma_ram_wr_cmd_be(app_data_dma_ram_wr_cmd_be), + .data_dma_ram_wr_cmd_addr(app_data_dma_ram_wr_cmd_addr), + .data_dma_ram_wr_cmd_data(app_data_dma_ram_wr_cmd_data), + .data_dma_ram_wr_cmd_valid(app_data_dma_ram_wr_cmd_valid), + .data_dma_ram_wr_cmd_ready(app_data_dma_ram_wr_cmd_ready), + .data_dma_ram_wr_done(app_data_dma_ram_wr_done), + .data_dma_ram_rd_cmd_sel(app_data_dma_ram_rd_cmd_sel), + .data_dma_ram_rd_cmd_addr(app_data_dma_ram_rd_cmd_addr), + .data_dma_ram_rd_cmd_valid(app_data_dma_ram_rd_cmd_valid), + .data_dma_ram_rd_cmd_ready(app_data_dma_ram_rd_cmd_ready), + .data_dma_ram_rd_resp_data(app_data_dma_ram_rd_resp_data), + .data_dma_ram_rd_resp_valid(app_data_dma_ram_rd_resp_valid), + .data_dma_ram_rd_resp_ready(app_data_dma_ram_rd_resp_ready), + + /* + * PTP clock + */ + .ptp_sample_clk(ptp_sample_clk), + .ptp_pps(ptp_pps), + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + .ptp_perout_locked(ptp_perout_locked), + .ptp_perout_error(ptp_perout_error), + .ptp_perout_pulse(ptp_perout_pulse), + + /* + * Ethernet (direct MAC interface - lowest latency raw traffic) + */ + .direct_tx_clk(app_direct_tx_clk), + .direct_tx_rst(app_direct_tx_rst), + + .s_axis_direct_tx_tdata(app_s_axis_direct_tx_tdata), + .s_axis_direct_tx_tkeep(app_s_axis_direct_tx_tkeep), + .s_axis_direct_tx_tvalid(app_s_axis_direct_tx_tvalid), + .s_axis_direct_tx_tready(app_s_axis_direct_tx_tready), + .s_axis_direct_tx_tlast(app_s_axis_direct_tx_tlast), + .s_axis_direct_tx_tuser(app_s_axis_direct_tx_tuser), + + .m_axis_direct_tx_tdata(app_m_axis_direct_tx_tdata), + .m_axis_direct_tx_tkeep(app_m_axis_direct_tx_tkeep), + .m_axis_direct_tx_tvalid(app_m_axis_direct_tx_tvalid), + .m_axis_direct_tx_tready(app_m_axis_direct_tx_tready), + .m_axis_direct_tx_tlast(app_m_axis_direct_tx_tlast), + .m_axis_direct_tx_tuser(app_m_axis_direct_tx_tuser), + + .s_axis_direct_tx_ptp_ts(app_s_axis_direct_tx_ptp_ts), + .s_axis_direct_tx_ptp_ts_tag(app_s_axis_direct_tx_ptp_ts_tag), + .s_axis_direct_tx_ptp_ts_valid(app_s_axis_direct_tx_ptp_ts_valid), + .s_axis_direct_tx_ptp_ts_ready(app_s_axis_direct_tx_ptp_ts_ready), + + .m_axis_direct_tx_ptp_ts(app_m_axis_direct_tx_ptp_ts), + .m_axis_direct_tx_ptp_ts_tag(app_m_axis_direct_tx_ptp_ts_tag), + .m_axis_direct_tx_ptp_ts_valid(app_m_axis_direct_tx_ptp_ts_valid), + .m_axis_direct_tx_ptp_ts_ready(app_m_axis_direct_tx_ptp_ts_ready), + + .direct_rx_clk(app_direct_rx_clk), + .direct_rx_rst(app_direct_rx_rst), + + .s_axis_direct_rx_tdata(app_s_axis_direct_rx_tdata), + .s_axis_direct_rx_tkeep(app_s_axis_direct_rx_tkeep), + .s_axis_direct_rx_tvalid(app_s_axis_direct_rx_tvalid), + .s_axis_direct_rx_tready(app_s_axis_direct_rx_tready), + .s_axis_direct_rx_tlast(app_s_axis_direct_rx_tlast), + .s_axis_direct_rx_tuser(app_s_axis_direct_rx_tuser), + + .m_axis_direct_rx_tdata(app_m_axis_direct_rx_tdata), + .m_axis_direct_rx_tkeep(app_m_axis_direct_rx_tkeep), + .m_axis_direct_rx_tvalid(app_m_axis_direct_rx_tvalid), + .m_axis_direct_rx_tready(app_m_axis_direct_rx_tready), + .m_axis_direct_rx_tlast(app_m_axis_direct_rx_tlast), + .m_axis_direct_rx_tuser(app_m_axis_direct_rx_tuser), + + /* + * Ethernet (synchronous MAC interface - low latency raw traffic) + */ + .s_axis_sync_tx_tdata(app_s_axis_sync_tx_tdata), + .s_axis_sync_tx_tkeep(app_s_axis_sync_tx_tkeep), + .s_axis_sync_tx_tvalid(app_s_axis_sync_tx_tvalid), + .s_axis_sync_tx_tready(app_s_axis_sync_tx_tready), + .s_axis_sync_tx_tlast(app_s_axis_sync_tx_tlast), + .s_axis_sync_tx_tuser(app_s_axis_sync_tx_tuser), + + .m_axis_sync_tx_tdata(app_m_axis_sync_tx_tdata), + .m_axis_sync_tx_tkeep(app_m_axis_sync_tx_tkeep), + .m_axis_sync_tx_tvalid(app_m_axis_sync_tx_tvalid), + .m_axis_sync_tx_tready(app_m_axis_sync_tx_tready), + .m_axis_sync_tx_tlast(app_m_axis_sync_tx_tlast), + .m_axis_sync_tx_tuser(app_m_axis_sync_tx_tuser), + + .s_axis_sync_tx_ptp_ts(app_s_axis_sync_tx_ptp_ts), + .s_axis_sync_tx_ptp_ts_tag(app_s_axis_sync_tx_ptp_ts_tag), + .s_axis_sync_tx_ptp_ts_valid(app_s_axis_sync_tx_ptp_ts_valid), + .s_axis_sync_tx_ptp_ts_ready(app_s_axis_sync_tx_ptp_ts_ready), + + .m_axis_sync_tx_ptp_ts(app_m_axis_sync_tx_ptp_ts), + .m_axis_sync_tx_ptp_ts_tag(app_m_axis_sync_tx_ptp_ts_tag), + .m_axis_sync_tx_ptp_ts_valid(app_m_axis_sync_tx_ptp_ts_valid), + .m_axis_sync_tx_ptp_ts_ready(app_m_axis_sync_tx_ptp_ts_ready), + + .s_axis_sync_rx_tdata(app_s_axis_sync_rx_tdata), + .s_axis_sync_rx_tkeep(app_s_axis_sync_rx_tkeep), + .s_axis_sync_rx_tvalid(app_s_axis_sync_rx_tvalid), + .s_axis_sync_rx_tready(app_s_axis_sync_rx_tready), + .s_axis_sync_rx_tlast(app_s_axis_sync_rx_tlast), + .s_axis_sync_rx_tuser(app_s_axis_sync_rx_tuser), + + .m_axis_sync_rx_tdata(app_m_axis_sync_rx_tdata), + .m_axis_sync_rx_tkeep(app_m_axis_sync_rx_tkeep), + .m_axis_sync_rx_tvalid(app_m_axis_sync_rx_tvalid), + .m_axis_sync_rx_tready(app_m_axis_sync_rx_tready), + .m_axis_sync_rx_tlast(app_m_axis_sync_rx_tlast), + .m_axis_sync_rx_tuser(app_m_axis_sync_rx_tuser), + + /* + * Ethernet (internal at interface module) + */ + .s_axis_if_tx_tdata(app_s_axis_if_tx_tdata), + .s_axis_if_tx_tkeep(app_s_axis_if_tx_tkeep), + .s_axis_if_tx_tvalid(app_s_axis_if_tx_tvalid), + .s_axis_if_tx_tready(app_s_axis_if_tx_tready), + .s_axis_if_tx_tlast(app_s_axis_if_tx_tlast), + .s_axis_if_tx_tuser(app_s_axis_if_tx_tuser), + + .m_axis_if_tx_tdata(app_m_axis_if_tx_tdata), + .m_axis_if_tx_tkeep(app_m_axis_if_tx_tkeep), + .m_axis_if_tx_tvalid(app_m_axis_if_tx_tvalid), + .m_axis_if_tx_tready(app_m_axis_if_tx_tready), + .m_axis_if_tx_tlast(app_m_axis_if_tx_tlast), + .m_axis_if_tx_tuser(app_m_axis_if_tx_tuser), + + .s_axis_if_tx_ptp_ts(app_s_axis_if_tx_ptp_ts), + .s_axis_if_tx_ptp_ts_tag(app_s_axis_if_tx_ptp_ts_tag), + .s_axis_if_tx_ptp_ts_valid(app_s_axis_if_tx_ptp_ts_valid), + .s_axis_if_tx_ptp_ts_ready(app_s_axis_if_tx_ptp_ts_ready), + + .m_axis_if_tx_ptp_ts(app_m_axis_if_tx_ptp_ts), + .m_axis_if_tx_ptp_ts_tag(app_m_axis_if_tx_ptp_ts_tag), + .m_axis_if_tx_ptp_ts_valid(app_m_axis_if_tx_ptp_ts_valid), + .m_axis_if_tx_ptp_ts_ready(app_m_axis_if_tx_ptp_ts_ready), + + .s_axis_if_rx_tdata(app_s_axis_if_rx_tdata), + .s_axis_if_rx_tkeep(app_s_axis_if_rx_tkeep), + .s_axis_if_rx_tvalid(app_s_axis_if_rx_tvalid), + .s_axis_if_rx_tready(app_s_axis_if_rx_tready), + .s_axis_if_rx_tlast(app_s_axis_if_rx_tlast), + .s_axis_if_rx_tuser(app_s_axis_if_rx_tuser), + + .m_axis_if_rx_tdata(app_m_axis_if_rx_tdata), + .m_axis_if_rx_tkeep(app_m_axis_if_rx_tkeep), + .m_axis_if_rx_tvalid(app_m_axis_if_rx_tvalid), + .m_axis_if_rx_tready(app_m_axis_if_rx_tready), + .m_axis_if_rx_tlast(app_m_axis_if_rx_tlast), + .m_axis_if_rx_tuser(app_m_axis_if_rx_tuser), + + /* + * Statistics increment output + */ + .m_axis_stat_tdata(axis_app_stat_tdata), + .m_axis_stat_tid(axis_app_stat_tid), + .m_axis_stat_tvalid(axis_app_stat_tvalid), + .m_axis_stat_tready(axis_app_stat_tready) + ); + +end else begin + + assign s_axil_app_ctrl_awready = 1'b0; + assign s_axil_app_ctrl_wready = 1'b0; + assign s_axil_app_ctrl_bresp = 0; + assign s_axil_app_ctrl_bvalid = 1'b0; + assign s_axil_app_ctrl_arready = 1'b0; + assign s_axil_app_ctrl_rdata = 0; + assign s_axil_app_ctrl_rresp = 0; + assign s_axil_app_ctrl_rvalid = 1'b0; + + assign axil_ctrl_app_awaddr = 0; + assign axil_ctrl_app_awprot = 0; + assign axil_ctrl_app_awvalid = 1'b0; + assign axil_ctrl_app_wdata = 0; + assign axil_ctrl_app_wstrb = 0; + assign axil_ctrl_app_wvalid = 1'b0; + assign axil_ctrl_app_bready = 1'b0; + assign axil_ctrl_app_araddr = 0; + assign axil_ctrl_app_arprot = 0; + assign axil_ctrl_app_arvalid = 1'b0; + assign axil_ctrl_app_rready = 1'b0; + + assign app_ctrl_dma_read_desc_dma_addr = 0; + assign app_ctrl_dma_read_desc_ram_sel = 0; + assign app_ctrl_dma_read_desc_ram_addr = 0; + assign app_ctrl_dma_read_desc_len = 0; + assign app_ctrl_dma_read_desc_tag = 0; + assign app_ctrl_dma_read_desc_valid = 0; + + assign app_ctrl_dma_write_desc_dma_addr = 0; + assign app_ctrl_dma_write_desc_ram_sel = 0; + assign app_ctrl_dma_write_desc_ram_addr = 0; + assign app_ctrl_dma_write_desc_len = 0; + assign app_ctrl_dma_write_desc_tag = 0; + assign app_ctrl_dma_write_desc_valid = 0; + + assign app_data_dma_read_desc_dma_addr = 0; + assign app_data_dma_read_desc_ram_sel = 0; + assign app_data_dma_read_desc_ram_addr = 0; + assign app_data_dma_read_desc_len = 0; + assign app_data_dma_read_desc_tag = 0; + assign app_data_dma_read_desc_valid = 0; + + assign app_data_dma_write_desc_dma_addr = 0; + assign app_data_dma_write_desc_ram_sel = 0; + assign app_data_dma_write_desc_ram_addr = 0; + assign app_data_dma_write_desc_len = 0; + assign app_data_dma_write_desc_tag = 0; + assign app_data_dma_write_desc_valid = 0; + + assign app_ctrl_dma_ram_wr_cmd_ready = 0; + assign app_ctrl_dma_ram_wr_done = 0; + assign app_ctrl_dma_ram_rd_cmd_ready = 0; + assign app_ctrl_dma_ram_rd_resp_data = 0; + assign app_ctrl_dma_ram_rd_resp_valid = 0; + + assign app_data_dma_ram_wr_cmd_ready = 0; + assign app_data_dma_ram_wr_done = 0; + assign app_data_dma_ram_rd_cmd_ready = 0; + assign app_data_dma_ram_rd_resp_data = 0; + assign app_data_dma_ram_rd_resp_valid = 0; + + assign app_s_axis_direct_tx_tready = 0; + + assign app_m_axis_direct_tx_tdata = 0; + assign app_m_axis_direct_tx_tkeep = 0; + assign app_m_axis_direct_tx_tvalid = 0; + assign app_m_axis_direct_tx_tlast = 0; + assign app_m_axis_direct_tx_tuser = 0; + + assign app_s_axis_direct_tx_ptp_ts_ready = 0; + + assign app_m_axis_direct_tx_ptp_ts = 0; + assign app_m_axis_direct_tx_ptp_ts_tag = 0; + assign app_m_axis_direct_tx_ptp_ts_valid = 0; + + assign app_s_axis_direct_rx_tready = 0; + + assign app_m_axis_direct_rx_tdata = 0; + assign app_m_axis_direct_rx_tkeep = 0; + assign app_m_axis_direct_rx_tvalid = 0; + assign app_m_axis_direct_rx_tlast = 0; + assign app_m_axis_direct_rx_tuser = 0; + + assign app_s_axis_sync_tx_tready = 0; + + assign app_m_axis_sync_tx_tdata = 0; + assign app_m_axis_sync_tx_tkeep = 0; + assign app_m_axis_sync_tx_tvalid = 0; + assign app_m_axis_sync_tx_tlast = 0; + assign app_m_axis_sync_tx_tuser = 0; + + assign app_s_axis_sync_tx_ptp_ts_ready = 0; + + assign app_m_axis_sync_tx_ptp_ts = 0; + assign app_m_axis_sync_tx_ptp_ts_tag = 0; + assign app_m_axis_sync_tx_ptp_ts_valid = 0; + + assign app_s_axis_sync_rx_tready = 0; + + assign app_m_axis_sync_rx_tdata = 0; + assign app_m_axis_sync_rx_tkeep = 0; + assign app_m_axis_sync_rx_tvalid = 0; + assign app_m_axis_sync_rx_tlast = 0; + assign app_m_axis_sync_rx_tuser = 0; + + assign app_s_axis_if_tx_tready = 0; + + assign app_m_axis_if_tx_tdata = 0; + assign app_m_axis_if_tx_tkeep = 0; + assign app_m_axis_if_tx_tvalid = 0; + assign app_m_axis_if_tx_tlast = 0; + assign app_m_axis_if_tx_tuser = 0; + + assign app_s_axis_if_tx_ptp_ts_ready = 0; + + assign app_m_axis_if_tx_ptp_ts = 0; + assign app_m_axis_if_tx_ptp_ts_tag = 0; + assign app_m_axis_if_tx_ptp_ts_valid = 0; + + assign app_s_axis_if_rx_tready = 0; + + assign app_m_axis_if_rx_tdata = 0; + assign app_m_axis_if_rx_tkeep = 0; + assign app_m_axis_if_rx_tvalid = 0; + assign app_m_axis_if_rx_tlast = 0; + assign app_m_axis_if_rx_tuser = 0; + + assign axis_app_stat_tdata = 0; + assign axis_app_stat_tid = 0; + assign axis_app_stat_tvalid = 1'b0; + +end + +endgenerate + endmodule diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index f87af2a0c..8d2a0962e 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -106,6 +106,15 @@ module mqnic_core_pcie # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_LEN_WIDTH = 16, parameter DMA_TAG_WIDTH = 16, @@ -141,6 +150,10 @@ module mqnic_core_pcie # parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8), parameter AXIL_CSR_PASSTHROUGH_ENABLE = 0, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + // Ethernet interface configuration parameter AXIS_DATA_WIDTH = 512, parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, @@ -357,9 +370,46 @@ parameter RAM_SEG_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH*2/RAM_SEG_COUNT; parameter RAM_SEG_ADDR_WIDTH = 12; parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8; parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1; -parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; +parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH); +parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8); + +// PCIe connections +wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_ctrl_rx_req_tlp_data; +wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_ctrl_rx_req_tlp_hdr; +wire [TLP_SEG_COUNT*3-1:0] pcie_ctrl_rx_req_tlp_bar_id; +wire [TLP_SEG_COUNT*8-1:0] pcie_ctrl_rx_req_tlp_func_num; +wire [TLP_SEG_COUNT-1:0] pcie_ctrl_rx_req_tlp_valid; +wire [TLP_SEG_COUNT-1:0] pcie_ctrl_rx_req_tlp_sop; +wire [TLP_SEG_COUNT-1:0] pcie_ctrl_rx_req_tlp_eop; +wire pcie_ctrl_rx_req_tlp_ready; + +wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_data; +wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_strb; +wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_hdr; +wire [TLP_SEG_COUNT-1:0] pcie_ctrl_tx_cpl_tlp_valid; +wire [TLP_SEG_COUNT-1:0] pcie_ctrl_tx_cpl_tlp_sop; +wire [TLP_SEG_COUNT-1:0] pcie_ctrl_tx_cpl_tlp_eop; +wire pcie_ctrl_tx_cpl_tlp_ready; + +wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_app_ctrl_rx_req_tlp_data; +wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_app_ctrl_rx_req_tlp_hdr; +wire [TLP_SEG_COUNT*3-1:0] pcie_app_ctrl_rx_req_tlp_bar_id; +wire [TLP_SEG_COUNT*8-1:0] pcie_app_ctrl_rx_req_tlp_func_num; +wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_rx_req_tlp_valid; +wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_rx_req_tlp_sop; +wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_rx_req_tlp_eop; +wire pcie_app_ctrl_rx_req_tlp_ready; + +wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_data; +wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_strb; +wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_hdr; +wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_tx_cpl_tlp_valid; +wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_tx_cpl_tlp_sop; +wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_tx_cpl_tlp_eop; +wire pcie_app_ctrl_tx_cpl_tlp_ready; + // AXI lite connections wire [AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_awaddr; wire [2:0] axil_ctrl_awprot; @@ -381,6 +431,26 @@ wire [1:0] axil_ctrl_rresp; wire axil_ctrl_rvalid; wire axil_ctrl_rready; +wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] axil_app_ctrl_awaddr; +wire [2:0] axil_app_ctrl_awprot; +wire axil_app_ctrl_awvalid; +wire axil_app_ctrl_awready; +wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] axil_app_ctrl_wdata; +wire [AXIL_APP_CTRL_STRB_WIDTH-1:0] axil_app_ctrl_wstrb; +wire axil_app_ctrl_wvalid; +wire axil_app_ctrl_wready; +wire [1:0] axil_app_ctrl_bresp; +wire axil_app_ctrl_bvalid; +wire axil_app_ctrl_bready; +wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] axil_app_ctrl_araddr; +wire [2:0] axil_app_ctrl_arprot; +wire axil_app_ctrl_arvalid; +wire axil_app_ctrl_arready; +wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] axil_app_ctrl_rdata; +wire [1:0] axil_app_ctrl_rresp; +wire axil_app_ctrl_rvalid; +wire axil_app_ctrl_rready; + // DMA connections wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel; wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be; @@ -398,8 +468,8 @@ wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid; wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready; // Error handling -wire [1:0] pcie_error_uncor_int; -wire [1:0] pcie_error_cor_int; +wire [2:0] pcie_error_uncor_int; +wire [2:0] pcie_error_cor_int; // DMA control wire [DMA_ADDR_WIDTH-1:0] dma_read_desc_dma_addr; @@ -428,6 +498,246 @@ wire dma_write_desc_status_valid; wire dma_enable = 1; +generate + +if (APP_ENABLE) begin : pcie_tlp_mux + + pcie_tlp_demux_bar #( + .PORTS(2), + .TLP_SEG_COUNT(TLP_SEG_COUNT), + .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), + .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), + .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), + .BAR_BASE(0), + .BAR_STRIDE(2), + .BAR_IDS(0) + ) + pcie_tlp_demux_inst ( + .clk(clk), + .rst(rst), + + /* + * TLP input + */ + .in_tlp_data(pcie_rx_req_tlp_data), + .in_tlp_strb(0), + .in_tlp_hdr(pcie_rx_req_tlp_hdr), + .in_tlp_bar_id(pcie_rx_req_tlp_bar_id), + .in_tlp_func_num(pcie_rx_req_tlp_func_num), + .in_tlp_error(0), + .in_tlp_valid(pcie_rx_req_tlp_valid), + .in_tlp_sop(pcie_rx_req_tlp_sop), + .in_tlp_eop(pcie_rx_req_tlp_eop), + .in_tlp_ready(pcie_rx_req_tlp_ready), + + /* + * TLP output + */ + .out_tlp_data( {pcie_app_ctrl_rx_req_tlp_data, pcie_ctrl_rx_req_tlp_data }), + .out_tlp_strb(), + .out_tlp_hdr( {pcie_app_ctrl_rx_req_tlp_hdr, pcie_ctrl_rx_req_tlp_hdr }), + .out_tlp_bar_id( {pcie_app_ctrl_rx_req_tlp_bar_id, pcie_ctrl_rx_req_tlp_bar_id }), + .out_tlp_func_num({pcie_app_ctrl_rx_req_tlp_func_num, pcie_ctrl_rx_req_tlp_func_num}), + .out_tlp_error(), + .out_tlp_valid( {pcie_app_ctrl_rx_req_tlp_valid, pcie_ctrl_rx_req_tlp_valid }), + .out_tlp_sop( {pcie_app_ctrl_rx_req_tlp_sop, pcie_ctrl_rx_req_tlp_sop }), + .out_tlp_eop( {pcie_app_ctrl_rx_req_tlp_eop, pcie_ctrl_rx_req_tlp_eop }), + .out_tlp_ready( {pcie_app_ctrl_rx_req_tlp_ready, pcie_ctrl_rx_req_tlp_ready }), + + /* + * Control + */ + .enable(1'b1) + ); + + pcie_tlp_mux #( + .PORTS(2), + .TLP_SEG_COUNT(TLP_SEG_COUNT), + .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), + .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), + .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), + .ARB_TYPE_ROUND_ROBIN(1), + .ARB_LSB_HIGH_PRIORITY(1) + ) + pcie_tlp_mux_inst ( + .clk(clk), + .rst(rst), + + /* + * TLP input + */ + .in_tlp_data( {pcie_app_ctrl_tx_cpl_tlp_data, pcie_ctrl_tx_cpl_tlp_data }), + .in_tlp_strb( {pcie_app_ctrl_tx_cpl_tlp_strb, pcie_ctrl_tx_cpl_tlp_strb }), + .in_tlp_hdr( {pcie_app_ctrl_tx_cpl_tlp_hdr, pcie_ctrl_tx_cpl_tlp_hdr }), + .in_tlp_bar_id(0), + .in_tlp_func_num(0), + .in_tlp_error(0), + .in_tlp_valid({pcie_app_ctrl_tx_cpl_tlp_valid, pcie_ctrl_tx_cpl_tlp_valid}), + .in_tlp_sop( {pcie_app_ctrl_tx_cpl_tlp_sop, pcie_ctrl_tx_cpl_tlp_sop }), + .in_tlp_eop( {pcie_app_ctrl_tx_cpl_tlp_eop, pcie_ctrl_tx_cpl_tlp_eop }), + .in_tlp_ready({pcie_app_ctrl_tx_cpl_tlp_ready, pcie_ctrl_tx_cpl_tlp_ready}), + + /* + * TLP output + */ + .out_tlp_data(pcie_tx_cpl_tlp_data), + .out_tlp_strb(pcie_tx_cpl_tlp_strb), + .out_tlp_hdr(pcie_tx_cpl_tlp_hdr), + .out_tlp_bar_id(), + .out_tlp_func_num(), + .out_tlp_error(), + .out_tlp_valid(pcie_tx_cpl_tlp_valid), + .out_tlp_sop(pcie_tx_cpl_tlp_sop), + .out_tlp_eop(pcie_tx_cpl_tlp_eop), + .out_tlp_ready(pcie_tx_cpl_tlp_ready) + ); + +end else begin + + assign pcie_ctrl_rx_req_tlp_data = pcie_rx_req_tlp_data; + assign pcie_ctrl_rx_req_tlp_hdr = pcie_rx_req_tlp_hdr; + assign pcie_ctrl_rx_req_tlp_bar_id = pcie_rx_req_tlp_bar_id; + assign pcie_ctrl_rx_req_tlp_func_num = pcie_rx_req_tlp_func_num; + assign pcie_ctrl_rx_req_tlp_valid = pcie_rx_req_tlp_valid; + assign pcie_ctrl_rx_req_tlp_sop = pcie_rx_req_tlp_sop; + assign pcie_ctrl_rx_req_tlp_eop = pcie_rx_req_tlp_eop; + assign pcie_rx_req_tlp_ready = pcie_ctrl_rx_req_tlp_ready; + + assign pcie_tx_cpl_tlp_data = pcie_ctrl_tx_cpl_tlp_data; + assign pcie_tx_cpl_tlp_strb = pcie_ctrl_tx_cpl_tlp_strb; + assign pcie_tx_cpl_tlp_hdr = pcie_ctrl_tx_cpl_tlp_hdr; + assign pcie_tx_cpl_tlp_valid = pcie_ctrl_tx_cpl_tlp_valid; + assign pcie_tx_cpl_tlp_sop = pcie_ctrl_tx_cpl_tlp_sop; + assign pcie_tx_cpl_tlp_eop = pcie_ctrl_tx_cpl_tlp_eop; + assign pcie_ctrl_tx_cpl_tlp_ready = pcie_tx_cpl_tlp_ready; + + assign pcie_app_ctrl_rx_req_tlp_data = 0; + assign pcie_app_ctrl_rx_req_tlp_hdr = 0; + assign pcie_app_ctrl_rx_req_tlp_valid = 0; + assign pcie_app_ctrl_rx_req_tlp_sop = 0; + assign pcie_app_ctrl_rx_req_tlp_eop = 0; + + assign pcie_app_ctrl_tx_cpl_tlp_ready = 1'b1; + + assign axil_app_ctrl_awaddr = 0; + assign axil_app_ctrl_awprot = 0; + assign axil_app_ctrl_awvalid = 1'b0; + assign axil_app_ctrl_wdata = 0; + assign axil_app_ctrl_wstrb = 0; + assign axil_app_ctrl_wvalid = 1'b0; + assign axil_app_ctrl_bready = 1'b1; + assign axil_app_ctrl_araddr = 0; + assign axil_app_ctrl_arprot = 0; + assign axil_app_ctrl_arvalid = 1'b0; + assign axil_app_ctrl_rready = 1'b1; + + assign pcie_error_cor_int[1] = 1'b0; + assign pcie_error_uncor_int[1] = 1'b0; + +end + +if (APP_ENABLE) begin : pcie_app_ctrl + + pcie_axil_master #( + .TLP_SEG_COUNT(TLP_SEG_COUNT), + .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), + .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), + .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), + .AXIL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + .AXIL_STRB_WIDTH(AXIL_APP_CTRL_STRB_WIDTH), + .TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR) + ) + pcie_axil_master_inst ( + .clk(clk), + .rst(rst), + + /* + * TLP input (request) + */ + .rx_req_tlp_data(pcie_app_ctrl_rx_req_tlp_data), + .rx_req_tlp_hdr(pcie_app_ctrl_rx_req_tlp_hdr), + .rx_req_tlp_valid(pcie_app_ctrl_rx_req_tlp_valid), + .rx_req_tlp_sop(pcie_app_ctrl_rx_req_tlp_sop), + .rx_req_tlp_eop(pcie_app_ctrl_rx_req_tlp_eop), + .rx_req_tlp_ready(pcie_app_ctrl_rx_req_tlp_ready), + + /* + * TLP output (completion) + */ + .tx_cpl_tlp_data(pcie_app_ctrl_tx_cpl_tlp_data), + .tx_cpl_tlp_strb(pcie_app_ctrl_tx_cpl_tlp_strb), + .tx_cpl_tlp_hdr(pcie_app_ctrl_tx_cpl_tlp_hdr), + .tx_cpl_tlp_valid(pcie_app_ctrl_tx_cpl_tlp_valid), + .tx_cpl_tlp_sop(pcie_app_ctrl_tx_cpl_tlp_sop), + .tx_cpl_tlp_eop(pcie_app_ctrl_tx_cpl_tlp_eop), + .tx_cpl_tlp_ready(pcie_app_ctrl_tx_cpl_tlp_ready), + + /* + * AXI Lite Master output + */ + .m_axil_awaddr(axil_app_ctrl_awaddr), + .m_axil_awprot(axil_app_ctrl_awprot), + .m_axil_awvalid(axil_app_ctrl_awvalid), + .m_axil_awready(axil_app_ctrl_awready), + .m_axil_wdata(axil_app_ctrl_wdata), + .m_axil_wstrb(axil_app_ctrl_wstrb), + .m_axil_wvalid(axil_app_ctrl_wvalid), + .m_axil_wready(axil_app_ctrl_wready), + .m_axil_bresp(axil_app_ctrl_bresp), + .m_axil_bvalid(axil_app_ctrl_bvalid), + .m_axil_bready(axil_app_ctrl_bready), + .m_axil_araddr(axil_app_ctrl_araddr), + .m_axil_arprot(axil_app_ctrl_arprot), + .m_axil_arvalid(axil_app_ctrl_arvalid), + .m_axil_arready(axil_app_ctrl_arready), + .m_axil_rdata(axil_app_ctrl_rdata), + .m_axil_rresp(axil_app_ctrl_rresp), + .m_axil_rvalid(axil_app_ctrl_rvalid), + .m_axil_rready(axil_app_ctrl_rready), + + /* + * Configuration + */ + .completer_id({8'd0, 5'd0, 3'd0}), + + /* + * Status + */ + .status_error_cor(pcie_error_cor_int[1]), + .status_error_uncor(pcie_error_uncor_int[1]) + ); + +end else begin + + assign pcie_app_ctrl_rx_req_tlp_ready = 1'b1; + + assign pcie_app_ctrl_tx_cpl_tlp_data = 0; + assign pcie_app_ctrl_tx_cpl_tlp_strb = 0; + assign pcie_app_ctrl_tx_cpl_tlp_hdr = 0; + assign pcie_app_ctrl_tx_cpl_tlp_valid = 0; + assign pcie_app_ctrl_tx_cpl_tlp_sop = 0; + assign pcie_app_ctrl_tx_cpl_tlp_eop = 0; + + assign axil_app_ctrl_awaddr = 0; + assign axil_app_ctrl_awprot = 0; + assign axil_app_ctrl_awvalid = 1'b0; + assign axil_app_ctrl_wdata = 0; + assign axil_app_ctrl_wstrb = 0; + assign axil_app_ctrl_wvalid = 1'b0; + assign axil_app_ctrl_bready = 1'b1; + assign axil_app_ctrl_araddr = 0; + assign axil_app_ctrl_arprot = 0; + assign axil_app_ctrl_arvalid = 1'b0; + assign axil_app_ctrl_rready = 1'b1; + + assign pcie_error_cor_int[1] = 1'b0; + assign pcie_error_uncor_int[1] = 1'b0; + +end + +endgenerate + pcie_axil_master #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), @@ -445,23 +755,23 @@ pcie_axil_master_inst ( /* * TLP input (request) */ - .rx_req_tlp_data(pcie_rx_req_tlp_data), - .rx_req_tlp_hdr(pcie_rx_req_tlp_hdr), - .rx_req_tlp_valid(pcie_rx_req_tlp_valid), - .rx_req_tlp_sop(pcie_rx_req_tlp_sop), - .rx_req_tlp_eop(pcie_rx_req_tlp_eop), - .rx_req_tlp_ready(pcie_rx_req_tlp_ready), + .rx_req_tlp_data(pcie_ctrl_rx_req_tlp_data), + .rx_req_tlp_hdr(pcie_ctrl_rx_req_tlp_hdr), + .rx_req_tlp_valid(pcie_ctrl_rx_req_tlp_valid), + .rx_req_tlp_sop(pcie_ctrl_rx_req_tlp_sop), + .rx_req_tlp_eop(pcie_ctrl_rx_req_tlp_eop), + .rx_req_tlp_ready(pcie_ctrl_rx_req_tlp_ready), /* * TLP output (completion) */ - .tx_cpl_tlp_data(pcie_tx_cpl_tlp_data), - .tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb), - .tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr), - .tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid), - .tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop), - .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), - .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + .tx_cpl_tlp_data(pcie_ctrl_tx_cpl_tlp_data), + .tx_cpl_tlp_strb(pcie_ctrl_tx_cpl_tlp_strb), + .tx_cpl_tlp_hdr(pcie_ctrl_tx_cpl_tlp_hdr), + .tx_cpl_tlp_valid(pcie_ctrl_tx_cpl_tlp_valid), + .tx_cpl_tlp_sop(pcie_ctrl_tx_cpl_tlp_sop), + .tx_cpl_tlp_eop(pcie_ctrl_tx_cpl_tlp_eop), + .tx_cpl_tlp_ready(pcie_ctrl_tx_cpl_tlp_ready), /* * AXI Lite Master output @@ -678,8 +988,8 @@ dma_if_pcie_inst ( /* * Status */ - .status_error_cor(pcie_error_cor_int[1]), - .status_error_uncor(pcie_error_uncor_int[1]), + .status_error_cor(pcie_error_cor_int[2]), + .status_error_uncor(pcie_error_uncor_int[2]), /* * Statistics @@ -721,7 +1031,7 @@ dma_if_pcie_inst ( ); pulse_merge #( - .INPUT_WIDTH(2), + .INPUT_WIDTH(3), .COUNT_WIDTH(4) ) pcie_error_cor_pm_inst ( @@ -734,7 +1044,7 @@ pcie_error_cor_pm_inst ( ); pulse_merge #( - .INPUT_WIDTH(2), + .INPUT_WIDTH(3), .COUNT_WIDTH(4) ) pcie_error_uncor_pm_inst ( @@ -1038,6 +1348,15 @@ mqnic_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // Application block configuration + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + // DMA interface configuration .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), .DMA_LEN_WIDTH(DMA_LEN_WIDTH), @@ -1061,6 +1380,11 @@ mqnic_core #( .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .AXIL_CSR_PASSTHROUGH_ENABLE(AXIL_CSR_PASSTHROUGH_ENABLE), + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + .AXIL_APP_CTRL_STRB_WIDTH(AXIL_APP_CTRL_STRB_WIDTH), + // Ethernet interface configuration .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), @@ -1142,6 +1466,29 @@ core_inst ( .s_axil_ctrl_rvalid(axil_ctrl_rvalid), .s_axil_ctrl_rready(axil_ctrl_rready), + /* + * AXI-Lite slave interface (application control) + */ + .s_axil_app_ctrl_awaddr(axil_app_ctrl_awaddr), + .s_axil_app_ctrl_awprot(axil_app_ctrl_awprot), + .s_axil_app_ctrl_awvalid(axil_app_ctrl_awvalid), + .s_axil_app_ctrl_awready(axil_app_ctrl_awready), + .s_axil_app_ctrl_wdata(axil_app_ctrl_wdata), + .s_axil_app_ctrl_wstrb(axil_app_ctrl_wstrb), + .s_axil_app_ctrl_wvalid(axil_app_ctrl_wvalid), + .s_axil_app_ctrl_wready(axil_app_ctrl_wready), + .s_axil_app_ctrl_bresp(axil_app_ctrl_bresp), + .s_axil_app_ctrl_bvalid(axil_app_ctrl_bvalid), + .s_axil_app_ctrl_bready(axil_app_ctrl_bready), + .s_axil_app_ctrl_araddr(axil_app_ctrl_araddr), + .s_axil_app_ctrl_arprot(axil_app_ctrl_arprot), + .s_axil_app_ctrl_arvalid(axil_app_ctrl_arvalid), + .s_axil_app_ctrl_arready(axil_app_ctrl_arready), + .s_axil_app_ctrl_rdata(axil_app_ctrl_rdata), + .s_axil_app_ctrl_rresp(axil_app_ctrl_rresp), + .s_axil_app_ctrl_rvalid(axil_app_ctrl_rvalid), + .s_axil_app_ctrl_rready(axil_app_ctrl_rready), + /* * AXI-Lite master interface (passthrough for NIC control and status) */ diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index 42dbe1b17..828966d38 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -106,6 +106,15 @@ module mqnic_core_pcie_us # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_LEN_WIDTH = 16, parameter DMA_TAG_WIDTH = 16, @@ -139,6 +148,10 @@ module mqnic_core_pcie_us # parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8), parameter AXIL_CSR_PASSTHROUGH_ENABLE = 0, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512, parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, @@ -696,6 +709,15 @@ mqnic_core_pcie #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // Application block configuration + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + // DMA interface configuration .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), @@ -731,6 +753,10 @@ mqnic_core_pcie #( .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .AXIL_CSR_PASSTHROUGH_ENABLE(AXIL_CSR_PASSTHROUGH_ENABLE), + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + // Ethernet interface configuration .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), diff --git a/fpga/common/tb/mqnic.py b/fpga/common/tb/mqnic.py index 1e1dc3500..f12b4fb29 100644 --- a/fpga/common/tb/mqnic.py +++ b/fpga/common/tb/mqnic.py @@ -1044,6 +1044,8 @@ class Driver(object): self.dev_id = None self.rc_tree_ent = None self.hw_addr = None + self.app_hw_addr = None + self.ram_hw_addr = None self.fw_id = None self.fw_ver = None @@ -1073,6 +1075,17 @@ class Driver(object): self.dev_id = dev_id self.rc_tree_ent = self.rc.tree.find_child_dev(dev_id) self.hw_addr = self.rc_tree_ent.bar_addr[0] + self.hw_regs_size = self.rc_tree_ent.bar_size[0] + self.app_hw_addr = self.rc_tree_ent.bar_addr[2] + self.app_hw_regs_size = self.rc_tree_ent.bar_size[2] + self.ram_hw_addr = self.rc_tree_ent.bar_addr[4] + self.ram_hw_regs_size = self.rc_tree_ent.bar_size[4] + + self.log.info("Control BAR size: %d", self.hw_regs_size) + if self.app_hw_regs_size: + self.log.info("Application BAR size: %d", self.app_hw_regs_size) + if self.ram_hw_regs_size: + self.log.info("RAM BAR size: %d", self.ram_hw_regs_size) # Read ID registers self.fw_id = await self.rc.mem_read_dword(self.hw_addr+MQNIC_REG_FW_ID) diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index df22aa1f8..d0d52ad15 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -50,6 +50,7 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v VERILOG_SOURCES += ../../rtl/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/tx_engine.v @@ -57,15 +58,14 @@ VERILOG_SOURCES += ../../rtl/rx_engine.v VERILOG_SOURCES += ../../rtl/tx_checksum.v VERILOG_SOURCES += ../../rtl/rx_hash.v VERILOG_SOURCES += ../../rtl/rx_checksum.v -VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/stats_counter.v VERILOG_SOURCES += ../../rtl/stats_collect.v VERILOG_SOURCES += ../../rtl/stats_pcie_if.v VERILOG_SOURCES += ../../rtl/stats_pcie_tlp.v VERILOG_SOURCES += ../../rtl/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v @@ -89,6 +89,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v @@ -163,6 +166,15 @@ export PARAM_MAX_RX_SIZE ?= 9214 export PARAM_TX_RAM_SIZE ?= 131072 export PARAM_RX_RAM_SIZE ?= 131072 +# Application block configuration +export PARAM_APP_ENABLE ?= 0 +export PARAM_APP_CTRL_ENABLE ?= 1 +export PARAM_APP_DMA_ENABLE ?= 1 +export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1 +export PARAM_APP_AXIS_SYNC_ENABLE ?= 1 +export PARAM_APP_AXIS_IF_ENABLE ?= 1 +export PARAM_APP_STAT_ENABLE ?= 1 + # DMA interface configuration export PARAM_DMA_LEN_WIDTH ?= 16 export PARAM_DMA_TAG_WIDTH ?= 16 @@ -186,6 +198,10 @@ export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CSR_PASSTHROUGH_ENABLE ?= 0 +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24 + # Ethernet interface configuration export PARAM_AXIS_ETH_DATA_WIDTH ?= 512 export PARAM_AXIS_ETH_SYNC_DATA_WIDTH ?= $(PARAM_AXIS_ETH_DATA_WIDTH) @@ -243,6 +259,13 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) @@ -260,6 +283,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_DATA_WIDTH=$(PARAM_AXIS_ETH_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_SYNC_DATA_WIDTH=$(PARAM_AXIS_ETH_SYNC_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_USE_READY=$(PARAM_AXIS_ETH_RX_USE_READY) @@ -318,6 +343,13 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) @@ -335,6 +367,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) + COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIS_ETH_DATA_WIDTH=$(PARAM_AXIS_ETH_DATA_WIDTH) COMPILE_ARGS += -GAXIS_ETH_SYNC_DATA_WIDTH=$(PARAM_AXIS_ETH_SYNC_DATA_WIDTH) COMPILE_ARGS += -GAXIS_ETH_RX_USE_READY=$(PARAM_AXIS_ETH_RX_USE_READY) diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 2011d6b9a..62a19ff05 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -266,6 +266,8 @@ class TB(object): self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) # Ethernet self.port_mac = [] @@ -297,14 +299,14 @@ class TB(object): mac = EthMac( tx_clk=port.tx_async_fifo_inst.m_clk, tx_rst=port.tx_async_fifo_inst.m_rst, - tx_bus=AxiStreamBus.from_prefix(port.tx_async_fifo_inst, "m_axis"), + tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"), tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts, - tx_ptp_ts=port.ptp.tx_ptp_ts_fifo_inst.s_axis_tdata, - tx_ptp_ts_tag=port.ptp.tx_ptp_ts_fifo_inst.s_axis_tid, - tx_ptp_ts_valid=port.ptp.tx_ptp_ts_fifo_inst.s_axis_tvalid, + tx_ptp_ts=port.ptp.axis_tx_ptp_ts, + tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag, + tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid, rx_clk=port.rx_async_fifo_inst.s_clk, rx_rst=port.rx_async_fifo_inst.s_rst, - rx_bus=AxiStreamBus.from_prefix(port.rx_async_fifo_inst, "s_axis"), + rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"), rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts, ifg=12, speed=speed ) @@ -528,6 +530,7 @@ def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width, os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), os.path.join(rtl_dir, "desc_op_mux.v"), + os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), os.path.join(rtl_dir, "tx_engine.v"), @@ -535,15 +538,14 @@ def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width, os.path.join(rtl_dir, "tx_checksum.v"), os.path.join(rtl_dir, "rx_hash.v"), os.path.join(rtl_dir, "rx_checksum.v"), - os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "stats_counter.v"), os.path.join(rtl_dir, "stats_collect.v"), os.path.join(rtl_dir, "stats_pcie_if.v"), os.path.join(rtl_dir, "stats_pcie_tlp.v"), os.path.join(rtl_dir, "stats_dma_if_pcie.v"), os.path.join(rtl_dir, "stats_dma_latency.v"), + os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "tx_scheduler_rr.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), @@ -566,12 +568,10 @@ def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width, os.path.join(axis_rtl_dir, "axis_fifo.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), @@ -584,6 +584,11 @@ def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width, os.path.join(pcie_rtl_dir, "dma_psdpram.v"), os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_msi.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"), @@ -642,6 +647,15 @@ def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width, parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # Application block configuration + parameters['APP_ENABLE'] = 0 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + # DMA interface configuration parameters['DMA_LEN_WIDTH'] = 16 parameters['DMA_TAG_WIDTH'] = 16 @@ -665,6 +679,10 @@ def test_mqnic_core_pcie_us(request, axis_pcie_data_width, axis_eth_data_width, parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CSR_PASSTHROUGH_ENABLE'] = 0 + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + # Ethernet interface configuration parameters['AXIS_ETH_DATA_WIDTH'] = axis_eth_data_width parameters['AXIS_ETH_SYNC_DATA_WIDTH'] = axis_eth_sync_data_width diff --git a/fpga/mqnic/fb2CG/fpga_100g/app b/fpga/mqnic/fb2CG/fpga_100g/app new file mode 120000 index 000000000..4d46690fb --- /dev/null +++ b/fpga/mqnic/fb2CG/fpga_100g/app @@ -0,0 +1 @@ +../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index 66e5438dc..229f65831 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -22,6 +22,7 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_engine.v @@ -29,15 +30,14 @@ SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v SYN_FILES += rtl/common/rx_hash.v SYN_FILES += rtl/common/rx_checksum.v -SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v -SYN_FILES += rtl/common/tx_scheduler_rr.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/stats_counter.v SYN_FILES += rtl/common/stats_collect.v SYN_FILES += rtl/common/stats_pcie_if.v SYN_FILES += rtl/common/stats_pcie_tlp.v SYN_FILES += rtl/common/stats_dma_if_pcie.v SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += lib/eth/rtl/ptp_clock.v SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v @@ -63,12 +63,10 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v -SYN_FILES += lib/pcie/rtl/pcie_us_if.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v @@ -81,6 +79,11 @@ SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v SYN_FILES += lib/pcie/rtl/dma_psdpram.v SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_msi.v SYN_FILES += lib/pcie/rtl/pulse_merge.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl index 39ca162d9..34baa17de 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl @@ -93,6 +93,15 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" +# Application block configuration +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + # DMA interface configuration dict set params DMA_LEN_WIDTH "16" dict set params DMA_TAG_WIDTH "16" @@ -111,6 +120,10 @@ dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_ADDR_WIDTH "24" +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + # Ethernet interface configuration dict set params AXIS_ETH_TX_PIPELINE "0" dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" @@ -173,6 +186,9 @@ proc configure_bar {pcie pf bar aperture} { # Control BAR (BAR 0) configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index a150759ee..3ad327362 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -97,6 +97,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_LEN_WIDTH = 16, parameter DMA_TAG_WIDTH = 16, @@ -124,6 +133,10 @@ module fpga # parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_ADDR_WIDTH = 24, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + // Ethernet interface configuration parameter AXIS_ETH_TX_PIPELINE = 0, parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, @@ -1702,6 +1715,15 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // Application block configuration + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + // DMA interface configuration .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), @@ -1730,6 +1752,10 @@ fpga_core #( .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + // Ethernet interface configuration .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 2df3bb60f..2e5245c6e 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -105,6 +105,15 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_LEN_WIDTH = 16, parameter DMA_TAG_WIDTH = 16, @@ -133,6 +142,10 @@ module fpga_core # parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_ADDR_WIDTH = 24, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512, parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, @@ -826,6 +839,15 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // Application block configuration + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + // DMA interface configuration .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), @@ -859,6 +881,10 @@ mqnic_core_pcie_us #( .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .AXIL_CSR_PASSTHROUGH_ENABLE(0), + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + // Ethernet interface configuration .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index d5f22871f..73612aa35 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -52,6 +52,7 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v @@ -59,15 +60,14 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v VERILOG_SOURCES += ../../rtl/common/rx_hash.v VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/stats_counter.v VERILOG_SOURCES += ../../rtl/common/stats_collect.v VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v @@ -91,12 +91,10 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v @@ -109,6 +107,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v @@ -165,6 +168,15 @@ export PARAM_MAX_RX_SIZE ?= 9214 export PARAM_TX_RAM_SIZE ?= 131072 export PARAM_RX_RAM_SIZE ?= 131072 +# Application block configuration +export PARAM_APP_ENABLE ?= 0 +export PARAM_APP_CTRL_ENABLE ?= 1 +export PARAM_APP_DMA_ENABLE ?= 1 +export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1 +export PARAM_APP_AXIS_SYNC_ENABLE ?= 1 +export PARAM_APP_AXIS_IF_ENABLE ?= 1 +export PARAM_APP_STAT_ENABLE ?= 1 + # DMA interface configuration export PARAM_DMA_LEN_WIDTH ?= 16 export PARAM_DMA_TAG_WIDTH ?= 16 @@ -186,6 +198,10 @@ export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24 + # Ethernet interface configuration export PARAM_AXIS_ETH_TX_PIPELINE ?= 0 export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2 @@ -239,6 +255,13 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) @@ -254,6 +277,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) @@ -308,6 +333,13 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) @@ -323,6 +355,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index d85812bb1..85e58347f 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -265,6 +265,8 @@ class TB(object): self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) # Ethernet cocotb.fork(Clock(dut.qsfp_0_rx_clk, 3.102, units="ns").start()) @@ -505,6 +507,7 @@ async def run_test_nic(dut): tests_dir = os.path.dirname(__file__) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) @@ -531,6 +534,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), + os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), @@ -538,15 +542,14 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "tx_checksum.v"), os.path.join(rtl_dir, "common", "rx_hash.v"), os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "stats_counter.v"), os.path.join(rtl_dir, "common", "stats_collect.v"), os.path.join(rtl_dir, "common", "stats_pcie_if.v"), os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), os.path.join(rtl_dir, "common", "stats_dma_latency.v"), + os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), @@ -570,12 +573,10 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_fifo.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), @@ -588,6 +589,11 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "dma_psdpram.v"), os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_msi.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"), @@ -645,6 +651,15 @@ def test_fpga_core(request): parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # Application block configuration + parameters['APP_ENABLE'] = 0 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + # DMA interface configuration parameters['DMA_LEN_WIDTH'] = 16 parameters['DMA_TAG_WIDTH'] = 16 @@ -666,6 +681,10 @@ def test_fpga_core(request): parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + # Ethernet interface configuration parameters['AXIS_ETH_TX_PIPELINE'] = 0 parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 diff --git a/fpga/mqnic/fb2CG/fpga_10g/app b/fpga/mqnic/fb2CG/fpga_10g/app new file mode 120000 index 000000000..4d46690fb --- /dev/null +++ b/fpga/mqnic/fb2CG/fpga_10g/app @@ -0,0 +1 @@ +../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile index 3b2007e97..6ed5b8c9a 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile @@ -22,6 +22,7 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_engine.v @@ -29,15 +30,14 @@ SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v SYN_FILES += rtl/common/rx_hash.v SYN_FILES += rtl/common/rx_checksum.v -SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v -SYN_FILES += rtl/common/tx_scheduler_rr.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/stats_counter.v SYN_FILES += rtl/common/stats_collect.v SYN_FILES += rtl/common/stats_pcie_if.v SYN_FILES += rtl/common/stats_pcie_tlp.v SYN_FILES += rtl/common/stats_dma_if_pcie.v SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber_ch.v @@ -79,12 +79,10 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v -SYN_FILES += lib/pcie/rtl/pcie_us_if.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v @@ -97,6 +95,11 @@ SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v SYN_FILES += lib/pcie/rtl/dma_psdpram.v SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_msi.v SYN_FILES += lib/pcie/rtl/pulse_merge.v diff --git a/fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl index db95ea987..f7f32f980 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_10g/fpga/config.tcl @@ -110,6 +110,15 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" +# Application block configuration +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + # DMA interface configuration dict set params DMA_LEN_WIDTH "16" dict set params DMA_TAG_WIDTH "16" @@ -128,6 +137,10 @@ dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_ADDR_WIDTH "24" +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + # Ethernet interface configuration dict set params AXIS_ETH_TX_PIPELINE "0" dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" @@ -190,6 +203,9 @@ proc configure_bar {pcie pf bar aperture} { # Control BAR (BAR 0) configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v index 9ce85fe92..0a08e01b9 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v @@ -97,6 +97,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_LEN_WIDTH = 16, parameter DMA_TAG_WIDTH = 16, @@ -124,6 +133,10 @@ module fpga # parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_ADDR_WIDTH = 24, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + // Ethernet interface configuration parameter AXIS_ETH_TX_PIPELINE = 0, parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, @@ -1622,6 +1635,15 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // Application block configuration + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + // DMA interface configuration .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), @@ -1650,6 +1672,10 @@ fpga_core #( .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + // Ethernet interface configuration .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v index 0c54d09f9..8c11bb810 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v @@ -110,6 +110,15 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_LEN_WIDTH = 16, parameter DMA_TAG_WIDTH = 16, @@ -138,6 +147,10 @@ module fpga_core # parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_ADDR_WIDTH = 24, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64, parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, @@ -1084,6 +1097,15 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // Application block configuration + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + // DMA interface configuration .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), @@ -1117,6 +1139,10 @@ mqnic_core_pcie_us #( .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .AXIL_CSR_PASSTHROUGH_ENABLE(1), + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + // Ethernet interface configuration .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile index 9ee11c014..33764dc1a 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile @@ -52,6 +52,7 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v @@ -59,15 +60,14 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v VERILOG_SOURCES += ../../rtl/common/rx_hash.v VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/stats_counter.v VERILOG_SOURCES += ../../rtl/common/stats_collect.v VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v VERILOG_SOURCES += ../../rtl/common/tdma_ber.v VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v @@ -98,12 +98,10 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v @@ -116,6 +114,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v @@ -172,6 +175,15 @@ export PARAM_MAX_RX_SIZE ?= 9214 export PARAM_TX_RAM_SIZE ?= 32768 export PARAM_RX_RAM_SIZE ?= 32768 +# Application block configuration +export PARAM_APP_ENABLE ?= 0 +export PARAM_APP_CTRL_ENABLE ?= 1 +export PARAM_APP_DMA_ENABLE ?= 1 +export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1 +export PARAM_APP_AXIS_SYNC_ENABLE ?= 1 +export PARAM_APP_AXIS_IF_ENABLE ?= 1 +export PARAM_APP_STAT_ENABLE ?= 1 + # DMA interface configuration export PARAM_DMA_LEN_WIDTH ?= 16 export PARAM_DMA_TAG_WIDTH ?= 16 @@ -193,6 +205,10 @@ export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24 + # Ethernet interface configuration export PARAM_AXIS_ETH_TX_PIPELINE ?= 0 export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2 @@ -246,6 +262,13 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) @@ -261,6 +284,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) @@ -315,6 +340,13 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) @@ -330,6 +362,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) diff --git a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py index 1a3974ca5..4596cea1f 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -265,6 +265,8 @@ class TB(object): self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) # Ethernet cocotb.fork(Clock(dut.qsfp_0_rx_clk_0, 6.4, units="ns").start()) @@ -547,6 +549,7 @@ async def run_test_nic(dut): tests_dir = os.path.dirname(__file__) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) @@ -573,6 +576,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), + os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), @@ -580,15 +584,14 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "tx_checksum.v"), os.path.join(rtl_dir, "common", "rx_hash.v"), os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "stats_counter.v"), os.path.join(rtl_dir, "common", "stats_collect.v"), os.path.join(rtl_dir, "common", "stats_pcie_if.v"), os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), os.path.join(rtl_dir, "common", "stats_dma_latency.v"), + os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), os.path.join(rtl_dir, "common", "tdma_scheduler.v"), os.path.join(rtl_dir, "common", "tdma_ber.v"), os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), @@ -619,12 +622,10 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_fifo.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), @@ -637,6 +638,11 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "dma_psdpram.v"), os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_msi.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"), @@ -694,6 +700,15 @@ def test_fpga_core(request): parameters['TX_RAM_SIZE'] = 32768 parameters['RX_RAM_SIZE'] = 32768 + # Application block configuration + parameters['APP_ENABLE'] = 0 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + # DMA interface configuration parameters['DMA_LEN_WIDTH'] = 16 parameters['DMA_TAG_WIDTH'] = 16 @@ -715,6 +730,10 @@ def test_fpga_core(request): parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + # Ethernet interface configuration parameters['AXIS_ETH_TX_PIPELINE'] = 0 parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 diff --git a/fpga/mqnic/fb2CG/fpga_25g/app b/fpga/mqnic/fb2CG/fpga_25g/app new file mode 120000 index 000000000..4d46690fb --- /dev/null +++ b/fpga/mqnic/fb2CG/fpga_25g/app @@ -0,0 +1 @@ +../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index 3b2007e97..6ed5b8c9a 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -22,6 +22,7 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_engine.v @@ -29,15 +30,14 @@ SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v SYN_FILES += rtl/common/rx_hash.v SYN_FILES += rtl/common/rx_checksum.v -SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v -SYN_FILES += rtl/common/tx_scheduler_rr.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/stats_counter.v SYN_FILES += rtl/common/stats_collect.v SYN_FILES += rtl/common/stats_pcie_if.v SYN_FILES += rtl/common/stats_pcie_tlp.v SYN_FILES += rtl/common/stats_dma_if_pcie.v SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber_ch.v @@ -79,12 +79,10 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v -SYN_FILES += lib/pcie/rtl/pcie_us_if.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v -SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v @@ -97,6 +95,11 @@ SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v SYN_FILES += lib/pcie/rtl/dma_psdpram.v SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_msi.v SYN_FILES += lib/pcie/rtl/pulse_merge.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index db95ea987..f7f32f980 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -110,6 +110,15 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" +# Application block configuration +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + # DMA interface configuration dict set params DMA_LEN_WIDTH "16" dict set params DMA_TAG_WIDTH "16" @@ -128,6 +137,10 @@ dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_ADDR_WIDTH "24" +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + # Ethernet interface configuration dict set params AXIS_ETH_TX_PIPELINE "0" dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" @@ -190,6 +203,9 @@ proc configure_bar {pcie pf bar aperture} { # Control BAR (BAR 0) configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index 9ce7bdbad..da226eb72 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -97,6 +97,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_LEN_WIDTH = 16, parameter DMA_TAG_WIDTH = 16, @@ -124,6 +133,10 @@ module fpga # parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_ADDR_WIDTH = 24, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + // Ethernet interface configuration parameter AXIS_ETH_TX_PIPELINE = 0, parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, @@ -1638,6 +1651,15 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // Application block configuration + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + // DMA interface configuration .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), @@ -1666,6 +1688,10 @@ fpga_core #( .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + // Ethernet interface configuration .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index eadfffb63..a75af8f50 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -110,6 +110,15 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // Application block configuration + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + // DMA interface configuration parameter DMA_LEN_WIDTH = 16, parameter DMA_TAG_WIDTH = 16, @@ -138,6 +147,10 @@ module fpga_core # parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_ADDR_WIDTH = 24, + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64, parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, @@ -1084,6 +1097,15 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // Application block configuration + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + // DMA interface configuration .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), @@ -1117,6 +1139,10 @@ mqnic_core_pcie_us #( .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), .AXIL_CSR_PASSTHROUGH_ENABLE(1), + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + // Ethernet interface configuration .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index 9ee11c014..33764dc1a 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -52,6 +52,7 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v @@ -59,15 +60,14 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v VERILOG_SOURCES += ../../rtl/common/rx_hash.v VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/stats_counter.v VERILOG_SOURCES += ../../rtl/common/stats_collect.v VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v VERILOG_SOURCES += ../../rtl/common/tdma_ber.v VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v @@ -98,12 +98,10 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v @@ -116,6 +114,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v @@ -172,6 +175,15 @@ export PARAM_MAX_RX_SIZE ?= 9214 export PARAM_TX_RAM_SIZE ?= 32768 export PARAM_RX_RAM_SIZE ?= 32768 +# Application block configuration +export PARAM_APP_ENABLE ?= 0 +export PARAM_APP_CTRL_ENABLE ?= 1 +export PARAM_APP_DMA_ENABLE ?= 1 +export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1 +export PARAM_APP_AXIS_SYNC_ENABLE ?= 1 +export PARAM_APP_AXIS_IF_ENABLE ?= 1 +export PARAM_APP_STAT_ENABLE ?= 1 + # DMA interface configuration export PARAM_DMA_LEN_WIDTH ?= 16 export PARAM_DMA_TAG_WIDTH ?= 16 @@ -193,6 +205,10 @@ export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24 + # Ethernet interface configuration export PARAM_AXIS_ETH_TX_PIPELINE ?= 0 export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2 @@ -246,6 +262,13 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) @@ -261,6 +284,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) @@ -315,6 +340,13 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) @@ -330,6 +362,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 40142e1cc..8d284e01d 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -265,6 +265,8 @@ class TB(object): self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) # Ethernet cocotb.fork(Clock(dut.qsfp_0_rx_clk_0, 2.56, units="ns").start()) @@ -547,6 +549,7 @@ async def run_test_nic(dut): tests_dir = os.path.dirname(__file__) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) @@ -573,6 +576,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), + os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), @@ -580,15 +584,14 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "tx_checksum.v"), os.path.join(rtl_dir, "common", "rx_hash.v"), os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "stats_counter.v"), os.path.join(rtl_dir, "common", "stats_collect.v"), os.path.join(rtl_dir, "common", "stats_pcie_if.v"), os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), os.path.join(rtl_dir, "common", "stats_dma_latency.v"), + os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), os.path.join(rtl_dir, "common", "tdma_scheduler.v"), os.path.join(rtl_dir, "common", "tdma_ber.v"), os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), @@ -619,12 +622,10 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_fifo.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), @@ -637,6 +638,11 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "dma_psdpram.v"), os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_msi.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"), @@ -694,6 +700,15 @@ def test_fpga_core(request): parameters['TX_RAM_SIZE'] = 32768 parameters['RX_RAM_SIZE'] = 32768 + # Application block configuration + parameters['APP_ENABLE'] = 0 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + # DMA interface configuration parameters['DMA_LEN_WIDTH'] = 16 parameters['DMA_TAG_WIDTH'] = 16 @@ -715,6 +730,10 @@ def test_fpga_core(request): parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + # Ethernet interface configuration parameters['AXIS_ETH_TX_PIPELINE'] = 0 parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 diff --git a/tox.ini b/tox.ini index 69e3b5a0a..c92d58d79 100644 --- a/tox.ini +++ b/tox.ini @@ -28,6 +28,7 @@ testpaths = fpga/common/tb fpga/mqnic fpga/mqnic_tdma + fpga/app addopts = --ignore-glob=*lib* --import-mode=importlib