diff --git a/rtl/arbiter.v b/rtl/arbiter.v index cd55dd3dc..cfac70d1c 100644 --- a/rtl/arbiter.v +++ b/rtl/arbiter.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Arbiter module @@ -153,3 +155,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_adapter.v b/rtl/axi_adapter.v index e945f3699..5f67c218f 100644 --- a/rtl/axi_adapter.v +++ b/rtl/axi_adapter.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 width adapter @@ -318,3 +320,5 @@ axi_adapter_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axi_adapter_rd.v b/rtl/axi_adapter_rd.v index 05e1d1e6a..4290861f1 100644 --- a/rtl/axi_adapter_rd.v +++ b/rtl/axi_adapter_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 width adapter @@ -690,3 +692,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_adapter_wr.v b/rtl/axi_adapter_wr.v index f71fa211e..214a9a428 100644 --- a/rtl/axi_adapter_wr.v +++ b/rtl/axi_adapter_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 width adapter @@ -781,3 +783,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_axil_adapter.v b/rtl/axi_axil_adapter.v index 184c5d77e..4593ea31b 100644 --- a/rtl/axi_axil_adapter.v +++ b/rtl/axi_axil_adapter.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 to AXI4-Lite adapter @@ -217,3 +219,5 @@ axi_axil_adapter_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axi_axil_adapter_rd.v b/rtl/axi_axil_adapter_rd.v index 0b48fdb8a..9e029fbfe 100644 --- a/rtl/axi_axil_adapter_rd.v +++ b/rtl/axi_axil_adapter_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 to AXI4-Lite adapter (read) @@ -504,3 +506,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_axil_adapter_wr.v b/rtl/axi_axil_adapter_wr.v index 5293f61b4..fc653651f 100644 --- a/rtl/axi_axil_adapter_wr.v +++ b/rtl/axi_axil_adapter_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 to AXI4-Lite adapter (write) @@ -558,3 +560,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_cdma.v b/rtl/axi_cdma.v index 06dad0fa2..54b8e8748 100644 --- a/rtl/axi_cdma.v +++ b/rtl/axi_cdma.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 Central DMA @@ -792,3 +794,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_cdma_desc_mux.v b/rtl/axi_cdma_desc_mux.v index 9aa3ddc6f..3f7ce35cf 100644 --- a/rtl/axi_cdma_desc_mux.v +++ b/rtl/axi_cdma_desc_mux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI CDMA descriptor mux @@ -259,3 +261,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_crossbar.v b/rtl/axi_crossbar.v index 04af41636..991d45403 100644 --- a/rtl/axi_crossbar.v +++ b/rtl/axi_crossbar.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 crossbar @@ -385,3 +387,5 @@ axi_crossbar_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axi_crossbar_addr.v b/rtl/axi_crossbar_addr.v index 2286b2fdb..7b7846526 100644 --- a/rtl/axi_crossbar_addr.v +++ b/rtl/axi_crossbar_addr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 crossbar address decode and admission control @@ -412,3 +414,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_crossbar_rd.v b/rtl/axi_crossbar_rd.v index 50055e977..2b1410ac6 100644 --- a/rtl/axi_crossbar_rd.v +++ b/rtl/axi_crossbar_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 crossbar (read) @@ -563,3 +565,5 @@ generate endgenerate endmodule + +`resetall diff --git a/rtl/axi_crossbar_wr.v b/rtl/axi_crossbar_wr.v index 4b0641a4b..5f5566535 100644 --- a/rtl/axi_crossbar_wr.v +++ b/rtl/axi_crossbar_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 crossbar (write) @@ -672,3 +674,5 @@ generate endgenerate endmodule + +`resetall diff --git a/rtl/axi_crossbar_wrap.py b/rtl/axi_crossbar_wrap.py index 466ad369d..9d554146b 100755 --- a/rtl/axi_crossbar_wrap.py +++ b/rtl/axi_crossbar_wrap.py @@ -67,7 +67,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 {{m}}x{{n}} crossbar (wrapper) @@ -427,6 +429,8 @@ axi_crossbar_inst ( endmodule +`resetall + """) print(f"Writing file '{output}'...") diff --git a/rtl/axi_dma.v b/rtl/axi_dma.v index 5e82d7711..b677cba79 100644 --- a/rtl/axi_dma.v +++ b/rtl/axi_dma.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 DMA @@ -355,3 +357,5 @@ axi_dma_wr_inst ( ); endmodule + +`resetall diff --git a/rtl/axi_dma_desc_mux.v b/rtl/axi_dma_desc_mux.v index 662f6b708..8cf229814 100644 --- a/rtl/axi_dma_desc_mux.v +++ b/rtl/axi_dma_desc_mux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI DMA descriptor mux @@ -313,3 +315,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_dma_rd.v b/rtl/axi_dma_rd.v index 57f05439f..710006d05 100644 --- a/rtl/axi_dma_rd.v +++ b/rtl/axi_dma_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 DMA @@ -686,3 +688,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_dma_wr.v b/rtl/axi_dma_wr.v index 55be3812f..119199a22 100644 --- a/rtl/axi_dma_wr.v +++ b/rtl/axi_dma_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 DMA @@ -936,3 +938,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_dp_ram.v b/rtl/axi_dp_ram.v index 2fb96ca29..25368149f 100644 --- a/rtl/axi_dp_ram.v +++ b/rtl/axi_dp_ram.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 dual port RAM @@ -420,3 +422,5 @@ always @(posedge b_clk) begin end endmodule + +`resetall diff --git a/rtl/axi_fifo.v b/rtl/axi_fifo.v index 0e18f5fb6..2170efbbf 100644 --- a/rtl/axi_fifo.v +++ b/rtl/axi_fifo.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 FIFO @@ -310,3 +312,5 @@ axi_fifo_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axi_fifo_rd.v b/rtl/axi_fifo_rd.v index 642d5c082..fe3bad3b2 100644 --- a/rtl/axi_fifo_rd.v +++ b/rtl/axi_fifo_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 FIFO (read) @@ -406,3 +408,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_fifo_wr.v b/rtl/axi_fifo_wr.v index 4cb34c5e5..8a4ff8418 100644 --- a/rtl/axi_fifo_wr.v +++ b/rtl/axi_fifo_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 FIFO (write) @@ -446,3 +448,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_interconnect.v b/rtl/axi_interconnect.v index 1635df738..14256ad7d 100644 --- a/rtl/axi_interconnect.v +++ b/rtl/axi_interconnect.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 interconnect @@ -982,3 +984,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_interconnect_wrap.py b/rtl/axi_interconnect_wrap.py index 1409566a3..874f5a4d6 100755 --- a/rtl/axi_interconnect_wrap.py +++ b/rtl/axi_interconnect_wrap.py @@ -67,7 +67,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 {{m}}x{{n}} interconnect (wrapper) @@ -338,6 +340,8 @@ axi_interconnect_inst ( endmodule +`resetall + """) print(f"Writing file '{output}'...") diff --git a/rtl/axi_ram.v b/rtl/axi_ram.v index 408ebea5b..7eea20315 100644 --- a/rtl/axi_ram.v +++ b/rtl/axi_ram.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 RAM @@ -367,3 +369,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_ram_rd_if.v b/rtl/axi_ram_rd_if.v index 83015f071..8238894a7 100644 --- a/rtl/axi_ram_rd_if.v +++ b/rtl/axi_ram_rd_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 RAM read interface @@ -268,3 +270,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_ram_wr_if.v b/rtl/axi_ram_wr_if.v index 6d97810c4..f0797760a 100644 --- a/rtl/axi_ram_wr_if.v +++ b/rtl/axi_ram_wr_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 RAM write interface @@ -286,3 +288,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_ram_wr_rd_if.v b/rtl/axi_ram_wr_rd_if.v index 947e69695..3e0b34186 100644 --- a/rtl/axi_ram_wr_rd_if.v +++ b/rtl/axi_ram_wr_rd_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 RAM read/write interface @@ -337,3 +339,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axi_register.v b/rtl/axi_register.v index 040e5af41..b831c8b62 100644 --- a/rtl/axi_register.v +++ b/rtl/axi_register.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 register @@ -318,3 +320,5 @@ axi_register_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axi_register_rd.v b/rtl/axi_register_rd.v index 56648b4eb..c0df03a03 100644 --- a/rtl/axi_register_rd.v +++ b/rtl/axi_register_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 register (read) @@ -524,3 +526,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/axi_register_wr.v b/rtl/axi_register_wr.v index 4d83a0abf..9176d6ba9 100644 --- a/rtl/axi_register_wr.v +++ b/rtl/axi_register_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 register (write) @@ -685,3 +687,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/axil_adapter.v b/rtl/axil_adapter.v index c77a6a307..c71b54e8a 100644 --- a/rtl/axil_adapter.v +++ b/rtl/axil_adapter.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite width adapter @@ -172,3 +174,5 @@ axil_adapter_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axil_adapter_rd.v b/rtl/axil_adapter_rd.v index 8bb5a8a85..d36baec1e 100644 --- a/rtl/axil_adapter_rd.v +++ b/rtl/axil_adapter_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite width adapter (read) @@ -269,3 +271,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axil_adapter_wr.v b/rtl/axil_adapter_wr.v index f73ab7093..54871dc0d 100644 --- a/rtl/axil_adapter_wr.v +++ b/rtl/axil_adapter_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite width adapter (write) @@ -331,3 +333,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axil_cdc.v b/rtl/axil_cdc.v index f719d6c5f..21fce462a 100644 --- a/rtl/axil_cdc.v +++ b/rtl/axil_cdc.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite clock domain crossing module @@ -167,3 +169,5 @@ axil_cdc_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axil_cdc_rd.v b/rtl/axil_cdc_rd.v index a34aff281..8b13702b1 100644 --- a/rtl/axil_cdc_rd.v +++ b/rtl/axil_cdc_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite clock domain crossing module (read) @@ -202,3 +204,5 @@ always @(posedge m_clk) begin end endmodule + +`resetall diff --git a/rtl/axil_cdc_wr.v b/rtl/axil_cdc_wr.v index 4107d6ee2..dd3f11f74 100644 --- a/rtl/axil_cdc_wr.v +++ b/rtl/axil_cdc_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite clock domain crossing module (write) @@ -226,3 +228,5 @@ always @(posedge m_clk) begin end endmodule + +`resetall diff --git a/rtl/axil_crossbar.v b/rtl/axil_crossbar.v index 0340a2edf..5167037f0 100644 --- a/rtl/axil_crossbar.v +++ b/rtl/axil_crossbar.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite crossbar @@ -245,3 +247,5 @@ axil_crossbar_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axil_crossbar_addr.v b/rtl/axil_crossbar_addr.v index 15334dcb9..dc07e98e7 100644 --- a/rtl/axil_crossbar_addr.v +++ b/rtl/axil_crossbar_addr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite crossbar address decode and admission control @@ -303,3 +305,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axil_crossbar_rd.v b/rtl/axil_crossbar_rd.v index 35989b176..b7d93cf24 100644 --- a/rtl/axil_crossbar_rd.v +++ b/rtl/axil_crossbar_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite crossbar (read) @@ -419,3 +421,5 @@ generate endgenerate endmodule + +`resetall diff --git a/rtl/axil_crossbar_wr.v b/rtl/axil_crossbar_wr.v index 56ccf3704..d7f8a8dc6 100644 --- a/rtl/axil_crossbar_wr.v +++ b/rtl/axil_crossbar_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite crossbar (write) @@ -527,3 +529,5 @@ generate endgenerate endmodule + +`resetall diff --git a/rtl/axil_crossbar_wrap.py b/rtl/axil_crossbar_wrap.py index be54eea80..cc883a437 100755 --- a/rtl/axil_crossbar_wrap.py +++ b/rtl/axil_crossbar_wrap.py @@ -67,7 +67,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite {{m}}x{{n}} crossbar (wrapper) @@ -291,6 +293,8 @@ axil_crossbar_inst ( endmodule +`resetall + """) print(f"Writing file '{output}'...") diff --git a/rtl/axil_dp_ram.v b/rtl/axil_dp_ram.v index 3a6d789b0..926e6747c 100644 --- a/rtl/axil_dp_ram.v +++ b/rtl/axil_dp_ram.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Lite dual port RAM @@ -309,3 +311,5 @@ always @(posedge b_clk) begin end endmodule + +`resetall diff --git a/rtl/axil_interconnect.v b/rtl/axil_interconnect.v index b474ab8d8..fb9d9bfc2 100644 --- a/rtl/axil_interconnect.v +++ b/rtl/axil_interconnect.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite interconnect @@ -558,3 +560,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axil_interconnect_wrap.py b/rtl/axil_interconnect_wrap.py index a748d6046..1c94b9e9b 100755 --- a/rtl/axil_interconnect_wrap.py +++ b/rtl/axil_interconnect_wrap.py @@ -67,7 +67,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite {{m}}x{{n}} interconnect (wrapper) @@ -218,6 +220,8 @@ axil_interconnect_inst ( endmodule +`resetall + """) print(f"Writing file '{output}'...") diff --git a/rtl/axil_ram.v b/rtl/axil_ram.v index d0d27fd88..50fee2e50 100644 --- a/rtl/axil_ram.v +++ b/rtl/axil_ram.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Lite RAM @@ -177,3 +179,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axil_reg_if.v b/rtl/axil_reg_if.v index dd9cfc029..887638099 100644 --- a/rtl/axil_reg_if.v +++ b/rtl/axil_reg_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI lite register interface module @@ -152,3 +154,5 @@ axil_reg_if_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axil_reg_if_rd.v b/rtl/axil_reg_if_rd.v index a7e312ec2..89473c0f8 100644 --- a/rtl/axil_reg_if_rd.v +++ b/rtl/axil_reg_if_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI lite register interface module (read) @@ -130,3 +132,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axil_reg_if_wr.v b/rtl/axil_reg_if_wr.v index 55f9517c2..4ffc0672a 100644 --- a/rtl/axil_reg_if_wr.v +++ b/rtl/axil_reg_if_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI lite register interface module (write) @@ -149,3 +151,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axil_register.v b/rtl/axil_register.v index f94e737e3..38f6b2c4c 100644 --- a/rtl/axil_register.v +++ b/rtl/axil_register.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite register @@ -184,3 +186,5 @@ axil_register_rd_inst ( ); endmodule + +`resetall diff --git a/rtl/axil_register_rd.v b/rtl/axil_register_rd.v index 8f0bc088d..dc7d32782 100644 --- a/rtl/axil_register_rd.v +++ b/rtl/axil_register_rd.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite register (read) @@ -370,3 +372,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/axil_register_wr.v b/rtl/axil_register_wr.v index 4000d5d15..a13fa4e6c 100644 --- a/rtl/axil_register_wr.v +++ b/rtl/axil_register_wr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4 lite register (write) @@ -515,3 +517,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/priority_encoder.v b/rtl/priority_encoder.v index dd59fa455..cf82512ba 100644 --- a/rtl/priority_encoder.v +++ b/rtl/priority_encoder.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Priority encoder module @@ -86,3 +88,5 @@ assign output_encoded = stage_enc[LEVELS-1]; assign output_unencoded = 1 << output_encoded; endmodule + +`resetall