Add default_nettype none and resetall directives

rtl/arbiter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Arbiter module
@@ -153,3 +155,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 width adapter
@@ -318,3 +320,5 @@ axi_adapter_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axi_adapter_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 width adapter
@@ -690,3 +692,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_adapter_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 width adapter
@@ -781,3 +783,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_axil_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 to AXI4-Lite adapter
@@ -217,3 +219,5 @@ axi_axil_adapter_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axi_axil_adapter_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 to AXI4-Lite adapter (read)
@@ -504,3 +506,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_axil_adapter_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 to AXI4-Lite adapter (write)
@@ -558,3 +560,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_cdma.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 Central DMA
@@ -792,3 +794,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_cdma_desc_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI CDMA descriptor mux
@@ -259,3 +261,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_crossbar.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 crossbar
@@ -385,3 +387,5 @@ axi_crossbar_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axi_crossbar_addr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 crossbar address decode and admission control
@@ -412,3 +414,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_crossbar_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 crossbar (read)
@@ -563,3 +565,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall

rtl/axi_crossbar_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 crossbar (write)
@@ -672,3 +674,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall

rtl/axi_crossbar_wrap.py

@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 {{m}}x{{n}} crossbar (wrapper)
@@ -427,6 +429,8 @@ axi_crossbar_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

rtl/axi_dma.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 DMA
@@ -355,3 +357,5 @@ axi_dma_wr_inst (
 );
 
 endmodule
+
+`resetall

rtl/axi_dma_desc_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI DMA descriptor mux
@@ -313,3 +315,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_dma_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 DMA
@@ -686,3 +688,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_dma_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 DMA
@@ -936,3 +938,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_dp_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 dual port RAM
@@ -420,3 +422,5 @@ always @(posedge b_clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_fifo.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 FIFO
@@ -310,3 +312,5 @@ axi_fifo_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axi_fifo_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 FIFO (read)
@@ -406,3 +408,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_fifo_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 FIFO (write)
@@ -446,3 +448,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_interconnect.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 interconnect
@@ -982,3 +984,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_interconnect_wrap.py

@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 {{m}}x{{n}} interconnect (wrapper)
@@ -338,6 +340,8 @@ axi_interconnect_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

rtl/axi_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM
@@ -367,3 +369,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_ram_rd_if.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM read interface
@@ -268,3 +270,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_ram_wr_if.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM write interface
@@ -286,3 +288,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_ram_wr_rd_if.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 RAM read/write interface
@@ -337,3 +339,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 register
@@ -318,3 +320,5 @@ axi_register_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axi_register_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 register (read)
@@ -524,3 +526,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

rtl/axi_register_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 register (write)
@@ -685,3 +687,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

rtl/axil_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite width adapter
@@ -172,3 +174,5 @@ axil_adapter_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axil_adapter_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite width adapter (read)
@@ -269,3 +271,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_adapter_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite width adapter (write)
@@ -331,3 +333,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_cdc.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite clock domain crossing module
@@ -167,3 +169,5 @@ axil_cdc_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axil_cdc_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite clock domain crossing module (read)
@@ -202,3 +204,5 @@ always @(posedge m_clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_cdc_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite clock domain crossing module (write)
@@ -226,3 +228,5 @@ always @(posedge m_clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_crossbar.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite crossbar
@@ -245,3 +247,5 @@ axil_crossbar_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axil_crossbar_addr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite crossbar address decode and admission control
@@ -303,3 +305,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_crossbar_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite crossbar (read)
@@ -419,3 +421,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall

rtl/axil_crossbar_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite crossbar (write)
@@ -527,3 +529,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall

rtl/axil_crossbar_wrap.py

@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite {{m}}x{{n}} crossbar (wrapper)
@@ -291,6 +293,8 @@ axil_crossbar_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

rtl/axil_dp_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Lite dual port RAM
@@ -309,3 +311,5 @@ always @(posedge b_clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_interconnect.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite interconnect
@@ -558,3 +560,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_interconnect_wrap.py

@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite {{m}}x{{n}} interconnect (wrapper)
@@ -218,6 +220,8 @@ axil_interconnect_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

rtl/axil_ram.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Lite RAM
@@ -177,3 +179,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_reg_if.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI lite register interface module
@@ -152,3 +154,5 @@ axil_reg_if_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axil_reg_if_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI lite register interface module (read)
@@ -130,3 +132,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_reg_if_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI lite register interface module (write)
@@ -149,3 +151,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axil_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite register
@@ -184,3 +186,5 @@ axil_register_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axil_register_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite register (read)
@@ -370,3 +372,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

rtl/axil_register_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 lite register (write)
@@ -515,3 +517,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

rtl/priority_encoder.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Priority encoder module
@@ -86,3 +88,5 @@ assign output_encoded = stage_enc[LEVELS-1];
 assign output_unencoded = 1 << output_encoded;
 
 endmodule
+
+`resetall