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Convert generated eth_mux to verilog parametrized module
This commit is contained in:
Alex Forencich
parent
68abccd0a1
commit
d28d459d70
374
rtl/eth_mux.py
374
rtl/eth_mux.py
@ -1,374 +0,0 @@
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#!/usr/bin/env python
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"""
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Generates an Ethernet mux with the specified number of ports
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"""
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from __future__ import print_function
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import argparse
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import math
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from jinja2 import Template
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def main():
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parser = argparse.ArgumentParser(description=__doc__.strip())
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parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
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parser.add_argument('-n', '--name', type=str, help="module name")
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parser.add_argument('-o', '--output', type=str, help="output file name")
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args = parser.parse_args()
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try:
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generate(**args.__dict__)
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except IOError as ex:
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print(ex)
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exit(1)
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def generate(ports=4, name=None, output=None):
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if name is None:
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name = "eth_mux_{0}".format(ports)
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if output is None:
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output = name + ".v"
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print("Opening file '{0}'...".format(output))
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output_file = open(output, 'w')
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print("Generating {0} port Ethernet mux {1}...".format(ports, name))
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select_width = int(math.ceil(math.log(ports, 2)))
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t = Template(u"""/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ethernet {{n}} port multiplexer
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*/
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module {{name}}
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame inputs
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*/
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{%- for p in ports %}
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input wire input_{{p}}_eth_hdr_valid,
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output wire input_{{p}}_eth_hdr_ready,
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input wire [47:0] input_{{p}}_eth_dest_mac,
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input wire [47:0] input_{{p}}_eth_src_mac,
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input wire [15:0] input_{{p}}_eth_type,
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input wire [7:0] input_{{p}}_eth_payload_tdata,
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input wire input_{{p}}_eth_payload_tvalid,
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output wire input_{{p}}_eth_payload_tready,
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input wire input_{{p}}_eth_payload_tlast,
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input wire input_{{p}}_eth_payload_tuser,
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{% endfor %}
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/*
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* Ethernet frame output
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*/
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output wire output_eth_hdr_valid,
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input wire output_eth_hdr_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [7:0] output_eth_payload_tdata,
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output wire output_eth_payload_tvalid,
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input wire output_eth_payload_tready,
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output wire output_eth_payload_tlast,
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output wire output_eth_payload_tuser,
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/*
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* Control
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*/
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input wire enable,
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input wire [{{w-1}}:0] select
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);
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reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
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reg frame_reg = 1'b0, frame_next;
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{% for p in ports %}
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reg input_{{p}}_eth_hdr_ready_reg = 1'b0, input_{{p}}_eth_hdr_ready_next;
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{%- endfor %}
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{% for p in ports %}
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reg input_{{p}}_eth_payload_tready_reg = 1'b0, input_{{p}}_eth_payload_tready_next;
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{%- endfor %}
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reg output_eth_hdr_valid_reg = 1'b0, output_eth_hdr_valid_next;
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reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
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reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
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reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
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// internal datapath
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reg [7:0] output_eth_payload_tdata_int;
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reg output_eth_payload_tvalid_int;
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reg output_eth_payload_tready_int_reg = 1'b0;
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reg output_eth_payload_tlast_int;
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reg output_eth_payload_tuser_int;
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wire output_eth_payload_tready_int_early;
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{% for p in ports %}
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assign input_{{p}}_eth_hdr_ready = input_{{p}}_eth_hdr_ready_reg;
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{%- endfor %}
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{% for p in ports %}
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assign input_{{p}}_eth_payload_tready = input_{{p}}_eth_payload_tready_reg;
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{%- endfor %}
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assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
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assign output_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_eth_src_mac = output_eth_src_mac_reg;
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assign output_eth_type = output_eth_type_reg;
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// mux for start of packet detection
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reg selected_input_eth_hdr_valid;
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reg [47:0] selected_input_eth_dest_mac;
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reg [47:0] selected_input_eth_src_mac;
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reg [15:0] selected_input_eth_type;
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always @* begin
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case (select)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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selected_input_eth_hdr_valid = input_{{p}}_eth_hdr_valid;
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selected_input_eth_dest_mac = input_{{p}}_eth_dest_mac;
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selected_input_eth_src_mac = input_{{p}}_eth_src_mac;
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selected_input_eth_type = input_{{p}}_eth_type;
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end
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{%- endfor %}
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default: begin
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selected_input_eth_hdr_valid = 1'b0;
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selected_input_eth_dest_mac = 48'd0;
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selected_input_eth_src_mac = 48'd0;
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selected_input_eth_type = 16'd0;
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end
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endcase
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end
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// mux for incoming packet
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reg [7:0] current_input_tdata;
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reg current_input_tvalid;
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reg current_input_tready;
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reg current_input_tlast;
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reg current_input_tuser;
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always @* begin
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case (select_reg)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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current_input_tdata = input_{{p}}_eth_payload_tdata;
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current_input_tvalid = input_{{p}}_eth_payload_tvalid;
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current_input_tready = input_{{p}}_eth_payload_tready;
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current_input_tlast = input_{{p}}_eth_payload_tlast;
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current_input_tuser = input_{{p}}_eth_payload_tuser;
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end
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{%- endfor %}
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default: begin
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current_input_tdata = 8'd0;
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current_input_tvalid = 1'b0;
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current_input_tready = 1'b0;
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current_input_tlast = 1'b0;
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current_input_tuser = 1'b0;
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end
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endcase
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end
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always @* begin
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select_next = select_reg;
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frame_next = frame_reg;
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{% for p in ports %}
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input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_reg & ~input_{{p}}_eth_hdr_valid;
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{%- endfor %}
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{% for p in ports %}
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input_{{p}}_eth_payload_tready_next = 1'b0;
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{%- endfor %}
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output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
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output_eth_dest_mac_next = output_eth_dest_mac_reg;
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output_eth_src_mac_next = output_eth_src_mac_reg;
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output_eth_type_next = output_eth_type_reg;
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if (current_input_tvalid & current_input_tready) begin
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// end of frame detection
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if (current_input_tlast) begin
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frame_next = 1'b0;
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end
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end
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if (~frame_reg & enable & ~output_eth_hdr_valid & selected_input_eth_hdr_valid) begin
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// start of frame, grab select value
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frame_next = 1'b1;
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select_next = select;
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case (select_next)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_eth_hdr_ready_next = 1'b1;
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{%- endfor %}
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endcase
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output_eth_hdr_valid_next = 1'b1;
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output_eth_dest_mac_next = selected_input_eth_dest_mac;
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output_eth_src_mac_next = selected_input_eth_src_mac;
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output_eth_type_next = selected_input_eth_type;
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end
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// generate ready signal on selected port
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case (select_next)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
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{%- endfor %}
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endcase
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// pass through selected packet data
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output_eth_payload_tdata_int = current_input_tdata;
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output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
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output_eth_payload_tlast_int = current_input_tlast;
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output_eth_payload_tuser_int = current_input_tuser;
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end
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always @(posedge clk) begin
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if (rst) begin
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select_reg <= {{w}}'d0;
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frame_reg <= 1'b0;
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{%- for p in ports %}
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input_{{p}}_eth_hdr_ready_reg <= 1'b0;
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{%- endfor %}
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{%- for p in ports %}
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input_{{p}}_eth_payload_tready_reg <= 1'b0;
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{%- endfor %}
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output_eth_hdr_valid_reg <= 1'b0;
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end else begin
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select_reg <= select_next;
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frame_reg <= frame_next;
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{%- for p in ports %}
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input_{{p}}_eth_hdr_ready_reg <= input_{{p}}_eth_hdr_ready_next;
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{%- endfor %}
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{%- for p in ports %}
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input_{{p}}_eth_payload_tready_reg <= input_{{p}}_eth_payload_tready_next;
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{%- endfor %}
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output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
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end
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output_eth_dest_mac_reg <= output_eth_dest_mac_next;
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output_eth_src_mac_reg <= output_eth_src_mac_next;
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output_eth_type_reg <= output_eth_type_next;
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end
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// output datapath logic
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reg [7:0] output_eth_payload_tdata_reg = 8'd0;
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reg output_eth_payload_tvalid_reg = 1'b0, output_eth_payload_tvalid_next;
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reg output_eth_payload_tlast_reg = 1'b0;
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reg output_eth_payload_tuser_reg = 1'b0;
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reg [7:0] temp_eth_payload_tdata_reg = 8'd0;
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reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
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reg temp_eth_payload_tlast_reg = 1'b0;
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reg temp_eth_payload_tuser_reg = 1'b0;
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// datapath control
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reg store_eth_payload_int_to_output;
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reg store_eth_payload_int_to_temp;
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reg store_eth_payload_temp_to_output;
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assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
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assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
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assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
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assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & (~output_eth_payload_tvalid_reg | ~output_eth_payload_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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output_eth_payload_tvalid_next = output_eth_payload_tvalid_reg;
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temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
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store_eth_payload_int_to_output = 1'b0;
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store_eth_payload_int_to_temp = 1'b0;
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store_eth_payload_temp_to_output = 1'b0;
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if (output_eth_payload_tready_int_reg) begin
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// input is ready
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if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
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store_eth_payload_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
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store_eth_payload_int_to_temp = 1'b1;
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end
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end else if (output_eth_payload_tready) begin
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// input is not ready, but output is ready
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output_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
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temp_eth_payload_tvalid_next = 1'b0;
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store_eth_payload_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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output_eth_payload_tvalid_reg <= 1'b0;
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output_eth_payload_tready_int_reg <= 1'b0;
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temp_eth_payload_tvalid_reg <= 1'b0;
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end else begin
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output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_next;
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output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
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temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
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end
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// datapath
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if (store_eth_payload_int_to_output) begin
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output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
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output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
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output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
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end else if (store_eth_payload_temp_to_output) begin
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output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
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output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
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output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
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end
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if (store_eth_payload_int_to_temp) begin
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temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
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temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
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temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
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end
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end
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endmodule
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""")
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output_file.write(t.render(
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n=ports,
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w=select_width,
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name=name,
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ports=range(ports)
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))
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print("Done")
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if __name__ == "__main__":
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main()
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299
rtl/eth_mux.v
Normal file
299
rtl/eth_mux.v
Normal file
@ -0,0 +1,299 @@
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/*
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||||
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Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
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|
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// Language: Verilog 2001
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|
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`timescale 1ns / 1ps
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/*
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* Ethernet multiplexer
|
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*/
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module eth_mux #
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(
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parameter S_COUNT = 4,
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame inputs
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*/
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input wire [S_COUNT-1:0] s_eth_hdr_valid,
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output wire [S_COUNT-1:0] s_eth_hdr_ready,
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input wire [S_COUNT*48-1:0] s_eth_dest_mac,
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input wire [S_COUNT*48-1:0] s_eth_src_mac,
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input wire [S_COUNT*16-1:0] s_eth_type,
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input wire [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
|
||||
input wire [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
|
||||
input wire [S_COUNT-1:0] s_eth_payload_axis_tvalid,
|
||||
output wire [S_COUNT-1:0] s_eth_payload_axis_tready,
|
||||
input wire [S_COUNT-1:0] s_eth_payload_axis_tlast,
|
||||
input wire [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid,
|
||||
input wire [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
|
||||
input wire [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire m_eth_hdr_valid,
|
||||
input wire m_eth_hdr_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
|
||||
output wire m_eth_payload_axis_tvalid,
|
||||
input wire m_eth_payload_axis_tready,
|
||||
output wire m_eth_payload_axis_tlast,
|
||||
output wire [ID_WIDTH-1:0] m_eth_payload_axis_tid,
|
||||
output wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
|
||||
output wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable,
|
||||
input wire [$clog2(S_COUNT)-1:0] select
|
||||
);
|
||||
|
||||
parameter CL_S_COUNT = $clog2(S_COUNT);
|
||||
|
||||
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
|
||||
reg [S_COUNT-1:0] s_eth_hdr_ready_reg = 0, s_eth_hdr_ready_next;
|
||||
|
||||
reg [S_COUNT-1:0] s_eth_payload_axis_tready_reg = 0, s_eth_payload_axis_tready_next;
|
||||
|
||||
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
|
||||
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
|
||||
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
|
||||
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
|
||||
|
||||
// internal datapath
|
||||
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
|
||||
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
|
||||
reg m_eth_payload_axis_tvalid_int;
|
||||
reg m_eth_payload_axis_tready_int_reg = 1'b0;
|
||||
reg m_eth_payload_axis_tlast_int;
|
||||
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
|
||||
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
|
||||
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
|
||||
wire m_eth_payload_axis_tready_int_early;
|
||||
|
||||
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
|
||||
|
||||
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
|
||||
|
||||
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
|
||||
assign m_eth_dest_mac = m_eth_dest_mac_reg;
|
||||
assign m_eth_src_mac = m_eth_src_mac_reg;
|
||||
assign m_eth_type = m_eth_type_reg;
|
||||
|
||||
// mux for incoming packet
|
||||
wire [DATA_WIDTH-1:0] current_s_tdata = s_eth_payload_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
|
||||
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_eth_payload_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
|
||||
wire current_s_tvalid = s_eth_payload_axis_tvalid[select_reg];
|
||||
wire current_s_tready = s_eth_payload_axis_tready[select_reg];
|
||||
wire current_s_tlast = s_eth_payload_axis_tlast[select_reg];
|
||||
wire [ID_WIDTH-1:0] current_s_tid = s_eth_payload_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
|
||||
wire [DEST_WIDTH-1:0] current_s_tdest = s_eth_payload_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
|
||||
wire [USER_WIDTH-1:0] current_s_tuser = s_eth_payload_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
|
||||
|
||||
always @* begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
|
||||
s_eth_hdr_ready_next = 0;
|
||||
|
||||
s_eth_payload_axis_tready_next = 0;
|
||||
|
||||
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
|
||||
m_eth_dest_mac_next = m_eth_dest_mac_reg;
|
||||
m_eth_src_mac_next = m_eth_src_mac_reg;
|
||||
m_eth_type_next = m_eth_type_reg;
|
||||
|
||||
if (current_s_tvalid & current_s_tready) begin
|
||||
// end of frame detection
|
||||
if (current_s_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (!frame_reg && enable && !m_eth_hdr_valid && (s_eth_hdr_valid & (1 << select))) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
|
||||
s_eth_hdr_ready_next = (1 << select);
|
||||
|
||||
m_eth_hdr_valid_next = 1'b1;
|
||||
m_eth_dest_mac_next = s_eth_dest_mac[select*48 +: 48];
|
||||
m_eth_src_mac_next = s_eth_src_mac[select*48 +: 48];
|
||||
m_eth_type_next = s_eth_type[select*16 +: 16];
|
||||
end
|
||||
|
||||
// generate ready signal on selected port
|
||||
s_eth_payload_axis_tready_next = (m_eth_payload_axis_tready_int_early && frame_next) << select_next;
|
||||
|
||||
// pass through selected packet data
|
||||
m_eth_payload_axis_tdata_int = current_s_tdata;
|
||||
m_eth_payload_axis_tkeep_int = current_s_tkeep;
|
||||
m_eth_payload_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
|
||||
m_eth_payload_axis_tlast_int = current_s_tlast;
|
||||
m_eth_payload_axis_tid_int = current_s_tid;
|
||||
m_eth_payload_axis_tdest_int = current_s_tdest;
|
||||
m_eth_payload_axis_tuser_int = current_s_tuser;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
select_reg <= 0;
|
||||
frame_reg <= 1'b0;
|
||||
s_eth_hdr_ready_reg <= 0;
|
||||
s_eth_payload_axis_tready_reg <= 0;
|
||||
m_eth_hdr_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
|
||||
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
|
||||
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
|
||||
end
|
||||
|
||||
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
|
||||
m_eth_src_mac_reg <= m_eth_src_mac_next;
|
||||
m_eth_type_reg <= m_eth_type_next;
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
|
||||
reg m_eth_payload_axis_tlast_reg = 1'b0;
|
||||
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
|
||||
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
|
||||
|
||||
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
|
||||
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
|
||||
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
|
||||
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
|
||||
|
||||
// datapath control
|
||||
reg store_axis_int_to_output;
|
||||
reg store_axis_int_to_temp;
|
||||
reg store_axis_temp_to_output;
|
||||
|
||||
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
|
||||
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
|
||||
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
|
||||
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
|
||||
assign m_eth_payload_axis_tid = ID_ENABLE ? m_eth_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
|
||||
assign m_eth_payload_axis_tdest = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
|
||||
assign m_eth_payload_axis_tuser = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
|
||||
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
|
||||
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (m_eth_payload_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
|
||||
store_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
|
||||
store_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_eth_payload_axis_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
|
||||
temp_m_eth_payload_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
m_eth_payload_axis_tvalid_reg <= 1'b0;
|
||||
m_eth_payload_axis_tready_int_reg <= 1'b0;
|
||||
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
|
||||
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
|
||||
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
|
||||
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
|
||||
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
|
||||
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
|
||||
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
|
||||
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
|
||||
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
|
||||
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
|
||||
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
|
||||
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
|
||||
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
|
||||
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
|
||||
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
|
||||
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
|
||||
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
|
||||
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
332
rtl/eth_mux_2.v
332
rtl/eth_mux_2.v
@ -1,332 +0,0 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Ethernet 2 port multiplexer
|
||||
*/
|
||||
module eth_mux_2
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame inputs
|
||||
*/
|
||||
input wire input_0_eth_hdr_valid,
|
||||
output wire input_0_eth_hdr_ready,
|
||||
input wire [47:0] input_0_eth_dest_mac,
|
||||
input wire [47:0] input_0_eth_src_mac,
|
||||
input wire [15:0] input_0_eth_type,
|
||||
input wire [7:0] input_0_eth_payload_tdata,
|
||||
input wire input_0_eth_payload_tvalid,
|
||||
output wire input_0_eth_payload_tready,
|
||||
input wire input_0_eth_payload_tlast,
|
||||
input wire input_0_eth_payload_tuser,
|
||||
|
||||
input wire input_1_eth_hdr_valid,
|
||||
output wire input_1_eth_hdr_ready,
|
||||
input wire [47:0] input_1_eth_dest_mac,
|
||||
input wire [47:0] input_1_eth_src_mac,
|
||||
input wire [15:0] input_1_eth_type,
|
||||
input wire [7:0] input_1_eth_payload_tdata,
|
||||
input wire input_1_eth_payload_tvalid,
|
||||
output wire input_1_eth_payload_tready,
|
||||
input wire input_1_eth_payload_tlast,
|
||||
input wire input_1_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire output_eth_hdr_valid,
|
||||
input wire output_eth_hdr_ready,
|
||||
output wire [47:0] output_eth_dest_mac,
|
||||
output wire [47:0] output_eth_src_mac,
|
||||
output wire [15:0] output_eth_type,
|
||||
output wire [7:0] output_eth_payload_tdata,
|
||||
output wire output_eth_payload_tvalid,
|
||||
input wire output_eth_payload_tready,
|
||||
output wire output_eth_payload_tlast,
|
||||
output wire output_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable,
|
||||
input wire [0:0] select
|
||||
);
|
||||
|
||||
reg [0:0] select_reg = 1'd0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
|
||||
reg input_0_eth_hdr_ready_reg = 1'b0, input_0_eth_hdr_ready_next;
|
||||
reg input_1_eth_hdr_ready_reg = 1'b0, input_1_eth_hdr_ready_next;
|
||||
|
||||
reg input_0_eth_payload_tready_reg = 1'b0, input_0_eth_payload_tready_next;
|
||||
reg input_1_eth_payload_tready_reg = 1'b0, input_1_eth_payload_tready_next;
|
||||
|
||||
reg output_eth_hdr_valid_reg = 1'b0, output_eth_hdr_valid_next;
|
||||
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
|
||||
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
|
||||
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
|
||||
|
||||
// internal datapath
|
||||
reg [7:0] output_eth_payload_tdata_int;
|
||||
reg output_eth_payload_tvalid_int;
|
||||
reg output_eth_payload_tready_int_reg = 1'b0;
|
||||
reg output_eth_payload_tlast_int;
|
||||
reg output_eth_payload_tuser_int;
|
||||
wire output_eth_payload_tready_int_early;
|
||||
|
||||
assign input_0_eth_hdr_ready = input_0_eth_hdr_ready_reg;
|
||||
assign input_1_eth_hdr_ready = input_1_eth_hdr_ready_reg;
|
||||
|
||||
assign input_0_eth_payload_tready = input_0_eth_payload_tready_reg;
|
||||
assign input_1_eth_payload_tready = input_1_eth_payload_tready_reg;
|
||||
|
||||
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
|
||||
assign output_eth_dest_mac = output_eth_dest_mac_reg;
|
||||
assign output_eth_src_mac = output_eth_src_mac_reg;
|
||||
assign output_eth_type = output_eth_type_reg;
|
||||
|
||||
// mux for start of packet detection
|
||||
reg selected_input_eth_hdr_valid;
|
||||
reg [47:0] selected_input_eth_dest_mac;
|
||||
reg [47:0] selected_input_eth_src_mac;
|
||||
reg [15:0] selected_input_eth_type;
|
||||
always @* begin
|
||||
case (select)
|
||||
1'd0: begin
|
||||
selected_input_eth_hdr_valid = input_0_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_0_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_0_eth_src_mac;
|
||||
selected_input_eth_type = input_0_eth_type;
|
||||
end
|
||||
1'd1: begin
|
||||
selected_input_eth_hdr_valid = input_1_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_1_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_1_eth_src_mac;
|
||||
selected_input_eth_type = input_1_eth_type;
|
||||
end
|
||||
default: begin
|
||||
selected_input_eth_hdr_valid = 1'b0;
|
||||
selected_input_eth_dest_mac = 48'd0;
|
||||
selected_input_eth_src_mac = 48'd0;
|
||||
selected_input_eth_type = 16'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// mux for incoming packet
|
||||
reg [7:0] current_input_tdata;
|
||||
reg current_input_tvalid;
|
||||
reg current_input_tready;
|
||||
reg current_input_tlast;
|
||||
reg current_input_tuser;
|
||||
always @* begin
|
||||
case (select_reg)
|
||||
1'd0: begin
|
||||
current_input_tdata = input_0_eth_payload_tdata;
|
||||
current_input_tvalid = input_0_eth_payload_tvalid;
|
||||
current_input_tready = input_0_eth_payload_tready;
|
||||
current_input_tlast = input_0_eth_payload_tlast;
|
||||
current_input_tuser = input_0_eth_payload_tuser;
|
||||
end
|
||||
1'd1: begin
|
||||
current_input_tdata = input_1_eth_payload_tdata;
|
||||
current_input_tvalid = input_1_eth_payload_tvalid;
|
||||
current_input_tready = input_1_eth_payload_tready;
|
||||
current_input_tlast = input_1_eth_payload_tlast;
|
||||
current_input_tuser = input_1_eth_payload_tuser;
|
||||
end
|
||||
default: begin
|
||||
current_input_tdata = 8'd0;
|
||||
current_input_tvalid = 1'b0;
|
||||
current_input_tready = 1'b0;
|
||||
current_input_tlast = 1'b0;
|
||||
current_input_tuser = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
|
||||
input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_reg & ~input_0_eth_hdr_valid;
|
||||
input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_reg & ~input_1_eth_hdr_valid;
|
||||
|
||||
input_0_eth_payload_tready_next = 1'b0;
|
||||
input_1_eth_payload_tready_next = 1'b0;
|
||||
|
||||
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
|
||||
output_eth_dest_mac_next = output_eth_dest_mac_reg;
|
||||
output_eth_src_mac_next = output_eth_src_mac_reg;
|
||||
output_eth_type_next = output_eth_type_reg;
|
||||
|
||||
if (current_input_tvalid & current_input_tready) begin
|
||||
// end of frame detection
|
||||
if (current_input_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (~frame_reg & enable & ~output_eth_hdr_valid & selected_input_eth_hdr_valid) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
|
||||
case (select_next)
|
||||
1'd0: input_0_eth_hdr_ready_next = 1'b1;
|
||||
1'd1: input_1_eth_hdr_ready_next = 1'b1;
|
||||
endcase
|
||||
|
||||
output_eth_hdr_valid_next = 1'b1;
|
||||
output_eth_dest_mac_next = selected_input_eth_dest_mac;
|
||||
output_eth_src_mac_next = selected_input_eth_src_mac;
|
||||
output_eth_type_next = selected_input_eth_type;
|
||||
end
|
||||
|
||||
// generate ready signal on selected port
|
||||
case (select_next)
|
||||
1'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
1'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
endcase
|
||||
|
||||
// pass through selected packet data
|
||||
output_eth_payload_tdata_int = current_input_tdata;
|
||||
output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
|
||||
output_eth_payload_tlast_int = current_input_tlast;
|
||||
output_eth_payload_tuser_int = current_input_tuser;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
select_reg <= 1'd0;
|
||||
frame_reg <= 1'b0;
|
||||
input_0_eth_hdr_ready_reg <= 1'b0;
|
||||
input_1_eth_hdr_ready_reg <= 1'b0;
|
||||
input_0_eth_payload_tready_reg <= 1'b0;
|
||||
input_1_eth_payload_tready_reg <= 1'b0;
|
||||
output_eth_hdr_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
input_0_eth_hdr_ready_reg <= input_0_eth_hdr_ready_next;
|
||||
input_1_eth_hdr_ready_reg <= input_1_eth_hdr_ready_next;
|
||||
input_0_eth_payload_tready_reg <= input_0_eth_payload_tready_next;
|
||||
input_1_eth_payload_tready_reg <= input_1_eth_payload_tready_next;
|
||||
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
|
||||
end
|
||||
|
||||
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
|
||||
output_eth_src_mac_reg <= output_eth_src_mac_next;
|
||||
output_eth_type_reg <= output_eth_type_next;
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [7:0] output_eth_payload_tdata_reg = 8'd0;
|
||||
reg output_eth_payload_tvalid_reg = 1'b0, output_eth_payload_tvalid_next;
|
||||
reg output_eth_payload_tlast_reg = 1'b0;
|
||||
reg output_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
reg [7:0] temp_eth_payload_tdata_reg = 8'd0;
|
||||
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
|
||||
reg temp_eth_payload_tlast_reg = 1'b0;
|
||||
reg temp_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_eth_payload_int_to_output;
|
||||
reg store_eth_payload_int_to_temp;
|
||||
reg store_eth_payload_temp_to_output;
|
||||
|
||||
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
|
||||
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
|
||||
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
|
||||
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & (~output_eth_payload_tvalid_reg | ~output_eth_payload_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
|
||||
store_eth_payload_int_to_output = 1'b0;
|
||||
store_eth_payload_int_to_temp = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b0;
|
||||
|
||||
if (output_eth_payload_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (output_eth_payload_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
output_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
output_eth_payload_tvalid_reg <= 1'b0;
|
||||
output_eth_payload_tready_int_reg <= 1'b0;
|
||||
temp_eth_payload_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_next;
|
||||
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
|
||||
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_eth_payload_int_to_output) begin
|
||||
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end else if (store_eth_payload_temp_to_output) begin
|
||||
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
|
||||
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
|
||||
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_eth_payload_int_to_temp) begin
|
||||
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
404
rtl/eth_mux_4.v
404
rtl/eth_mux_4.v
@ -1,404 +0,0 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Ethernet 4 port multiplexer
|
||||
*/
|
||||
module eth_mux_4
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame inputs
|
||||
*/
|
||||
input wire input_0_eth_hdr_valid,
|
||||
output wire input_0_eth_hdr_ready,
|
||||
input wire [47:0] input_0_eth_dest_mac,
|
||||
input wire [47:0] input_0_eth_src_mac,
|
||||
input wire [15:0] input_0_eth_type,
|
||||
input wire [7:0] input_0_eth_payload_tdata,
|
||||
input wire input_0_eth_payload_tvalid,
|
||||
output wire input_0_eth_payload_tready,
|
||||
input wire input_0_eth_payload_tlast,
|
||||
input wire input_0_eth_payload_tuser,
|
||||
|
||||
input wire input_1_eth_hdr_valid,
|
||||
output wire input_1_eth_hdr_ready,
|
||||
input wire [47:0] input_1_eth_dest_mac,
|
||||
input wire [47:0] input_1_eth_src_mac,
|
||||
input wire [15:0] input_1_eth_type,
|
||||
input wire [7:0] input_1_eth_payload_tdata,
|
||||
input wire input_1_eth_payload_tvalid,
|
||||
output wire input_1_eth_payload_tready,
|
||||
input wire input_1_eth_payload_tlast,
|
||||
input wire input_1_eth_payload_tuser,
|
||||
|
||||
input wire input_2_eth_hdr_valid,
|
||||
output wire input_2_eth_hdr_ready,
|
||||
input wire [47:0] input_2_eth_dest_mac,
|
||||
input wire [47:0] input_2_eth_src_mac,
|
||||
input wire [15:0] input_2_eth_type,
|
||||
input wire [7:0] input_2_eth_payload_tdata,
|
||||
input wire input_2_eth_payload_tvalid,
|
||||
output wire input_2_eth_payload_tready,
|
||||
input wire input_2_eth_payload_tlast,
|
||||
input wire input_2_eth_payload_tuser,
|
||||
|
||||
input wire input_3_eth_hdr_valid,
|
||||
output wire input_3_eth_hdr_ready,
|
||||
input wire [47:0] input_3_eth_dest_mac,
|
||||
input wire [47:0] input_3_eth_src_mac,
|
||||
input wire [15:0] input_3_eth_type,
|
||||
input wire [7:0] input_3_eth_payload_tdata,
|
||||
input wire input_3_eth_payload_tvalid,
|
||||
output wire input_3_eth_payload_tready,
|
||||
input wire input_3_eth_payload_tlast,
|
||||
input wire input_3_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire output_eth_hdr_valid,
|
||||
input wire output_eth_hdr_ready,
|
||||
output wire [47:0] output_eth_dest_mac,
|
||||
output wire [47:0] output_eth_src_mac,
|
||||
output wire [15:0] output_eth_type,
|
||||
output wire [7:0] output_eth_payload_tdata,
|
||||
output wire output_eth_payload_tvalid,
|
||||
input wire output_eth_payload_tready,
|
||||
output wire output_eth_payload_tlast,
|
||||
output wire output_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable,
|
||||
input wire [1:0] select
|
||||
);
|
||||
|
||||
reg [1:0] select_reg = 2'd0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
|
||||
reg input_0_eth_hdr_ready_reg = 1'b0, input_0_eth_hdr_ready_next;
|
||||
reg input_1_eth_hdr_ready_reg = 1'b0, input_1_eth_hdr_ready_next;
|
||||
reg input_2_eth_hdr_ready_reg = 1'b0, input_2_eth_hdr_ready_next;
|
||||
reg input_3_eth_hdr_ready_reg = 1'b0, input_3_eth_hdr_ready_next;
|
||||
|
||||
reg input_0_eth_payload_tready_reg = 1'b0, input_0_eth_payload_tready_next;
|
||||
reg input_1_eth_payload_tready_reg = 1'b0, input_1_eth_payload_tready_next;
|
||||
reg input_2_eth_payload_tready_reg = 1'b0, input_2_eth_payload_tready_next;
|
||||
reg input_3_eth_payload_tready_reg = 1'b0, input_3_eth_payload_tready_next;
|
||||
|
||||
reg output_eth_hdr_valid_reg = 1'b0, output_eth_hdr_valid_next;
|
||||
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
|
||||
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
|
||||
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
|
||||
|
||||
// internal datapath
|
||||
reg [7:0] output_eth_payload_tdata_int;
|
||||
reg output_eth_payload_tvalid_int;
|
||||
reg output_eth_payload_tready_int_reg = 1'b0;
|
||||
reg output_eth_payload_tlast_int;
|
||||
reg output_eth_payload_tuser_int;
|
||||
wire output_eth_payload_tready_int_early;
|
||||
|
||||
assign input_0_eth_hdr_ready = input_0_eth_hdr_ready_reg;
|
||||
assign input_1_eth_hdr_ready = input_1_eth_hdr_ready_reg;
|
||||
assign input_2_eth_hdr_ready = input_2_eth_hdr_ready_reg;
|
||||
assign input_3_eth_hdr_ready = input_3_eth_hdr_ready_reg;
|
||||
|
||||
assign input_0_eth_payload_tready = input_0_eth_payload_tready_reg;
|
||||
assign input_1_eth_payload_tready = input_1_eth_payload_tready_reg;
|
||||
assign input_2_eth_payload_tready = input_2_eth_payload_tready_reg;
|
||||
assign input_3_eth_payload_tready = input_3_eth_payload_tready_reg;
|
||||
|
||||
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
|
||||
assign output_eth_dest_mac = output_eth_dest_mac_reg;
|
||||
assign output_eth_src_mac = output_eth_src_mac_reg;
|
||||
assign output_eth_type = output_eth_type_reg;
|
||||
|
||||
// mux for start of packet detection
|
||||
reg selected_input_eth_hdr_valid;
|
||||
reg [47:0] selected_input_eth_dest_mac;
|
||||
reg [47:0] selected_input_eth_src_mac;
|
||||
reg [15:0] selected_input_eth_type;
|
||||
always @* begin
|
||||
case (select)
|
||||
2'd0: begin
|
||||
selected_input_eth_hdr_valid = input_0_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_0_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_0_eth_src_mac;
|
||||
selected_input_eth_type = input_0_eth_type;
|
||||
end
|
||||
2'd1: begin
|
||||
selected_input_eth_hdr_valid = input_1_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_1_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_1_eth_src_mac;
|
||||
selected_input_eth_type = input_1_eth_type;
|
||||
end
|
||||
2'd2: begin
|
||||
selected_input_eth_hdr_valid = input_2_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_2_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_2_eth_src_mac;
|
||||
selected_input_eth_type = input_2_eth_type;
|
||||
end
|
||||
2'd3: begin
|
||||
selected_input_eth_hdr_valid = input_3_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_3_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_3_eth_src_mac;
|
||||
selected_input_eth_type = input_3_eth_type;
|
||||
end
|
||||
default: begin
|
||||
selected_input_eth_hdr_valid = 1'b0;
|
||||
selected_input_eth_dest_mac = 48'd0;
|
||||
selected_input_eth_src_mac = 48'd0;
|
||||
selected_input_eth_type = 16'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// mux for incoming packet
|
||||
reg [7:0] current_input_tdata;
|
||||
reg current_input_tvalid;
|
||||
reg current_input_tready;
|
||||
reg current_input_tlast;
|
||||
reg current_input_tuser;
|
||||
always @* begin
|
||||
case (select_reg)
|
||||
2'd0: begin
|
||||
current_input_tdata = input_0_eth_payload_tdata;
|
||||
current_input_tvalid = input_0_eth_payload_tvalid;
|
||||
current_input_tready = input_0_eth_payload_tready;
|
||||
current_input_tlast = input_0_eth_payload_tlast;
|
||||
current_input_tuser = input_0_eth_payload_tuser;
|
||||
end
|
||||
2'd1: begin
|
||||
current_input_tdata = input_1_eth_payload_tdata;
|
||||
current_input_tvalid = input_1_eth_payload_tvalid;
|
||||
current_input_tready = input_1_eth_payload_tready;
|
||||
current_input_tlast = input_1_eth_payload_tlast;
|
||||
current_input_tuser = input_1_eth_payload_tuser;
|
||||
end
|
||||
2'd2: begin
|
||||
current_input_tdata = input_2_eth_payload_tdata;
|
||||
current_input_tvalid = input_2_eth_payload_tvalid;
|
||||
current_input_tready = input_2_eth_payload_tready;
|
||||
current_input_tlast = input_2_eth_payload_tlast;
|
||||
current_input_tuser = input_2_eth_payload_tuser;
|
||||
end
|
||||
2'd3: begin
|
||||
current_input_tdata = input_3_eth_payload_tdata;
|
||||
current_input_tvalid = input_3_eth_payload_tvalid;
|
||||
current_input_tready = input_3_eth_payload_tready;
|
||||
current_input_tlast = input_3_eth_payload_tlast;
|
||||
current_input_tuser = input_3_eth_payload_tuser;
|
||||
end
|
||||
default: begin
|
||||
current_input_tdata = 8'd0;
|
||||
current_input_tvalid = 1'b0;
|
||||
current_input_tready = 1'b0;
|
||||
current_input_tlast = 1'b0;
|
||||
current_input_tuser = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
|
||||
input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_reg & ~input_0_eth_hdr_valid;
|
||||
input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_reg & ~input_1_eth_hdr_valid;
|
||||
input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_reg & ~input_2_eth_hdr_valid;
|
||||
input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_reg & ~input_3_eth_hdr_valid;
|
||||
|
||||
input_0_eth_payload_tready_next = 1'b0;
|
||||
input_1_eth_payload_tready_next = 1'b0;
|
||||
input_2_eth_payload_tready_next = 1'b0;
|
||||
input_3_eth_payload_tready_next = 1'b0;
|
||||
|
||||
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
|
||||
output_eth_dest_mac_next = output_eth_dest_mac_reg;
|
||||
output_eth_src_mac_next = output_eth_src_mac_reg;
|
||||
output_eth_type_next = output_eth_type_reg;
|
||||
|
||||
if (current_input_tvalid & current_input_tready) begin
|
||||
// end of frame detection
|
||||
if (current_input_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (~frame_reg & enable & ~output_eth_hdr_valid & selected_input_eth_hdr_valid) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
|
||||
case (select_next)
|
||||
2'd0: input_0_eth_hdr_ready_next = 1'b1;
|
||||
2'd1: input_1_eth_hdr_ready_next = 1'b1;
|
||||
2'd2: input_2_eth_hdr_ready_next = 1'b1;
|
||||
2'd3: input_3_eth_hdr_ready_next = 1'b1;
|
||||
endcase
|
||||
|
||||
output_eth_hdr_valid_next = 1'b1;
|
||||
output_eth_dest_mac_next = selected_input_eth_dest_mac;
|
||||
output_eth_src_mac_next = selected_input_eth_src_mac;
|
||||
output_eth_type_next = selected_input_eth_type;
|
||||
end
|
||||
|
||||
// generate ready signal on selected port
|
||||
case (select_next)
|
||||
2'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
2'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
2'd2: input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
2'd3: input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
endcase
|
||||
|
||||
// pass through selected packet data
|
||||
output_eth_payload_tdata_int = current_input_tdata;
|
||||
output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
|
||||
output_eth_payload_tlast_int = current_input_tlast;
|
||||
output_eth_payload_tuser_int = current_input_tuser;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
select_reg <= 2'd0;
|
||||
frame_reg <= 1'b0;
|
||||
input_0_eth_hdr_ready_reg <= 1'b0;
|
||||
input_1_eth_hdr_ready_reg <= 1'b0;
|
||||
input_2_eth_hdr_ready_reg <= 1'b0;
|
||||
input_3_eth_hdr_ready_reg <= 1'b0;
|
||||
input_0_eth_payload_tready_reg <= 1'b0;
|
||||
input_1_eth_payload_tready_reg <= 1'b0;
|
||||
input_2_eth_payload_tready_reg <= 1'b0;
|
||||
input_3_eth_payload_tready_reg <= 1'b0;
|
||||
output_eth_hdr_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
input_0_eth_hdr_ready_reg <= input_0_eth_hdr_ready_next;
|
||||
input_1_eth_hdr_ready_reg <= input_1_eth_hdr_ready_next;
|
||||
input_2_eth_hdr_ready_reg <= input_2_eth_hdr_ready_next;
|
||||
input_3_eth_hdr_ready_reg <= input_3_eth_hdr_ready_next;
|
||||
input_0_eth_payload_tready_reg <= input_0_eth_payload_tready_next;
|
||||
input_1_eth_payload_tready_reg <= input_1_eth_payload_tready_next;
|
||||
input_2_eth_payload_tready_reg <= input_2_eth_payload_tready_next;
|
||||
input_3_eth_payload_tready_reg <= input_3_eth_payload_tready_next;
|
||||
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
|
||||
end
|
||||
|
||||
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
|
||||
output_eth_src_mac_reg <= output_eth_src_mac_next;
|
||||
output_eth_type_reg <= output_eth_type_next;
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [7:0] output_eth_payload_tdata_reg = 8'd0;
|
||||
reg output_eth_payload_tvalid_reg = 1'b0, output_eth_payload_tvalid_next;
|
||||
reg output_eth_payload_tlast_reg = 1'b0;
|
||||
reg output_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
reg [7:0] temp_eth_payload_tdata_reg = 8'd0;
|
||||
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
|
||||
reg temp_eth_payload_tlast_reg = 1'b0;
|
||||
reg temp_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_eth_payload_int_to_output;
|
||||
reg store_eth_payload_int_to_temp;
|
||||
reg store_eth_payload_temp_to_output;
|
||||
|
||||
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
|
||||
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
|
||||
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
|
||||
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & (~output_eth_payload_tvalid_reg | ~output_eth_payload_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
|
||||
store_eth_payload_int_to_output = 1'b0;
|
||||
store_eth_payload_int_to_temp = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b0;
|
||||
|
||||
if (output_eth_payload_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (output_eth_payload_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
output_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
output_eth_payload_tvalid_reg <= 1'b0;
|
||||
output_eth_payload_tready_int_reg <= 1'b0;
|
||||
temp_eth_payload_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_next;
|
||||
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
|
||||
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_eth_payload_int_to_output) begin
|
||||
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end else if (store_eth_payload_temp_to_output) begin
|
||||
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
|
||||
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
|
||||
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_eth_payload_int_to_temp) begin
|
||||
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,387 +0,0 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
Generates an Ethernet mux with the specified number of ports
|
||||
"""
|
||||
|
||||
from __future__ import print_function
|
||||
|
||||
import argparse
|
||||
import math
|
||||
from jinja2 import Template
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description=__doc__.strip())
|
||||
parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
|
||||
parser.add_argument('-n', '--name', type=str, help="module name")
|
||||
parser.add_argument('-o', '--output', type=str, help="output file name")
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
try:
|
||||
generate(**args.__dict__)
|
||||
except IOError as ex:
|
||||
print(ex)
|
||||
exit(1)
|
||||
|
||||
def generate(ports=4, name=None, output=None):
|
||||
if name is None:
|
||||
name = "eth_mux_64_{0}".format(ports)
|
||||
|
||||
if output is None:
|
||||
output = name + ".v"
|
||||
|
||||
print("Opening file '{0}'...".format(output))
|
||||
|
||||
output_file = open(output, 'w')
|
||||
|
||||
print("Generating {0} port Ethernet mux {1}...".format(ports, name))
|
||||
|
||||
select_width = int(math.ceil(math.log(ports, 2)))
|
||||
|
||||
t = Template(u"""/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Ethernet {{n}} port multiplexer (64 bit datapath)
|
||||
*/
|
||||
module {{name}}
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame inputs
|
||||
*/
|
||||
{%- for p in ports %}
|
||||
input wire input_{{p}}_eth_hdr_valid,
|
||||
output wire input_{{p}}_eth_hdr_ready,
|
||||
input wire [47:0] input_{{p}}_eth_dest_mac,
|
||||
input wire [47:0] input_{{p}}_eth_src_mac,
|
||||
input wire [15:0] input_{{p}}_eth_type,
|
||||
input wire [63:0] input_{{p}}_eth_payload_tdata,
|
||||
input wire [7:0] input_{{p}}_eth_payload_tkeep,
|
||||
input wire input_{{p}}_eth_payload_tvalid,
|
||||
output wire input_{{p}}_eth_payload_tready,
|
||||
input wire input_{{p}}_eth_payload_tlast,
|
||||
input wire input_{{p}}_eth_payload_tuser,
|
||||
{% endfor %}
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire output_eth_hdr_valid,
|
||||
input wire output_eth_hdr_ready,
|
||||
output wire [47:0] output_eth_dest_mac,
|
||||
output wire [47:0] output_eth_src_mac,
|
||||
output wire [15:0] output_eth_type,
|
||||
output wire [63:0] output_eth_payload_tdata,
|
||||
output wire [7:0] output_eth_payload_tkeep,
|
||||
output wire output_eth_payload_tvalid,
|
||||
input wire output_eth_payload_tready,
|
||||
output wire output_eth_payload_tlast,
|
||||
output wire output_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable,
|
||||
input wire [{{w-1}}:0] select
|
||||
);
|
||||
|
||||
reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
{% for p in ports %}
|
||||
reg input_{{p}}_eth_hdr_ready_reg = 1'b0, input_{{p}}_eth_hdr_ready_next;
|
||||
{%- endfor %}
|
||||
{% for p in ports %}
|
||||
reg input_{{p}}_eth_payload_tready_reg = 1'b0, input_{{p}}_eth_payload_tready_next;
|
||||
{%- endfor %}
|
||||
|
||||
reg output_eth_hdr_valid_reg = 1'b0, output_eth_hdr_valid_next;
|
||||
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
|
||||
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
|
||||
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
|
||||
|
||||
// internal datapath
|
||||
reg [63:0] output_eth_payload_tdata_int;
|
||||
reg [7:0] output_eth_payload_tkeep_int;
|
||||
reg output_eth_payload_tvalid_int;
|
||||
reg output_eth_payload_tready_int_reg = 1'b0;
|
||||
reg output_eth_payload_tlast_int;
|
||||
reg output_eth_payload_tuser_int;
|
||||
wire output_eth_payload_tready_int_early;
|
||||
{% for p in ports %}
|
||||
assign input_{{p}}_eth_hdr_ready = input_{{p}}_eth_hdr_ready_reg;
|
||||
{%- endfor %}
|
||||
{% for p in ports %}
|
||||
assign input_{{p}}_eth_payload_tready = input_{{p}}_eth_payload_tready_reg;
|
||||
{%- endfor %}
|
||||
|
||||
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
|
||||
assign output_eth_dest_mac = output_eth_dest_mac_reg;
|
||||
assign output_eth_src_mac = output_eth_src_mac_reg;
|
||||
assign output_eth_type = output_eth_type_reg;
|
||||
|
||||
// mux for start of packet detection
|
||||
reg selected_input_eth_hdr_valid;
|
||||
reg [47:0] selected_input_eth_dest_mac;
|
||||
reg [47:0] selected_input_eth_src_mac;
|
||||
reg [15:0] selected_input_eth_type;
|
||||
always @* begin
|
||||
case (select)
|
||||
{%- for p in ports %}
|
||||
{{w}}'d{{p}}: begin
|
||||
selected_input_eth_hdr_valid = input_{{p}}_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_{{p}}_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_{{p}}_eth_src_mac;
|
||||
selected_input_eth_type = input_{{p}}_eth_type;
|
||||
end
|
||||
{%- endfor %}
|
||||
default: begin
|
||||
selected_input_eth_hdr_valid = 1'b0;
|
||||
selected_input_eth_dest_mac = 48'd0;
|
||||
selected_input_eth_src_mac = 48'd0;
|
||||
selected_input_eth_type = 16'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// mux for incoming packet
|
||||
reg [63:0] current_input_tdata;
|
||||
reg [7:0] current_input_tkeep;
|
||||
reg current_input_tvalid;
|
||||
reg current_input_tready;
|
||||
reg current_input_tlast;
|
||||
reg current_input_tuser;
|
||||
always @* begin
|
||||
case (select_reg)
|
||||
{%- for p in ports %}
|
||||
{{w}}'d{{p}}: begin
|
||||
current_input_tdata = input_{{p}}_eth_payload_tdata;
|
||||
current_input_tkeep = input_{{p}}_eth_payload_tkeep;
|
||||
current_input_tvalid = input_{{p}}_eth_payload_tvalid;
|
||||
current_input_tready = input_{{p}}_eth_payload_tready;
|
||||
current_input_tlast = input_{{p}}_eth_payload_tlast;
|
||||
current_input_tuser = input_{{p}}_eth_payload_tuser;
|
||||
end
|
||||
{%- endfor %}
|
||||
default: begin
|
||||
current_input_tdata = 64'd0;
|
||||
current_input_tkeep = 8'd0;
|
||||
current_input_tvalid = 1'b0;
|
||||
current_input_tready = 1'b0;
|
||||
current_input_tlast = 1'b0;
|
||||
current_input_tuser = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
{% for p in ports %}
|
||||
input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_reg & ~input_{{p}}_eth_hdr_valid;
|
||||
{%- endfor %}
|
||||
{% for p in ports %}
|
||||
input_{{p}}_eth_payload_tready_next = 1'b0;
|
||||
{%- endfor %}
|
||||
|
||||
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
|
||||
output_eth_dest_mac_next = output_eth_dest_mac_reg;
|
||||
output_eth_src_mac_next = output_eth_src_mac_reg;
|
||||
output_eth_type_next = output_eth_type_reg;
|
||||
|
||||
if (current_input_tvalid & current_input_tready) begin
|
||||
// end of frame detection
|
||||
if (current_input_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (~frame_reg & enable & ~output_eth_hdr_valid & selected_input_eth_hdr_valid) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
|
||||
case (select_next)
|
||||
{%- for p in ports %}
|
||||
{{w}}'d{{p}}: input_{{p}}_eth_hdr_ready_next = 1'b1;
|
||||
{%- endfor %}
|
||||
endcase
|
||||
|
||||
output_eth_hdr_valid_next = 1'b1;
|
||||
output_eth_dest_mac_next = selected_input_eth_dest_mac;
|
||||
output_eth_src_mac_next = selected_input_eth_src_mac;
|
||||
output_eth_type_next = selected_input_eth_type;
|
||||
end
|
||||
|
||||
// generate ready signal on selected port
|
||||
case (select_next)
|
||||
{%- for p in ports %}
|
||||
{{w}}'d{{p}}: input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
{%- endfor %}
|
||||
endcase
|
||||
|
||||
// pass through selected packet data
|
||||
output_eth_payload_tdata_int = current_input_tdata;
|
||||
output_eth_payload_tkeep_int = current_input_tkeep;
|
||||
output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
|
||||
output_eth_payload_tlast_int = current_input_tlast;
|
||||
output_eth_payload_tuser_int = current_input_tuser;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
select_reg <= {{w}}'d0;
|
||||
frame_reg <= 1'b0;
|
||||
{%- for p in ports %}
|
||||
input_{{p}}_eth_hdr_ready_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
{%- for p in ports %}
|
||||
input_{{p}}_eth_payload_tready_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
output_eth_hdr_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
{%- for p in ports %}
|
||||
input_{{p}}_eth_hdr_ready_reg <= input_{{p}}_eth_hdr_ready_next;
|
||||
{%- endfor %}
|
||||
{%- for p in ports %}
|
||||
input_{{p}}_eth_payload_tready_reg <= input_{{p}}_eth_payload_tready_next;
|
||||
{%- endfor %}
|
||||
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
|
||||
end
|
||||
|
||||
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
|
||||
output_eth_src_mac_reg <= output_eth_src_mac_next;
|
||||
output_eth_type_reg <= output_eth_type_next;
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [63:0] output_eth_payload_tdata_reg = 64'd0;
|
||||
reg [7:0] output_eth_payload_tkeep_reg = 8'd0;
|
||||
reg output_eth_payload_tvalid_reg = 1'b0, output_eth_payload_tvalid_next;
|
||||
reg output_eth_payload_tlast_reg = 1'b0;
|
||||
reg output_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
reg [63:0] temp_eth_payload_tdata_reg = 64'd0;
|
||||
reg [7:0] temp_eth_payload_tkeep_reg = 8'd0;
|
||||
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
|
||||
reg temp_eth_payload_tlast_reg = 1'b0;
|
||||
reg temp_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_eth_payload_int_to_output;
|
||||
reg store_eth_payload_int_to_temp;
|
||||
reg store_eth_payload_temp_to_output;
|
||||
|
||||
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
|
||||
assign output_eth_payload_tkeep = output_eth_payload_tkeep_reg;
|
||||
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
|
||||
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
|
||||
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & (~output_eth_payload_tvalid_reg | ~output_eth_payload_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
|
||||
store_eth_payload_int_to_output = 1'b0;
|
||||
store_eth_payload_int_to_temp = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b0;
|
||||
|
||||
if (output_eth_payload_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (output_eth_payload_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
output_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
output_eth_payload_tvalid_reg <= 1'b0;
|
||||
output_eth_payload_tready_int_reg <= 1'b0;
|
||||
temp_eth_payload_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_next;
|
||||
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
|
||||
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_eth_payload_int_to_output) begin
|
||||
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
|
||||
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end else if (store_eth_payload_temp_to_output) begin
|
||||
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
|
||||
output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg;
|
||||
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
|
||||
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_eth_payload_int_to_temp) begin
|
||||
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
|
||||
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
""")
|
||||
|
||||
output_file.write(t.render(
|
||||
n=ports,
|
||||
w=select_width,
|
||||
name=name,
|
||||
ports=range(ports)
|
||||
))
|
||||
|
||||
print("Done")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
||||
@ -1,347 +0,0 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Ethernet 2 port multiplexer (64 bit datapath)
|
||||
*/
|
||||
module eth_mux_64_2
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame inputs
|
||||
*/
|
||||
input wire input_0_eth_hdr_valid,
|
||||
output wire input_0_eth_hdr_ready,
|
||||
input wire [47:0] input_0_eth_dest_mac,
|
||||
input wire [47:0] input_0_eth_src_mac,
|
||||
input wire [15:0] input_0_eth_type,
|
||||
input wire [63:0] input_0_eth_payload_tdata,
|
||||
input wire [7:0] input_0_eth_payload_tkeep,
|
||||
input wire input_0_eth_payload_tvalid,
|
||||
output wire input_0_eth_payload_tready,
|
||||
input wire input_0_eth_payload_tlast,
|
||||
input wire input_0_eth_payload_tuser,
|
||||
|
||||
input wire input_1_eth_hdr_valid,
|
||||
output wire input_1_eth_hdr_ready,
|
||||
input wire [47:0] input_1_eth_dest_mac,
|
||||
input wire [47:0] input_1_eth_src_mac,
|
||||
input wire [15:0] input_1_eth_type,
|
||||
input wire [63:0] input_1_eth_payload_tdata,
|
||||
input wire [7:0] input_1_eth_payload_tkeep,
|
||||
input wire input_1_eth_payload_tvalid,
|
||||
output wire input_1_eth_payload_tready,
|
||||
input wire input_1_eth_payload_tlast,
|
||||
input wire input_1_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire output_eth_hdr_valid,
|
||||
input wire output_eth_hdr_ready,
|
||||
output wire [47:0] output_eth_dest_mac,
|
||||
output wire [47:0] output_eth_src_mac,
|
||||
output wire [15:0] output_eth_type,
|
||||
output wire [63:0] output_eth_payload_tdata,
|
||||
output wire [7:0] output_eth_payload_tkeep,
|
||||
output wire output_eth_payload_tvalid,
|
||||
input wire output_eth_payload_tready,
|
||||
output wire output_eth_payload_tlast,
|
||||
output wire output_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable,
|
||||
input wire [0:0] select
|
||||
);
|
||||
|
||||
reg [0:0] select_reg = 1'd0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
|
||||
reg input_0_eth_hdr_ready_reg = 1'b0, input_0_eth_hdr_ready_next;
|
||||
reg input_1_eth_hdr_ready_reg = 1'b0, input_1_eth_hdr_ready_next;
|
||||
|
||||
reg input_0_eth_payload_tready_reg = 1'b0, input_0_eth_payload_tready_next;
|
||||
reg input_1_eth_payload_tready_reg = 1'b0, input_1_eth_payload_tready_next;
|
||||
|
||||
reg output_eth_hdr_valid_reg = 1'b0, output_eth_hdr_valid_next;
|
||||
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
|
||||
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
|
||||
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
|
||||
|
||||
// internal datapath
|
||||
reg [63:0] output_eth_payload_tdata_int;
|
||||
reg [7:0] output_eth_payload_tkeep_int;
|
||||
reg output_eth_payload_tvalid_int;
|
||||
reg output_eth_payload_tready_int_reg = 1'b0;
|
||||
reg output_eth_payload_tlast_int;
|
||||
reg output_eth_payload_tuser_int;
|
||||
wire output_eth_payload_tready_int_early;
|
||||
|
||||
assign input_0_eth_hdr_ready = input_0_eth_hdr_ready_reg;
|
||||
assign input_1_eth_hdr_ready = input_1_eth_hdr_ready_reg;
|
||||
|
||||
assign input_0_eth_payload_tready = input_0_eth_payload_tready_reg;
|
||||
assign input_1_eth_payload_tready = input_1_eth_payload_tready_reg;
|
||||
|
||||
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
|
||||
assign output_eth_dest_mac = output_eth_dest_mac_reg;
|
||||
assign output_eth_src_mac = output_eth_src_mac_reg;
|
||||
assign output_eth_type = output_eth_type_reg;
|
||||
|
||||
// mux for start of packet detection
|
||||
reg selected_input_eth_hdr_valid;
|
||||
reg [47:0] selected_input_eth_dest_mac;
|
||||
reg [47:0] selected_input_eth_src_mac;
|
||||
reg [15:0] selected_input_eth_type;
|
||||
always @* begin
|
||||
case (select)
|
||||
1'd0: begin
|
||||
selected_input_eth_hdr_valid = input_0_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_0_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_0_eth_src_mac;
|
||||
selected_input_eth_type = input_0_eth_type;
|
||||
end
|
||||
1'd1: begin
|
||||
selected_input_eth_hdr_valid = input_1_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_1_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_1_eth_src_mac;
|
||||
selected_input_eth_type = input_1_eth_type;
|
||||
end
|
||||
default: begin
|
||||
selected_input_eth_hdr_valid = 1'b0;
|
||||
selected_input_eth_dest_mac = 48'd0;
|
||||
selected_input_eth_src_mac = 48'd0;
|
||||
selected_input_eth_type = 16'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// mux for incoming packet
|
||||
reg [63:0] current_input_tdata;
|
||||
reg [7:0] current_input_tkeep;
|
||||
reg current_input_tvalid;
|
||||
reg current_input_tready;
|
||||
reg current_input_tlast;
|
||||
reg current_input_tuser;
|
||||
always @* begin
|
||||
case (select_reg)
|
||||
1'd0: begin
|
||||
current_input_tdata = input_0_eth_payload_tdata;
|
||||
current_input_tkeep = input_0_eth_payload_tkeep;
|
||||
current_input_tvalid = input_0_eth_payload_tvalid;
|
||||
current_input_tready = input_0_eth_payload_tready;
|
||||
current_input_tlast = input_0_eth_payload_tlast;
|
||||
current_input_tuser = input_0_eth_payload_tuser;
|
||||
end
|
||||
1'd1: begin
|
||||
current_input_tdata = input_1_eth_payload_tdata;
|
||||
current_input_tkeep = input_1_eth_payload_tkeep;
|
||||
current_input_tvalid = input_1_eth_payload_tvalid;
|
||||
current_input_tready = input_1_eth_payload_tready;
|
||||
current_input_tlast = input_1_eth_payload_tlast;
|
||||
current_input_tuser = input_1_eth_payload_tuser;
|
||||
end
|
||||
default: begin
|
||||
current_input_tdata = 64'd0;
|
||||
current_input_tkeep = 8'd0;
|
||||
current_input_tvalid = 1'b0;
|
||||
current_input_tready = 1'b0;
|
||||
current_input_tlast = 1'b0;
|
||||
current_input_tuser = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
|
||||
input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_reg & ~input_0_eth_hdr_valid;
|
||||
input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_reg & ~input_1_eth_hdr_valid;
|
||||
|
||||
input_0_eth_payload_tready_next = 1'b0;
|
||||
input_1_eth_payload_tready_next = 1'b0;
|
||||
|
||||
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
|
||||
output_eth_dest_mac_next = output_eth_dest_mac_reg;
|
||||
output_eth_src_mac_next = output_eth_src_mac_reg;
|
||||
output_eth_type_next = output_eth_type_reg;
|
||||
|
||||
if (current_input_tvalid & current_input_tready) begin
|
||||
// end of frame detection
|
||||
if (current_input_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (~frame_reg & enable & ~output_eth_hdr_valid & selected_input_eth_hdr_valid) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
|
||||
case (select_next)
|
||||
1'd0: input_0_eth_hdr_ready_next = 1'b1;
|
||||
1'd1: input_1_eth_hdr_ready_next = 1'b1;
|
||||
endcase
|
||||
|
||||
output_eth_hdr_valid_next = 1'b1;
|
||||
output_eth_dest_mac_next = selected_input_eth_dest_mac;
|
||||
output_eth_src_mac_next = selected_input_eth_src_mac;
|
||||
output_eth_type_next = selected_input_eth_type;
|
||||
end
|
||||
|
||||
// generate ready signal on selected port
|
||||
case (select_next)
|
||||
1'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
1'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
endcase
|
||||
|
||||
// pass through selected packet data
|
||||
output_eth_payload_tdata_int = current_input_tdata;
|
||||
output_eth_payload_tkeep_int = current_input_tkeep;
|
||||
output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
|
||||
output_eth_payload_tlast_int = current_input_tlast;
|
||||
output_eth_payload_tuser_int = current_input_tuser;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
select_reg <= 1'd0;
|
||||
frame_reg <= 1'b0;
|
||||
input_0_eth_hdr_ready_reg <= 1'b0;
|
||||
input_1_eth_hdr_ready_reg <= 1'b0;
|
||||
input_0_eth_payload_tready_reg <= 1'b0;
|
||||
input_1_eth_payload_tready_reg <= 1'b0;
|
||||
output_eth_hdr_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
input_0_eth_hdr_ready_reg <= input_0_eth_hdr_ready_next;
|
||||
input_1_eth_hdr_ready_reg <= input_1_eth_hdr_ready_next;
|
||||
input_0_eth_payload_tready_reg <= input_0_eth_payload_tready_next;
|
||||
input_1_eth_payload_tready_reg <= input_1_eth_payload_tready_next;
|
||||
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
|
||||
end
|
||||
|
||||
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
|
||||
output_eth_src_mac_reg <= output_eth_src_mac_next;
|
||||
output_eth_type_reg <= output_eth_type_next;
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [63:0] output_eth_payload_tdata_reg = 64'd0;
|
||||
reg [7:0] output_eth_payload_tkeep_reg = 8'd0;
|
||||
reg output_eth_payload_tvalid_reg = 1'b0, output_eth_payload_tvalid_next;
|
||||
reg output_eth_payload_tlast_reg = 1'b0;
|
||||
reg output_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
reg [63:0] temp_eth_payload_tdata_reg = 64'd0;
|
||||
reg [7:0] temp_eth_payload_tkeep_reg = 8'd0;
|
||||
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
|
||||
reg temp_eth_payload_tlast_reg = 1'b0;
|
||||
reg temp_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_eth_payload_int_to_output;
|
||||
reg store_eth_payload_int_to_temp;
|
||||
reg store_eth_payload_temp_to_output;
|
||||
|
||||
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
|
||||
assign output_eth_payload_tkeep = output_eth_payload_tkeep_reg;
|
||||
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
|
||||
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
|
||||
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & (~output_eth_payload_tvalid_reg | ~output_eth_payload_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
|
||||
store_eth_payload_int_to_output = 1'b0;
|
||||
store_eth_payload_int_to_temp = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b0;
|
||||
|
||||
if (output_eth_payload_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (output_eth_payload_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
output_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
output_eth_payload_tvalid_reg <= 1'b0;
|
||||
output_eth_payload_tready_int_reg <= 1'b0;
|
||||
temp_eth_payload_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_next;
|
||||
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
|
||||
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_eth_payload_int_to_output) begin
|
||||
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
|
||||
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end else if (store_eth_payload_temp_to_output) begin
|
||||
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
|
||||
output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg;
|
||||
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
|
||||
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_eth_payload_int_to_temp) begin
|
||||
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
|
||||
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,423 +0,0 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Ethernet 4 port multiplexer (64 bit datapath)
|
||||
*/
|
||||
module eth_mux_64_4
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame inputs
|
||||
*/
|
||||
input wire input_0_eth_hdr_valid,
|
||||
output wire input_0_eth_hdr_ready,
|
||||
input wire [47:0] input_0_eth_dest_mac,
|
||||
input wire [47:0] input_0_eth_src_mac,
|
||||
input wire [15:0] input_0_eth_type,
|
||||
input wire [63:0] input_0_eth_payload_tdata,
|
||||
input wire [7:0] input_0_eth_payload_tkeep,
|
||||
input wire input_0_eth_payload_tvalid,
|
||||
output wire input_0_eth_payload_tready,
|
||||
input wire input_0_eth_payload_tlast,
|
||||
input wire input_0_eth_payload_tuser,
|
||||
|
||||
input wire input_1_eth_hdr_valid,
|
||||
output wire input_1_eth_hdr_ready,
|
||||
input wire [47:0] input_1_eth_dest_mac,
|
||||
input wire [47:0] input_1_eth_src_mac,
|
||||
input wire [15:0] input_1_eth_type,
|
||||
input wire [63:0] input_1_eth_payload_tdata,
|
||||
input wire [7:0] input_1_eth_payload_tkeep,
|
||||
input wire input_1_eth_payload_tvalid,
|
||||
output wire input_1_eth_payload_tready,
|
||||
input wire input_1_eth_payload_tlast,
|
||||
input wire input_1_eth_payload_tuser,
|
||||
|
||||
input wire input_2_eth_hdr_valid,
|
||||
output wire input_2_eth_hdr_ready,
|
||||
input wire [47:0] input_2_eth_dest_mac,
|
||||
input wire [47:0] input_2_eth_src_mac,
|
||||
input wire [15:0] input_2_eth_type,
|
||||
input wire [63:0] input_2_eth_payload_tdata,
|
||||
input wire [7:0] input_2_eth_payload_tkeep,
|
||||
input wire input_2_eth_payload_tvalid,
|
||||
output wire input_2_eth_payload_tready,
|
||||
input wire input_2_eth_payload_tlast,
|
||||
input wire input_2_eth_payload_tuser,
|
||||
|
||||
input wire input_3_eth_hdr_valid,
|
||||
output wire input_3_eth_hdr_ready,
|
||||
input wire [47:0] input_3_eth_dest_mac,
|
||||
input wire [47:0] input_3_eth_src_mac,
|
||||
input wire [15:0] input_3_eth_type,
|
||||
input wire [63:0] input_3_eth_payload_tdata,
|
||||
input wire [7:0] input_3_eth_payload_tkeep,
|
||||
input wire input_3_eth_payload_tvalid,
|
||||
output wire input_3_eth_payload_tready,
|
||||
input wire input_3_eth_payload_tlast,
|
||||
input wire input_3_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire output_eth_hdr_valid,
|
||||
input wire output_eth_hdr_ready,
|
||||
output wire [47:0] output_eth_dest_mac,
|
||||
output wire [47:0] output_eth_src_mac,
|
||||
output wire [15:0] output_eth_type,
|
||||
output wire [63:0] output_eth_payload_tdata,
|
||||
output wire [7:0] output_eth_payload_tkeep,
|
||||
output wire output_eth_payload_tvalid,
|
||||
input wire output_eth_payload_tready,
|
||||
output wire output_eth_payload_tlast,
|
||||
output wire output_eth_payload_tuser,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable,
|
||||
input wire [1:0] select
|
||||
);
|
||||
|
||||
reg [1:0] select_reg = 2'd0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
|
||||
reg input_0_eth_hdr_ready_reg = 1'b0, input_0_eth_hdr_ready_next;
|
||||
reg input_1_eth_hdr_ready_reg = 1'b0, input_1_eth_hdr_ready_next;
|
||||
reg input_2_eth_hdr_ready_reg = 1'b0, input_2_eth_hdr_ready_next;
|
||||
reg input_3_eth_hdr_ready_reg = 1'b0, input_3_eth_hdr_ready_next;
|
||||
|
||||
reg input_0_eth_payload_tready_reg = 1'b0, input_0_eth_payload_tready_next;
|
||||
reg input_1_eth_payload_tready_reg = 1'b0, input_1_eth_payload_tready_next;
|
||||
reg input_2_eth_payload_tready_reg = 1'b0, input_2_eth_payload_tready_next;
|
||||
reg input_3_eth_payload_tready_reg = 1'b0, input_3_eth_payload_tready_next;
|
||||
|
||||
reg output_eth_hdr_valid_reg = 1'b0, output_eth_hdr_valid_next;
|
||||
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
|
||||
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
|
||||
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
|
||||
|
||||
// internal datapath
|
||||
reg [63:0] output_eth_payload_tdata_int;
|
||||
reg [7:0] output_eth_payload_tkeep_int;
|
||||
reg output_eth_payload_tvalid_int;
|
||||
reg output_eth_payload_tready_int_reg = 1'b0;
|
||||
reg output_eth_payload_tlast_int;
|
||||
reg output_eth_payload_tuser_int;
|
||||
wire output_eth_payload_tready_int_early;
|
||||
|
||||
assign input_0_eth_hdr_ready = input_0_eth_hdr_ready_reg;
|
||||
assign input_1_eth_hdr_ready = input_1_eth_hdr_ready_reg;
|
||||
assign input_2_eth_hdr_ready = input_2_eth_hdr_ready_reg;
|
||||
assign input_3_eth_hdr_ready = input_3_eth_hdr_ready_reg;
|
||||
|
||||
assign input_0_eth_payload_tready = input_0_eth_payload_tready_reg;
|
||||
assign input_1_eth_payload_tready = input_1_eth_payload_tready_reg;
|
||||
assign input_2_eth_payload_tready = input_2_eth_payload_tready_reg;
|
||||
assign input_3_eth_payload_tready = input_3_eth_payload_tready_reg;
|
||||
|
||||
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
|
||||
assign output_eth_dest_mac = output_eth_dest_mac_reg;
|
||||
assign output_eth_src_mac = output_eth_src_mac_reg;
|
||||
assign output_eth_type = output_eth_type_reg;
|
||||
|
||||
// mux for start of packet detection
|
||||
reg selected_input_eth_hdr_valid;
|
||||
reg [47:0] selected_input_eth_dest_mac;
|
||||
reg [47:0] selected_input_eth_src_mac;
|
||||
reg [15:0] selected_input_eth_type;
|
||||
always @* begin
|
||||
case (select)
|
||||
2'd0: begin
|
||||
selected_input_eth_hdr_valid = input_0_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_0_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_0_eth_src_mac;
|
||||
selected_input_eth_type = input_0_eth_type;
|
||||
end
|
||||
2'd1: begin
|
||||
selected_input_eth_hdr_valid = input_1_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_1_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_1_eth_src_mac;
|
||||
selected_input_eth_type = input_1_eth_type;
|
||||
end
|
||||
2'd2: begin
|
||||
selected_input_eth_hdr_valid = input_2_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_2_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_2_eth_src_mac;
|
||||
selected_input_eth_type = input_2_eth_type;
|
||||
end
|
||||
2'd3: begin
|
||||
selected_input_eth_hdr_valid = input_3_eth_hdr_valid;
|
||||
selected_input_eth_dest_mac = input_3_eth_dest_mac;
|
||||
selected_input_eth_src_mac = input_3_eth_src_mac;
|
||||
selected_input_eth_type = input_3_eth_type;
|
||||
end
|
||||
default: begin
|
||||
selected_input_eth_hdr_valid = 1'b0;
|
||||
selected_input_eth_dest_mac = 48'd0;
|
||||
selected_input_eth_src_mac = 48'd0;
|
||||
selected_input_eth_type = 16'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// mux for incoming packet
|
||||
reg [63:0] current_input_tdata;
|
||||
reg [7:0] current_input_tkeep;
|
||||
reg current_input_tvalid;
|
||||
reg current_input_tready;
|
||||
reg current_input_tlast;
|
||||
reg current_input_tuser;
|
||||
always @* begin
|
||||
case (select_reg)
|
||||
2'd0: begin
|
||||
current_input_tdata = input_0_eth_payload_tdata;
|
||||
current_input_tkeep = input_0_eth_payload_tkeep;
|
||||
current_input_tvalid = input_0_eth_payload_tvalid;
|
||||
current_input_tready = input_0_eth_payload_tready;
|
||||
current_input_tlast = input_0_eth_payload_tlast;
|
||||
current_input_tuser = input_0_eth_payload_tuser;
|
||||
end
|
||||
2'd1: begin
|
||||
current_input_tdata = input_1_eth_payload_tdata;
|
||||
current_input_tkeep = input_1_eth_payload_tkeep;
|
||||
current_input_tvalid = input_1_eth_payload_tvalid;
|
||||
current_input_tready = input_1_eth_payload_tready;
|
||||
current_input_tlast = input_1_eth_payload_tlast;
|
||||
current_input_tuser = input_1_eth_payload_tuser;
|
||||
end
|
||||
2'd2: begin
|
||||
current_input_tdata = input_2_eth_payload_tdata;
|
||||
current_input_tkeep = input_2_eth_payload_tkeep;
|
||||
current_input_tvalid = input_2_eth_payload_tvalid;
|
||||
current_input_tready = input_2_eth_payload_tready;
|
||||
current_input_tlast = input_2_eth_payload_tlast;
|
||||
current_input_tuser = input_2_eth_payload_tuser;
|
||||
end
|
||||
2'd3: begin
|
||||
current_input_tdata = input_3_eth_payload_tdata;
|
||||
current_input_tkeep = input_3_eth_payload_tkeep;
|
||||
current_input_tvalid = input_3_eth_payload_tvalid;
|
||||
current_input_tready = input_3_eth_payload_tready;
|
||||
current_input_tlast = input_3_eth_payload_tlast;
|
||||
current_input_tuser = input_3_eth_payload_tuser;
|
||||
end
|
||||
default: begin
|
||||
current_input_tdata = 64'd0;
|
||||
current_input_tkeep = 8'd0;
|
||||
current_input_tvalid = 1'b0;
|
||||
current_input_tready = 1'b0;
|
||||
current_input_tlast = 1'b0;
|
||||
current_input_tuser = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
|
||||
input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_reg & ~input_0_eth_hdr_valid;
|
||||
input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_reg & ~input_1_eth_hdr_valid;
|
||||
input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_reg & ~input_2_eth_hdr_valid;
|
||||
input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_reg & ~input_3_eth_hdr_valid;
|
||||
|
||||
input_0_eth_payload_tready_next = 1'b0;
|
||||
input_1_eth_payload_tready_next = 1'b0;
|
||||
input_2_eth_payload_tready_next = 1'b0;
|
||||
input_3_eth_payload_tready_next = 1'b0;
|
||||
|
||||
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
|
||||
output_eth_dest_mac_next = output_eth_dest_mac_reg;
|
||||
output_eth_src_mac_next = output_eth_src_mac_reg;
|
||||
output_eth_type_next = output_eth_type_reg;
|
||||
|
||||
if (current_input_tvalid & current_input_tready) begin
|
||||
// end of frame detection
|
||||
if (current_input_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (~frame_reg & enable & ~output_eth_hdr_valid & selected_input_eth_hdr_valid) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
|
||||
case (select_next)
|
||||
2'd0: input_0_eth_hdr_ready_next = 1'b1;
|
||||
2'd1: input_1_eth_hdr_ready_next = 1'b1;
|
||||
2'd2: input_2_eth_hdr_ready_next = 1'b1;
|
||||
2'd3: input_3_eth_hdr_ready_next = 1'b1;
|
||||
endcase
|
||||
|
||||
output_eth_hdr_valid_next = 1'b1;
|
||||
output_eth_dest_mac_next = selected_input_eth_dest_mac;
|
||||
output_eth_src_mac_next = selected_input_eth_src_mac;
|
||||
output_eth_type_next = selected_input_eth_type;
|
||||
end
|
||||
|
||||
// generate ready signal on selected port
|
||||
case (select_next)
|
||||
2'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
2'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
2'd2: input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
2'd3: input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
|
||||
endcase
|
||||
|
||||
// pass through selected packet data
|
||||
output_eth_payload_tdata_int = current_input_tdata;
|
||||
output_eth_payload_tkeep_int = current_input_tkeep;
|
||||
output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
|
||||
output_eth_payload_tlast_int = current_input_tlast;
|
||||
output_eth_payload_tuser_int = current_input_tuser;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
select_reg <= 2'd0;
|
||||
frame_reg <= 1'b0;
|
||||
input_0_eth_hdr_ready_reg <= 1'b0;
|
||||
input_1_eth_hdr_ready_reg <= 1'b0;
|
||||
input_2_eth_hdr_ready_reg <= 1'b0;
|
||||
input_3_eth_hdr_ready_reg <= 1'b0;
|
||||
input_0_eth_payload_tready_reg <= 1'b0;
|
||||
input_1_eth_payload_tready_reg <= 1'b0;
|
||||
input_2_eth_payload_tready_reg <= 1'b0;
|
||||
input_3_eth_payload_tready_reg <= 1'b0;
|
||||
output_eth_hdr_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
input_0_eth_hdr_ready_reg <= input_0_eth_hdr_ready_next;
|
||||
input_1_eth_hdr_ready_reg <= input_1_eth_hdr_ready_next;
|
||||
input_2_eth_hdr_ready_reg <= input_2_eth_hdr_ready_next;
|
||||
input_3_eth_hdr_ready_reg <= input_3_eth_hdr_ready_next;
|
||||
input_0_eth_payload_tready_reg <= input_0_eth_payload_tready_next;
|
||||
input_1_eth_payload_tready_reg <= input_1_eth_payload_tready_next;
|
||||
input_2_eth_payload_tready_reg <= input_2_eth_payload_tready_next;
|
||||
input_3_eth_payload_tready_reg <= input_3_eth_payload_tready_next;
|
||||
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
|
||||
end
|
||||
|
||||
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
|
||||
output_eth_src_mac_reg <= output_eth_src_mac_next;
|
||||
output_eth_type_reg <= output_eth_type_next;
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [63:0] output_eth_payload_tdata_reg = 64'd0;
|
||||
reg [7:0] output_eth_payload_tkeep_reg = 8'd0;
|
||||
reg output_eth_payload_tvalid_reg = 1'b0, output_eth_payload_tvalid_next;
|
||||
reg output_eth_payload_tlast_reg = 1'b0;
|
||||
reg output_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
reg [63:0] temp_eth_payload_tdata_reg = 64'd0;
|
||||
reg [7:0] temp_eth_payload_tkeep_reg = 8'd0;
|
||||
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
|
||||
reg temp_eth_payload_tlast_reg = 1'b0;
|
||||
reg temp_eth_payload_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_eth_payload_int_to_output;
|
||||
reg store_eth_payload_int_to_temp;
|
||||
reg store_eth_payload_temp_to_output;
|
||||
|
||||
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
|
||||
assign output_eth_payload_tkeep = output_eth_payload_tkeep_reg;
|
||||
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
|
||||
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
|
||||
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & (~output_eth_payload_tvalid_reg | ~output_eth_payload_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
|
||||
store_eth_payload_int_to_output = 1'b0;
|
||||
store_eth_payload_int_to_temp = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b0;
|
||||
|
||||
if (output_eth_payload_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
output_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
|
||||
store_eth_payload_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (output_eth_payload_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
output_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
|
||||
temp_eth_payload_tvalid_next = 1'b0;
|
||||
store_eth_payload_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
output_eth_payload_tvalid_reg <= 1'b0;
|
||||
output_eth_payload_tready_int_reg <= 1'b0;
|
||||
temp_eth_payload_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_next;
|
||||
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
|
||||
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_eth_payload_int_to_output) begin
|
||||
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
|
||||
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end else if (store_eth_payload_temp_to_output) begin
|
||||
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
|
||||
output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg;
|
||||
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
|
||||
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_eth_payload_int_to_temp) begin
|
||||
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
|
||||
temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
|
||||
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
|
||||
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -28,8 +28,8 @@ import os
|
||||
|
||||
import eth_ep
|
||||
|
||||
module = 'eth_mux_4'
|
||||
testbench = 'test_%s' % module
|
||||
module = 'eth_mux'
|
||||
testbench = 'test_%s_4' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
@ -42,167 +42,119 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
S_COUNT = 4
|
||||
DATA_WIDTH = 8
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
ID_ENABLE = 1
|
||||
ID_WIDTH = 8
|
||||
DEST_ENABLE = 1
|
||||
DEST_WIDTH = 8
|
||||
USER_ENABLE = 1
|
||||
USER_WIDTH = 1
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_0_eth_hdr_valid = Signal(bool(0))
|
||||
input_0_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
input_0_eth_src_mac = Signal(intbv(0)[48:])
|
||||
input_0_eth_type = Signal(intbv(0)[16:])
|
||||
input_0_eth_payload_tdata = Signal(intbv(0)[8:])
|
||||
input_0_eth_payload_tvalid = Signal(bool(0))
|
||||
input_0_eth_payload_tlast = Signal(bool(0))
|
||||
input_0_eth_payload_tuser = Signal(bool(0))
|
||||
input_1_eth_hdr_valid = Signal(bool(0))
|
||||
input_1_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
input_1_eth_src_mac = Signal(intbv(0)[48:])
|
||||
input_1_eth_type = Signal(intbv(0)[16:])
|
||||
input_1_eth_payload_tdata = Signal(intbv(0)[8:])
|
||||
input_1_eth_payload_tvalid = Signal(bool(0))
|
||||
input_1_eth_payload_tlast = Signal(bool(0))
|
||||
input_1_eth_payload_tuser = Signal(bool(0))
|
||||
input_2_eth_hdr_valid = Signal(bool(0))
|
||||
input_2_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
input_2_eth_src_mac = Signal(intbv(0)[48:])
|
||||
input_2_eth_type = Signal(intbv(0)[16:])
|
||||
input_2_eth_payload_tdata = Signal(intbv(0)[8:])
|
||||
input_2_eth_payload_tvalid = Signal(bool(0))
|
||||
input_2_eth_payload_tlast = Signal(bool(0))
|
||||
input_2_eth_payload_tuser = Signal(bool(0))
|
||||
input_3_eth_hdr_valid = Signal(bool(0))
|
||||
input_3_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
input_3_eth_src_mac = Signal(intbv(0)[48:])
|
||||
input_3_eth_type = Signal(intbv(0)[16:])
|
||||
input_3_eth_payload_tdata = Signal(intbv(0)[8:])
|
||||
input_3_eth_payload_tvalid = Signal(bool(0))
|
||||
input_3_eth_payload_tlast = Signal(bool(0))
|
||||
input_3_eth_payload_tuser = Signal(bool(0))
|
||||
s_eth_hdr_valid_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_eth_dest_mac_list = [Signal(intbv(0)[48:]) for i in range(S_COUNT)]
|
||||
s_eth_src_mac_list = [Signal(intbv(0)[48:]) for i in range(S_COUNT)]
|
||||
s_eth_type_list = [Signal(intbv(0)[16:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tkeep_list = [Signal(intbv(1)[KEEP_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tlast_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tdest_list = [Signal(intbv(0)[DEST_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tuser_list = [Signal(intbv(0)[USER_WIDTH:]) for i in range(S_COUNT)]
|
||||
|
||||
output_eth_payload_tready = Signal(bool(0))
|
||||
output_eth_hdr_ready = Signal(bool(0))
|
||||
s_eth_hdr_valid = ConcatSignal(*reversed(s_eth_hdr_valid_list))
|
||||
s_eth_dest_mac = ConcatSignal(*reversed(s_eth_dest_mac_list))
|
||||
s_eth_src_mac = ConcatSignal(*reversed(s_eth_src_mac_list))
|
||||
s_eth_type = ConcatSignal(*reversed(s_eth_type_list))
|
||||
s_eth_payload_axis_tdata = ConcatSignal(*reversed(s_eth_payload_axis_tdata_list))
|
||||
s_eth_payload_axis_tkeep = ConcatSignal(*reversed(s_eth_payload_axis_tkeep_list))
|
||||
s_eth_payload_axis_tvalid = ConcatSignal(*reversed(s_eth_payload_axis_tvalid_list))
|
||||
s_eth_payload_axis_tlast = ConcatSignal(*reversed(s_eth_payload_axis_tlast_list))
|
||||
s_eth_payload_axis_tid = ConcatSignal(*reversed(s_eth_payload_axis_tid_list))
|
||||
s_eth_payload_axis_tdest = ConcatSignal(*reversed(s_eth_payload_axis_tdest_list))
|
||||
s_eth_payload_axis_tuser = ConcatSignal(*reversed(s_eth_payload_axis_tuser_list))
|
||||
|
||||
m_eth_hdr_ready = Signal(bool(0))
|
||||
m_eth_payload_axis_tready = Signal(bool(0))
|
||||
|
||||
enable = Signal(bool(0))
|
||||
select = Signal(intbv(0)[2:])
|
||||
|
||||
# Outputs
|
||||
input_0_eth_hdr_ready = Signal(bool(0))
|
||||
input_0_eth_payload_tready = Signal(bool(0))
|
||||
input_1_eth_hdr_ready = Signal(bool(0))
|
||||
input_1_eth_payload_tready = Signal(bool(0))
|
||||
input_2_eth_hdr_ready = Signal(bool(0))
|
||||
input_2_eth_payload_tready = Signal(bool(0))
|
||||
input_3_eth_hdr_ready = Signal(bool(0))
|
||||
input_3_eth_payload_tready = Signal(bool(0))
|
||||
s_eth_hdr_ready = Signal(intbv(0)[S_COUNT:])
|
||||
s_eth_payload_axis_tready = Signal(intbv(0)[S_COUNT:])
|
||||
|
||||
output_eth_hdr_valid = Signal(bool(0))
|
||||
output_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
output_eth_src_mac = Signal(intbv(0)[48:])
|
||||
output_eth_type = Signal(intbv(0)[16:])
|
||||
output_eth_payload_tdata = Signal(intbv(0)[8:])
|
||||
output_eth_payload_tvalid = Signal(bool(0))
|
||||
output_eth_payload_tlast = Signal(bool(0))
|
||||
output_eth_payload_tuser = Signal(bool(0))
|
||||
s_eth_hdr_ready_list = [s_eth_hdr_ready(i) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tready_list = [s_eth_payload_axis_tready(i) for i in range(S_COUNT)]
|
||||
|
||||
m_eth_hdr_valid = Signal(bool(0))
|
||||
m_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
m_eth_src_mac = Signal(intbv(0)[48:])
|
||||
m_eth_type = Signal(intbv(0)[16:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
m_eth_payload_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
m_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
m_eth_payload_axis_tlast = Signal(bool(0))
|
||||
m_eth_payload_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
m_eth_payload_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
m_eth_payload_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
|
||||
# sources and sinks
|
||||
source_0_pause = Signal(bool(0))
|
||||
source_1_pause = Signal(bool(0))
|
||||
source_2_pause = Signal(bool(0))
|
||||
source_3_pause = Signal(bool(0))
|
||||
source_pause_list = []
|
||||
source_list = []
|
||||
source_logic_list = []
|
||||
sink_pause = Signal(bool(0))
|
||||
|
||||
source_0 = eth_ep.EthFrameSource()
|
||||
for k in range(S_COUNT):
|
||||
s = eth_ep.EthFrameSource()
|
||||
p = Signal(bool(0))
|
||||
|
||||
source_0_logic = source_0.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=input_0_eth_hdr_ready,
|
||||
eth_hdr_valid=input_0_eth_hdr_valid,
|
||||
eth_dest_mac=input_0_eth_dest_mac,
|
||||
eth_src_mac=input_0_eth_src_mac,
|
||||
eth_type=input_0_eth_type,
|
||||
eth_payload_tdata=input_0_eth_payload_tdata,
|
||||
eth_payload_tvalid=input_0_eth_payload_tvalid,
|
||||
eth_payload_tready=input_0_eth_payload_tready,
|
||||
eth_payload_tlast=input_0_eth_payload_tlast,
|
||||
eth_payload_tuser=input_0_eth_payload_tuser,
|
||||
pause=source_0_pause,
|
||||
name='source_0'
|
||||
)
|
||||
source_list.append(s)
|
||||
source_pause_list.append(p)
|
||||
|
||||
source_1 = eth_ep.EthFrameSource()
|
||||
|
||||
source_1_logic = source_1.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=input_1_eth_hdr_ready,
|
||||
eth_hdr_valid=input_1_eth_hdr_valid,
|
||||
eth_dest_mac=input_1_eth_dest_mac,
|
||||
eth_src_mac=input_1_eth_src_mac,
|
||||
eth_type=input_1_eth_type,
|
||||
eth_payload_tdata=input_1_eth_payload_tdata,
|
||||
eth_payload_tvalid=input_1_eth_payload_tvalid,
|
||||
eth_payload_tready=input_1_eth_payload_tready,
|
||||
eth_payload_tlast=input_1_eth_payload_tlast,
|
||||
eth_payload_tuser=input_1_eth_payload_tuser,
|
||||
pause=source_1_pause,
|
||||
name='source_1'
|
||||
)
|
||||
|
||||
source_2 = eth_ep.EthFrameSource()
|
||||
|
||||
source_2_logic = source_2.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=input_2_eth_hdr_ready,
|
||||
eth_hdr_valid=input_2_eth_hdr_valid,
|
||||
eth_dest_mac=input_2_eth_dest_mac,
|
||||
eth_src_mac=input_2_eth_src_mac,
|
||||
eth_type=input_2_eth_type,
|
||||
eth_payload_tdata=input_2_eth_payload_tdata,
|
||||
eth_payload_tvalid=input_2_eth_payload_tvalid,
|
||||
eth_payload_tready=input_2_eth_payload_tready,
|
||||
eth_payload_tlast=input_2_eth_payload_tlast,
|
||||
eth_payload_tuser=input_2_eth_payload_tuser,
|
||||
pause=source_2_pause,
|
||||
name='source_2'
|
||||
)
|
||||
|
||||
source_3 = eth_ep.EthFrameSource()
|
||||
|
||||
source_3_logic = source_3.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=input_3_eth_hdr_ready,
|
||||
eth_hdr_valid=input_3_eth_hdr_valid,
|
||||
eth_dest_mac=input_3_eth_dest_mac,
|
||||
eth_src_mac=input_3_eth_src_mac,
|
||||
eth_type=input_3_eth_type,
|
||||
eth_payload_tdata=input_3_eth_payload_tdata,
|
||||
eth_payload_tvalid=input_3_eth_payload_tvalid,
|
||||
eth_payload_tready=input_3_eth_payload_tready,
|
||||
eth_payload_tlast=input_3_eth_payload_tlast,
|
||||
eth_payload_tuser=input_3_eth_payload_tuser,
|
||||
pause=source_3_pause,
|
||||
name='source_3'
|
||||
)
|
||||
source_logic_list.append(s.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=s_eth_hdr_ready_list[k],
|
||||
eth_hdr_valid=s_eth_hdr_valid_list[k],
|
||||
eth_dest_mac=s_eth_dest_mac_list[k],
|
||||
eth_src_mac=s_eth_src_mac_list[k],
|
||||
eth_type=s_eth_type_list[k],
|
||||
eth_payload_tdata=s_eth_payload_axis_tdata_list[k],
|
||||
eth_payload_tkeep=s_eth_payload_axis_tkeep_list[k],
|
||||
eth_payload_tvalid=s_eth_payload_axis_tvalid_list[k],
|
||||
eth_payload_tready=s_eth_payload_axis_tready_list[k],
|
||||
eth_payload_tlast=s_eth_payload_axis_tlast_list[k],
|
||||
eth_payload_tuser=s_eth_payload_axis_tuser_list[k],
|
||||
pause=p,
|
||||
name='source_%d' % k
|
||||
))
|
||||
|
||||
sink = eth_ep.EthFrameSink()
|
||||
|
||||
sink_logic = sink.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=output_eth_hdr_ready,
|
||||
eth_hdr_valid=output_eth_hdr_valid,
|
||||
eth_dest_mac=output_eth_dest_mac,
|
||||
eth_src_mac=output_eth_src_mac,
|
||||
eth_type=output_eth_type,
|
||||
eth_payload_tdata=output_eth_payload_tdata,
|
||||
eth_payload_tvalid=output_eth_payload_tvalid,
|
||||
eth_payload_tready=output_eth_payload_tready,
|
||||
eth_payload_tlast=output_eth_payload_tlast,
|
||||
eth_payload_tuser=output_eth_payload_tuser,
|
||||
eth_hdr_ready=m_eth_hdr_ready,
|
||||
eth_hdr_valid=m_eth_hdr_valid,
|
||||
eth_dest_mac=m_eth_dest_mac,
|
||||
eth_src_mac=m_eth_src_mac,
|
||||
eth_type=m_eth_type,
|
||||
eth_payload_tdata=m_eth_payload_axis_tdata,
|
||||
eth_payload_tkeep=m_eth_payload_axis_tkeep,
|
||||
eth_payload_tvalid=m_eth_payload_axis_tvalid,
|
||||
eth_payload_tready=m_eth_payload_axis_tready,
|
||||
eth_payload_tlast=m_eth_payload_axis_tlast,
|
||||
eth_payload_tuser=m_eth_payload_axis_tuser,
|
||||
pause=sink_pause,
|
||||
name='sink'
|
||||
)
|
||||
@ -217,57 +169,33 @@ def bench():
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_0_eth_hdr_valid=input_0_eth_hdr_valid,
|
||||
input_0_eth_hdr_ready=input_0_eth_hdr_ready,
|
||||
input_0_eth_dest_mac=input_0_eth_dest_mac,
|
||||
input_0_eth_src_mac=input_0_eth_src_mac,
|
||||
input_0_eth_type=input_0_eth_type,
|
||||
input_0_eth_payload_tdata=input_0_eth_payload_tdata,
|
||||
input_0_eth_payload_tvalid=input_0_eth_payload_tvalid,
|
||||
input_0_eth_payload_tready=input_0_eth_payload_tready,
|
||||
input_0_eth_payload_tlast=input_0_eth_payload_tlast,
|
||||
input_0_eth_payload_tuser=input_0_eth_payload_tuser,
|
||||
input_1_eth_hdr_valid=input_1_eth_hdr_valid,
|
||||
input_1_eth_hdr_ready=input_1_eth_hdr_ready,
|
||||
input_1_eth_dest_mac=input_1_eth_dest_mac,
|
||||
input_1_eth_src_mac=input_1_eth_src_mac,
|
||||
input_1_eth_type=input_1_eth_type,
|
||||
input_1_eth_payload_tdata=input_1_eth_payload_tdata,
|
||||
input_1_eth_payload_tvalid=input_1_eth_payload_tvalid,
|
||||
input_1_eth_payload_tready=input_1_eth_payload_tready,
|
||||
input_1_eth_payload_tlast=input_1_eth_payload_tlast,
|
||||
input_1_eth_payload_tuser=input_1_eth_payload_tuser,
|
||||
input_2_eth_hdr_valid=input_2_eth_hdr_valid,
|
||||
input_2_eth_hdr_ready=input_2_eth_hdr_ready,
|
||||
input_2_eth_dest_mac=input_2_eth_dest_mac,
|
||||
input_2_eth_src_mac=input_2_eth_src_mac,
|
||||
input_2_eth_type=input_2_eth_type,
|
||||
input_2_eth_payload_tdata=input_2_eth_payload_tdata,
|
||||
input_2_eth_payload_tvalid=input_2_eth_payload_tvalid,
|
||||
input_2_eth_payload_tready=input_2_eth_payload_tready,
|
||||
input_2_eth_payload_tlast=input_2_eth_payload_tlast,
|
||||
input_2_eth_payload_tuser=input_2_eth_payload_tuser,
|
||||
input_3_eth_hdr_valid=input_3_eth_hdr_valid,
|
||||
input_3_eth_hdr_ready=input_3_eth_hdr_ready,
|
||||
input_3_eth_dest_mac=input_3_eth_dest_mac,
|
||||
input_3_eth_src_mac=input_3_eth_src_mac,
|
||||
input_3_eth_type=input_3_eth_type,
|
||||
input_3_eth_payload_tdata=input_3_eth_payload_tdata,
|
||||
input_3_eth_payload_tvalid=input_3_eth_payload_tvalid,
|
||||
input_3_eth_payload_tready=input_3_eth_payload_tready,
|
||||
input_3_eth_payload_tlast=input_3_eth_payload_tlast,
|
||||
input_3_eth_payload_tuser=input_3_eth_payload_tuser,
|
||||
s_eth_hdr_valid=s_eth_hdr_valid,
|
||||
s_eth_hdr_ready=s_eth_hdr_ready,
|
||||
s_eth_dest_mac=s_eth_dest_mac,
|
||||
s_eth_src_mac=s_eth_src_mac,
|
||||
s_eth_type=s_eth_type,
|
||||
s_eth_payload_axis_tdata=s_eth_payload_axis_tdata,
|
||||
s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep,
|
||||
s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid,
|
||||
s_eth_payload_axis_tready=s_eth_payload_axis_tready,
|
||||
s_eth_payload_axis_tlast=s_eth_payload_axis_tlast,
|
||||
s_eth_payload_axis_tid=s_eth_payload_axis_tid,
|
||||
s_eth_payload_axis_tdest=s_eth_payload_axis_tdest,
|
||||
s_eth_payload_axis_tuser=s_eth_payload_axis_tuser,
|
||||
|
||||
output_eth_hdr_valid=output_eth_hdr_valid,
|
||||
output_eth_hdr_ready=output_eth_hdr_ready,
|
||||
output_eth_dest_mac=output_eth_dest_mac,
|
||||
output_eth_src_mac=output_eth_src_mac,
|
||||
output_eth_type=output_eth_type,
|
||||
output_eth_payload_tdata=output_eth_payload_tdata,
|
||||
output_eth_payload_tvalid=output_eth_payload_tvalid,
|
||||
output_eth_payload_tready=output_eth_payload_tready,
|
||||
output_eth_payload_tlast=output_eth_payload_tlast,
|
||||
output_eth_payload_tuser=output_eth_payload_tuser,
|
||||
m_eth_hdr_valid=m_eth_hdr_valid,
|
||||
m_eth_hdr_ready=m_eth_hdr_ready,
|
||||
m_eth_dest_mac=m_eth_dest_mac,
|
||||
m_eth_src_mac=m_eth_src_mac,
|
||||
m_eth_type=m_eth_type,
|
||||
m_eth_payload_axis_tdata=m_eth_payload_axis_tdata,
|
||||
m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep,
|
||||
m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid,
|
||||
m_eth_payload_axis_tready=m_eth_payload_axis_tready,
|
||||
m_eth_payload_axis_tlast=m_eth_payload_axis_tlast,
|
||||
m_eth_payload_axis_tid=m_eth_payload_axis_tid,
|
||||
m_eth_payload_axis_tdest=m_eth_payload_axis_tdest,
|
||||
m_eth_payload_axis_tuser=m_eth_payload_axis_tuser,
|
||||
|
||||
enable=enable,
|
||||
select=select
|
||||
@ -303,7 +231,7 @@ def bench():
|
||||
test_frame.eth_type = 0x8000
|
||||
test_frame.payload = bytearray(range(32))
|
||||
|
||||
source_0.send(test_frame)
|
||||
source_list[0].send(test_frame)
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
@ -324,7 +252,7 @@ def bench():
|
||||
test_frame.eth_type = 0x8000
|
||||
test_frame.payload = bytearray(range(32))
|
||||
|
||||
source_1.send(test_frame)
|
||||
source_list[1].send(test_frame)
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
@ -350,8 +278,8 @@ def bench():
|
||||
test_frame2.eth_type = 0x8000
|
||||
test_frame2.payload = bytearray(range(32))
|
||||
|
||||
source_0.send(test_frame1)
|
||||
source_0.send(test_frame2)
|
||||
source_list[0].send(test_frame1)
|
||||
source_list[0].send(test_frame2)
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
@ -382,12 +310,12 @@ def bench():
|
||||
test_frame2.eth_type = 0x8000
|
||||
test_frame2.payload = bytearray(range(32))
|
||||
|
||||
source_1.send(test_frame1)
|
||||
source_2.send(test_frame2)
|
||||
source_list[1].send(test_frame1)
|
||||
source_list[2].send(test_frame2)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid:
|
||||
while s_eth_payload_axis_tvalid:
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
@ -420,23 +348,23 @@ def bench():
|
||||
test_frame2.eth_type = 0x8000
|
||||
test_frame2.payload = bytearray(range(32))
|
||||
|
||||
source_1.send(test_frame1)
|
||||
source_2.send(test_frame2)
|
||||
source_list[1].send(test_frame1)
|
||||
source_list[2].send(test_frame2)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid:
|
||||
source_0_pause.next = True
|
||||
source_1_pause.next = True
|
||||
source_2_pause.next = True
|
||||
source_3_pause.next = True
|
||||
while s_eth_payload_axis_tvalid:
|
||||
source_pause_list[0].next = True
|
||||
source_pause_list[1].next = True
|
||||
source_pause_list[2].next = True
|
||||
source_pause_list[3].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_0_pause.next = False
|
||||
source_1_pause.next = False
|
||||
source_2_pause.next = False
|
||||
source_3_pause.next = False
|
||||
source_pause_list[0].next = False
|
||||
source_pause_list[1].next = False
|
||||
source_pause_list[2].next = False
|
||||
source_pause_list[3].next = False
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
@ -469,12 +397,12 @@ def bench():
|
||||
test_frame2.eth_type = 0x8000
|
||||
test_frame2.payload = bytearray(range(32))
|
||||
|
||||
source_1.send(test_frame1)
|
||||
source_2.send(test_frame2)
|
||||
source_list[1].send(test_frame1)
|
||||
source_list[2].send(test_frame2)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid:
|
||||
while s_eth_payload_axis_tvalid:
|
||||
sink_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
@ -27,72 +27,60 @@ THE SOFTWARE.
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for eth_mux_4
|
||||
* Testbench for eth_mux
|
||||
*/
|
||||
module test_eth_mux_4;
|
||||
|
||||
// Parameters
|
||||
parameter S_COUNT = 4;
|
||||
parameter DATA_WIDTH = 8;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter ID_ENABLE = 1;
|
||||
parameter ID_WIDTH = 8;
|
||||
parameter DEST_ENABLE = 1;
|
||||
parameter DEST_WIDTH = 8;
|
||||
parameter USER_ENABLE = 1;
|
||||
parameter USER_WIDTH = 1;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg input_0_eth_hdr_valid = 0;
|
||||
reg [47:0] input_0_eth_dest_mac = 0;
|
||||
reg [47:0] input_0_eth_src_mac = 0;
|
||||
reg [15:0] input_0_eth_type = 0;
|
||||
reg [7:0] input_0_eth_payload_tdata = 0;
|
||||
reg input_0_eth_payload_tvalid = 0;
|
||||
reg input_0_eth_payload_tlast = 0;
|
||||
reg input_0_eth_payload_tuser = 0;
|
||||
reg input_1_eth_hdr_valid = 0;
|
||||
reg [47:0] input_1_eth_dest_mac = 0;
|
||||
reg [47:0] input_1_eth_src_mac = 0;
|
||||
reg [15:0] input_1_eth_type = 0;
|
||||
reg [7:0] input_1_eth_payload_tdata = 0;
|
||||
reg input_1_eth_payload_tvalid = 0;
|
||||
reg input_1_eth_payload_tlast = 0;
|
||||
reg input_1_eth_payload_tuser = 0;
|
||||
reg input_2_eth_hdr_valid = 0;
|
||||
reg [47:0] input_2_eth_dest_mac = 0;
|
||||
reg [47:0] input_2_eth_src_mac = 0;
|
||||
reg [15:0] input_2_eth_type = 0;
|
||||
reg [7:0] input_2_eth_payload_tdata = 0;
|
||||
reg input_2_eth_payload_tvalid = 0;
|
||||
reg input_2_eth_payload_tlast = 0;
|
||||
reg input_2_eth_payload_tuser = 0;
|
||||
reg input_3_eth_hdr_valid = 0;
|
||||
reg [47:0] input_3_eth_dest_mac = 0;
|
||||
reg [47:0] input_3_eth_src_mac = 0;
|
||||
reg [15:0] input_3_eth_type = 0;
|
||||
reg [7:0] input_3_eth_payload_tdata = 0;
|
||||
reg input_3_eth_payload_tvalid = 0;
|
||||
reg input_3_eth_payload_tlast = 0;
|
||||
reg input_3_eth_payload_tuser = 0;
|
||||
reg [S_COUNT-1:0] s_eth_hdr_valid = 0;
|
||||
reg [S_COUNT*48-1:0] s_eth_dest_mac = 0;
|
||||
reg [S_COUNT*48-1:0] s_eth_src_mac = 0;
|
||||
reg [S_COUNT*16-1:0] s_eth_type = 0;
|
||||
reg [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
|
||||
reg [S_COUNT-1:0] s_eth_payload_axis_tvalid = 0;
|
||||
reg [S_COUNT-1:0] s_eth_payload_axis_tlast = 0;
|
||||
reg [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid = 0;
|
||||
reg [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0;
|
||||
reg [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0;
|
||||
|
||||
reg output_eth_hdr_ready = 0;
|
||||
reg output_eth_payload_tready = 0;
|
||||
reg m_eth_hdr_ready = 0;
|
||||
reg m_eth_payload_axis_tready = 0;
|
||||
|
||||
reg enable = 0;
|
||||
reg [1:0] select = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_0_eth_payload_tready;
|
||||
wire input_0_eth_hdr_ready;
|
||||
wire input_1_eth_payload_tready;
|
||||
wire input_1_eth_hdr_ready;
|
||||
wire input_2_eth_payload_tready;
|
||||
wire input_2_eth_hdr_ready;
|
||||
wire input_3_eth_payload_tready;
|
||||
wire input_3_eth_hdr_ready;
|
||||
wire [S_COUNT-1:0] s_eth_hdr_ready;
|
||||
wire [S_COUNT-1:0] s_eth_payload_axis_tready;
|
||||
|
||||
wire output_eth_hdr_valid;
|
||||
wire [47:0] output_eth_dest_mac;
|
||||
wire [47:0] output_eth_src_mac;
|
||||
wire [15:0] output_eth_type;
|
||||
wire [7:0] output_eth_payload_tdata;
|
||||
wire output_eth_payload_tvalid;
|
||||
wire output_eth_payload_tlast;
|
||||
wire output_eth_payload_tuser;
|
||||
wire m_eth_hdr_valid;
|
||||
wire [47:0] m_eth_dest_mac;
|
||||
wire [47:0] m_eth_src_mac;
|
||||
wire [15:0] m_eth_type;
|
||||
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
|
||||
wire m_eth_payload_axis_tvalid;
|
||||
wire m_eth_payload_axis_tlast;
|
||||
wire [ID_WIDTH-1:0] m_eth_payload_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
@ -100,60 +88,36 @@ initial begin
|
||||
clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_0_eth_hdr_valid,
|
||||
input_0_eth_dest_mac,
|
||||
input_0_eth_src_mac,
|
||||
input_0_eth_type,
|
||||
input_0_eth_payload_tdata,
|
||||
input_0_eth_payload_tvalid,
|
||||
input_0_eth_payload_tlast,
|
||||
input_0_eth_payload_tuser,
|
||||
input_1_eth_hdr_valid,
|
||||
input_1_eth_dest_mac,
|
||||
input_1_eth_src_mac,
|
||||
input_1_eth_type,
|
||||
input_1_eth_payload_tdata,
|
||||
input_1_eth_payload_tvalid,
|
||||
input_1_eth_payload_tlast,
|
||||
input_1_eth_payload_tuser,
|
||||
input_2_eth_hdr_valid,
|
||||
input_2_eth_dest_mac,
|
||||
input_2_eth_src_mac,
|
||||
input_2_eth_type,
|
||||
input_2_eth_payload_tdata,
|
||||
input_2_eth_payload_tvalid,
|
||||
input_2_eth_payload_tlast,
|
||||
input_2_eth_payload_tuser,
|
||||
input_3_eth_hdr_valid,
|
||||
input_3_eth_dest_mac,
|
||||
input_3_eth_src_mac,
|
||||
input_3_eth_type,
|
||||
input_3_eth_payload_tdata,
|
||||
input_3_eth_payload_tvalid,
|
||||
input_3_eth_payload_tlast,
|
||||
input_3_eth_payload_tuser,
|
||||
output_eth_hdr_ready,
|
||||
output_eth_payload_tready,
|
||||
s_eth_hdr_valid,
|
||||
s_eth_dest_mac,
|
||||
s_eth_src_mac,
|
||||
s_eth_type,
|
||||
s_eth_payload_axis_tdata,
|
||||
s_eth_payload_axis_tkeep,
|
||||
s_eth_payload_axis_tvalid,
|
||||
s_eth_payload_axis_tlast,
|
||||
s_eth_payload_axis_tid,
|
||||
s_eth_payload_axis_tdest,
|
||||
s_eth_payload_axis_tuser,
|
||||
m_eth_hdr_ready,
|
||||
m_eth_payload_axis_tready,
|
||||
enable,
|
||||
select
|
||||
);
|
||||
$to_myhdl(
|
||||
input_0_eth_hdr_ready,
|
||||
input_0_eth_payload_tready,
|
||||
input_1_eth_hdr_ready,
|
||||
input_1_eth_payload_tready,
|
||||
input_2_eth_hdr_ready,
|
||||
input_2_eth_payload_tready,
|
||||
input_3_eth_hdr_ready,
|
||||
input_3_eth_payload_tready,
|
||||
output_eth_hdr_valid,
|
||||
output_eth_dest_mac,
|
||||
output_eth_src_mac,
|
||||
output_eth_type,
|
||||
output_eth_payload_tdata,
|
||||
output_eth_payload_tvalid,
|
||||
output_eth_payload_tlast,
|
||||
output_eth_payload_tuser
|
||||
s_eth_hdr_ready,
|
||||
s_eth_payload_axis_tready,
|
||||
m_eth_hdr_valid,
|
||||
m_eth_dest_mac,
|
||||
m_eth_src_mac,
|
||||
m_eth_type,
|
||||
m_eth_payload_axis_tdata,
|
||||
m_eth_payload_axis_tkeep,
|
||||
m_eth_payload_axis_tvalid,
|
||||
m_eth_payload_axis_tlast,
|
||||
m_eth_payload_axis_tid,
|
||||
m_eth_payload_axis_tdest,
|
||||
m_eth_payload_axis_tuser
|
||||
);
|
||||
|
||||
// dump file
|
||||
@ -161,62 +125,49 @@ initial begin
|
||||
$dumpvars(0, test_eth_mux_4);
|
||||
end
|
||||
|
||||
eth_mux_4
|
||||
eth_mux #(
|
||||
.S_COUNT(S_COUNT),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.ID_ENABLE(ID_ENABLE),
|
||||
.ID_WIDTH(ID_WIDTH),
|
||||
.DEST_ENABLE(DEST_ENABLE),
|
||||
.DEST_WIDTH(DEST_WIDTH),
|
||||
.USER_ENABLE(USER_ENABLE),
|
||||
.USER_WIDTH(USER_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// Ethernet frame inputs
|
||||
.input_0_eth_hdr_valid(input_0_eth_hdr_valid),
|
||||
.input_0_eth_hdr_ready(input_0_eth_hdr_ready),
|
||||
.input_0_eth_dest_mac(input_0_eth_dest_mac),
|
||||
.input_0_eth_src_mac(input_0_eth_src_mac),
|
||||
.input_0_eth_type(input_0_eth_type),
|
||||
.input_0_eth_payload_tdata(input_0_eth_payload_tdata),
|
||||
.input_0_eth_payload_tvalid(input_0_eth_payload_tvalid),
|
||||
.input_0_eth_payload_tready(input_0_eth_payload_tready),
|
||||
.input_0_eth_payload_tlast(input_0_eth_payload_tlast),
|
||||
.input_0_eth_payload_tuser(input_0_eth_payload_tuser),
|
||||
.input_1_eth_hdr_valid(input_1_eth_hdr_valid),
|
||||
.input_1_eth_hdr_ready(input_1_eth_hdr_ready),
|
||||
.input_1_eth_dest_mac(input_1_eth_dest_mac),
|
||||
.input_1_eth_src_mac(input_1_eth_src_mac),
|
||||
.input_1_eth_type(input_1_eth_type),
|
||||
.input_1_eth_payload_tdata(input_1_eth_payload_tdata),
|
||||
.input_1_eth_payload_tvalid(input_1_eth_payload_tvalid),
|
||||
.input_1_eth_payload_tready(input_1_eth_payload_tready),
|
||||
.input_1_eth_payload_tlast(input_1_eth_payload_tlast),
|
||||
.input_1_eth_payload_tuser(input_1_eth_payload_tuser),
|
||||
.input_2_eth_hdr_valid(input_2_eth_hdr_valid),
|
||||
.input_2_eth_hdr_ready(input_2_eth_hdr_ready),
|
||||
.input_2_eth_dest_mac(input_2_eth_dest_mac),
|
||||
.input_2_eth_src_mac(input_2_eth_src_mac),
|
||||
.input_2_eth_type(input_2_eth_type),
|
||||
.input_2_eth_payload_tdata(input_2_eth_payload_tdata),
|
||||
.input_2_eth_payload_tvalid(input_2_eth_payload_tvalid),
|
||||
.input_2_eth_payload_tready(input_2_eth_payload_tready),
|
||||
.input_2_eth_payload_tlast(input_2_eth_payload_tlast),
|
||||
.input_2_eth_payload_tuser(input_2_eth_payload_tuser),
|
||||
.input_3_eth_hdr_valid(input_3_eth_hdr_valid),
|
||||
.input_3_eth_hdr_ready(input_3_eth_hdr_ready),
|
||||
.input_3_eth_dest_mac(input_3_eth_dest_mac),
|
||||
.input_3_eth_src_mac(input_3_eth_src_mac),
|
||||
.input_3_eth_type(input_3_eth_type),
|
||||
.input_3_eth_payload_tdata(input_3_eth_payload_tdata),
|
||||
.input_3_eth_payload_tvalid(input_3_eth_payload_tvalid),
|
||||
.input_3_eth_payload_tready(input_3_eth_payload_tready),
|
||||
.input_3_eth_payload_tlast(input_3_eth_payload_tlast),
|
||||
.input_3_eth_payload_tuser(input_3_eth_payload_tuser),
|
||||
.s_eth_hdr_valid(s_eth_hdr_valid),
|
||||
.s_eth_hdr_ready(s_eth_hdr_ready),
|
||||
.s_eth_dest_mac(s_eth_dest_mac),
|
||||
.s_eth_src_mac(s_eth_src_mac),
|
||||
.s_eth_type(s_eth_type),
|
||||
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
|
||||
.s_eth_payload_axis_tid(s_eth_payload_axis_tid),
|
||||
.s_eth_payload_axis_tdest(s_eth_payload_axis_tdest),
|
||||
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
|
||||
// Ethernet frame output
|
||||
.output_eth_hdr_valid(output_eth_hdr_valid),
|
||||
.output_eth_hdr_ready(output_eth_hdr_ready),
|
||||
.output_eth_dest_mac(output_eth_dest_mac),
|
||||
.output_eth_src_mac(output_eth_src_mac),
|
||||
.output_eth_type(output_eth_type),
|
||||
.output_eth_payload_tdata(output_eth_payload_tdata),
|
||||
.output_eth_payload_tvalid(output_eth_payload_tvalid),
|
||||
.output_eth_payload_tready(output_eth_payload_tready),
|
||||
.output_eth_payload_tlast(output_eth_payload_tlast),
|
||||
.output_eth_payload_tuser(output_eth_payload_tuser),
|
||||
.m_eth_hdr_valid(m_eth_hdr_valid),
|
||||
.m_eth_hdr_ready(m_eth_hdr_ready),
|
||||
.m_eth_dest_mac(m_eth_dest_mac),
|
||||
.m_eth_src_mac(m_eth_src_mac),
|
||||
.m_eth_type(m_eth_type),
|
||||
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
|
||||
.m_eth_payload_axis_tid(m_eth_payload_axis_tid),
|
||||
.m_eth_payload_axis_tdest(m_eth_payload_axis_tdest),
|
||||
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
|
||||
// Control
|
||||
.enable(enable),
|
||||
.select(select)
|
||||
|
||||
@ -28,8 +28,8 @@ import os
|
||||
|
||||
import eth_ep
|
||||
|
||||
module = 'eth_mux_64_4'
|
||||
testbench = 'test_%s' % module
|
||||
module = 'eth_mux'
|
||||
testbench = 'test_%s_64_4' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
@ -42,177 +42,119 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
S_COUNT = 4
|
||||
DATA_WIDTH = 64
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
ID_ENABLE = 1
|
||||
ID_WIDTH = 8
|
||||
DEST_ENABLE = 1
|
||||
DEST_WIDTH = 8
|
||||
USER_ENABLE = 1
|
||||
USER_WIDTH = 1
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_0_eth_hdr_valid = Signal(bool(0))
|
||||
input_0_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
input_0_eth_src_mac = Signal(intbv(0)[48:])
|
||||
input_0_eth_type = Signal(intbv(0)[16:])
|
||||
input_0_eth_payload_tdata = Signal(intbv(0)[64:])
|
||||
input_0_eth_payload_tkeep = Signal(intbv(0)[8:])
|
||||
input_0_eth_payload_tvalid = Signal(bool(0))
|
||||
input_0_eth_payload_tlast = Signal(bool(0))
|
||||
input_0_eth_payload_tuser = Signal(bool(0))
|
||||
input_1_eth_hdr_valid = Signal(bool(0))
|
||||
input_1_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
input_1_eth_src_mac = Signal(intbv(0)[48:])
|
||||
input_1_eth_type = Signal(intbv(0)[16:])
|
||||
input_1_eth_payload_tdata = Signal(intbv(0)[64:])
|
||||
input_1_eth_payload_tkeep = Signal(intbv(0)[8:])
|
||||
input_1_eth_payload_tvalid = Signal(bool(0))
|
||||
input_1_eth_payload_tlast = Signal(bool(0))
|
||||
input_1_eth_payload_tuser = Signal(bool(0))
|
||||
input_2_eth_hdr_valid = Signal(bool(0))
|
||||
input_2_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
input_2_eth_src_mac = Signal(intbv(0)[48:])
|
||||
input_2_eth_type = Signal(intbv(0)[16:])
|
||||
input_2_eth_payload_tdata = Signal(intbv(0)[64:])
|
||||
input_2_eth_payload_tkeep = Signal(intbv(0)[8:])
|
||||
input_2_eth_payload_tvalid = Signal(bool(0))
|
||||
input_2_eth_payload_tlast = Signal(bool(0))
|
||||
input_2_eth_payload_tuser = Signal(bool(0))
|
||||
input_3_eth_hdr_valid = Signal(bool(0))
|
||||
input_3_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
input_3_eth_src_mac = Signal(intbv(0)[48:])
|
||||
input_3_eth_type = Signal(intbv(0)[16:])
|
||||
input_3_eth_payload_tdata = Signal(intbv(0)[64:])
|
||||
input_3_eth_payload_tkeep = Signal(intbv(0)[8:])
|
||||
input_3_eth_payload_tvalid = Signal(bool(0))
|
||||
input_3_eth_payload_tlast = Signal(bool(0))
|
||||
input_3_eth_payload_tuser = Signal(bool(0))
|
||||
s_eth_hdr_valid_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_eth_dest_mac_list = [Signal(intbv(0)[48:]) for i in range(S_COUNT)]
|
||||
s_eth_src_mac_list = [Signal(intbv(0)[48:]) for i in range(S_COUNT)]
|
||||
s_eth_type_list = [Signal(intbv(0)[16:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tkeep_list = [Signal(intbv(1)[KEEP_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tlast_list = [Signal(bool(0)) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tdest_list = [Signal(intbv(0)[DEST_WIDTH:]) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tuser_list = [Signal(intbv(0)[USER_WIDTH:]) for i in range(S_COUNT)]
|
||||
|
||||
output_eth_payload_tready = Signal(bool(0))
|
||||
output_eth_hdr_ready = Signal(bool(0))
|
||||
s_eth_hdr_valid = ConcatSignal(*reversed(s_eth_hdr_valid_list))
|
||||
s_eth_dest_mac = ConcatSignal(*reversed(s_eth_dest_mac_list))
|
||||
s_eth_src_mac = ConcatSignal(*reversed(s_eth_src_mac_list))
|
||||
s_eth_type = ConcatSignal(*reversed(s_eth_type_list))
|
||||
s_eth_payload_axis_tdata = ConcatSignal(*reversed(s_eth_payload_axis_tdata_list))
|
||||
s_eth_payload_axis_tkeep = ConcatSignal(*reversed(s_eth_payload_axis_tkeep_list))
|
||||
s_eth_payload_axis_tvalid = ConcatSignal(*reversed(s_eth_payload_axis_tvalid_list))
|
||||
s_eth_payload_axis_tlast = ConcatSignal(*reversed(s_eth_payload_axis_tlast_list))
|
||||
s_eth_payload_axis_tid = ConcatSignal(*reversed(s_eth_payload_axis_tid_list))
|
||||
s_eth_payload_axis_tdest = ConcatSignal(*reversed(s_eth_payload_axis_tdest_list))
|
||||
s_eth_payload_axis_tuser = ConcatSignal(*reversed(s_eth_payload_axis_tuser_list))
|
||||
|
||||
m_eth_hdr_ready = Signal(bool(0))
|
||||
m_eth_payload_axis_tready = Signal(bool(0))
|
||||
|
||||
enable = Signal(bool(0))
|
||||
select = Signal(intbv(0)[2:])
|
||||
|
||||
# Outputs
|
||||
input_0_eth_hdr_ready = Signal(bool(0))
|
||||
input_0_eth_payload_tready = Signal(bool(0))
|
||||
input_1_eth_hdr_ready = Signal(bool(0))
|
||||
input_1_eth_payload_tready = Signal(bool(0))
|
||||
input_2_eth_hdr_ready = Signal(bool(0))
|
||||
input_2_eth_payload_tready = Signal(bool(0))
|
||||
input_3_eth_hdr_ready = Signal(bool(0))
|
||||
input_3_eth_payload_tready = Signal(bool(0))
|
||||
s_eth_hdr_ready = Signal(intbv(0)[S_COUNT:])
|
||||
s_eth_payload_axis_tready = Signal(intbv(0)[S_COUNT:])
|
||||
|
||||
output_eth_hdr_valid = Signal(bool(0))
|
||||
output_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
output_eth_src_mac = Signal(intbv(0)[48:])
|
||||
output_eth_type = Signal(intbv(0)[16:])
|
||||
output_eth_payload_tdata = Signal(intbv(0)[64:])
|
||||
output_eth_payload_tkeep = Signal(intbv(0)[8:])
|
||||
output_eth_payload_tvalid = Signal(bool(0))
|
||||
output_eth_payload_tlast = Signal(bool(0))
|
||||
output_eth_payload_tuser = Signal(bool(0))
|
||||
s_eth_hdr_ready_list = [s_eth_hdr_ready(i) for i in range(S_COUNT)]
|
||||
s_eth_payload_axis_tready_list = [s_eth_payload_axis_tready(i) for i in range(S_COUNT)]
|
||||
|
||||
m_eth_hdr_valid = Signal(bool(0))
|
||||
m_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
m_eth_src_mac = Signal(intbv(0)[48:])
|
||||
m_eth_type = Signal(intbv(0)[16:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
m_eth_payload_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
m_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
m_eth_payload_axis_tlast = Signal(bool(0))
|
||||
m_eth_payload_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
m_eth_payload_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
m_eth_payload_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
|
||||
# sources and sinks
|
||||
source_0_pause = Signal(bool(0))
|
||||
source_1_pause = Signal(bool(0))
|
||||
source_2_pause = Signal(bool(0))
|
||||
source_3_pause = Signal(bool(0))
|
||||
source_pause_list = []
|
||||
source_list = []
|
||||
source_logic_list = []
|
||||
sink_pause = Signal(bool(0))
|
||||
|
||||
source_0 = eth_ep.EthFrameSource()
|
||||
for k in range(S_COUNT):
|
||||
s = eth_ep.EthFrameSource()
|
||||
p = Signal(bool(0))
|
||||
|
||||
source_0_logic = source_0.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=input_0_eth_hdr_ready,
|
||||
eth_hdr_valid=input_0_eth_hdr_valid,
|
||||
eth_dest_mac=input_0_eth_dest_mac,
|
||||
eth_src_mac=input_0_eth_src_mac,
|
||||
eth_type=input_0_eth_type,
|
||||
eth_payload_tdata=input_0_eth_payload_tdata,
|
||||
eth_payload_tkeep=input_0_eth_payload_tkeep,
|
||||
eth_payload_tvalid=input_0_eth_payload_tvalid,
|
||||
eth_payload_tready=input_0_eth_payload_tready,
|
||||
eth_payload_tlast=input_0_eth_payload_tlast,
|
||||
eth_payload_tuser=input_0_eth_payload_tuser,
|
||||
pause=source_0_pause,
|
||||
name='source_0'
|
||||
)
|
||||
source_list.append(s)
|
||||
source_pause_list.append(p)
|
||||
|
||||
source_1 = eth_ep.EthFrameSource()
|
||||
|
||||
source_1_logic = source_1.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=input_1_eth_hdr_ready,
|
||||
eth_hdr_valid=input_1_eth_hdr_valid,
|
||||
eth_dest_mac=input_1_eth_dest_mac,
|
||||
eth_src_mac=input_1_eth_src_mac,
|
||||
eth_type=input_1_eth_type,
|
||||
eth_payload_tdata=input_1_eth_payload_tdata,
|
||||
eth_payload_tkeep=input_1_eth_payload_tkeep,
|
||||
eth_payload_tvalid=input_1_eth_payload_tvalid,
|
||||
eth_payload_tready=input_1_eth_payload_tready,
|
||||
eth_payload_tlast=input_1_eth_payload_tlast,
|
||||
eth_payload_tuser=input_1_eth_payload_tuser,
|
||||
pause=source_1_pause,
|
||||
name='source_1'
|
||||
)
|
||||
|
||||
source_2 = eth_ep.EthFrameSource()
|
||||
|
||||
source_2_logic = source_2.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=input_2_eth_hdr_ready,
|
||||
eth_hdr_valid=input_2_eth_hdr_valid,
|
||||
eth_dest_mac=input_2_eth_dest_mac,
|
||||
eth_src_mac=input_2_eth_src_mac,
|
||||
eth_type=input_2_eth_type,
|
||||
eth_payload_tdata=input_2_eth_payload_tdata,
|
||||
eth_payload_tkeep=input_2_eth_payload_tkeep,
|
||||
eth_payload_tvalid=input_2_eth_payload_tvalid,
|
||||
eth_payload_tready=input_2_eth_payload_tready,
|
||||
eth_payload_tlast=input_2_eth_payload_tlast,
|
||||
eth_payload_tuser=input_2_eth_payload_tuser,
|
||||
pause=source_2_pause,
|
||||
name='source_2'
|
||||
)
|
||||
|
||||
source_3 = eth_ep.EthFrameSource()
|
||||
|
||||
source_3_logic = source_3.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=input_3_eth_hdr_ready,
|
||||
eth_hdr_valid=input_3_eth_hdr_valid,
|
||||
eth_dest_mac=input_3_eth_dest_mac,
|
||||
eth_src_mac=input_3_eth_src_mac,
|
||||
eth_type=input_3_eth_type,
|
||||
eth_payload_tdata=input_3_eth_payload_tdata,
|
||||
eth_payload_tkeep=input_3_eth_payload_tkeep,
|
||||
eth_payload_tvalid=input_3_eth_payload_tvalid,
|
||||
eth_payload_tready=input_3_eth_payload_tready,
|
||||
eth_payload_tlast=input_3_eth_payload_tlast,
|
||||
eth_payload_tuser=input_3_eth_payload_tuser,
|
||||
pause=source_3_pause,
|
||||
name='source_3'
|
||||
)
|
||||
source_logic_list.append(s.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=s_eth_hdr_ready_list[k],
|
||||
eth_hdr_valid=s_eth_hdr_valid_list[k],
|
||||
eth_dest_mac=s_eth_dest_mac_list[k],
|
||||
eth_src_mac=s_eth_src_mac_list[k],
|
||||
eth_type=s_eth_type_list[k],
|
||||
eth_payload_tdata=s_eth_payload_axis_tdata_list[k],
|
||||
eth_payload_tkeep=s_eth_payload_axis_tkeep_list[k],
|
||||
eth_payload_tvalid=s_eth_payload_axis_tvalid_list[k],
|
||||
eth_payload_tready=s_eth_payload_axis_tready_list[k],
|
||||
eth_payload_tlast=s_eth_payload_axis_tlast_list[k],
|
||||
eth_payload_tuser=s_eth_payload_axis_tuser_list[k],
|
||||
pause=p,
|
||||
name='source_%d' % k
|
||||
))
|
||||
|
||||
sink = eth_ep.EthFrameSink()
|
||||
|
||||
sink_logic = sink.create_logic(
|
||||
clk,
|
||||
rst,
|
||||
eth_hdr_ready=output_eth_hdr_ready,
|
||||
eth_hdr_valid=output_eth_hdr_valid,
|
||||
eth_dest_mac=output_eth_dest_mac,
|
||||
eth_src_mac=output_eth_src_mac,
|
||||
eth_type=output_eth_type,
|
||||
eth_payload_tdata=output_eth_payload_tdata,
|
||||
eth_payload_tkeep=output_eth_payload_tkeep,
|
||||
eth_payload_tvalid=output_eth_payload_tvalid,
|
||||
eth_payload_tready=output_eth_payload_tready,
|
||||
eth_payload_tlast=output_eth_payload_tlast,
|
||||
eth_payload_tuser=output_eth_payload_tuser,
|
||||
eth_hdr_ready=m_eth_hdr_ready,
|
||||
eth_hdr_valid=m_eth_hdr_valid,
|
||||
eth_dest_mac=m_eth_dest_mac,
|
||||
eth_src_mac=m_eth_src_mac,
|
||||
eth_type=m_eth_type,
|
||||
eth_payload_tdata=m_eth_payload_axis_tdata,
|
||||
eth_payload_tkeep=m_eth_payload_axis_tkeep,
|
||||
eth_payload_tvalid=m_eth_payload_axis_tvalid,
|
||||
eth_payload_tready=m_eth_payload_axis_tready,
|
||||
eth_payload_tlast=m_eth_payload_axis_tlast,
|
||||
eth_payload_tuser=m_eth_payload_axis_tuser,
|
||||
pause=sink_pause,
|
||||
name='sink'
|
||||
)
|
||||
@ -227,62 +169,33 @@ def bench():
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_0_eth_hdr_valid=input_0_eth_hdr_valid,
|
||||
input_0_eth_hdr_ready=input_0_eth_hdr_ready,
|
||||
input_0_eth_dest_mac=input_0_eth_dest_mac,
|
||||
input_0_eth_src_mac=input_0_eth_src_mac,
|
||||
input_0_eth_type=input_0_eth_type,
|
||||
input_0_eth_payload_tdata=input_0_eth_payload_tdata,
|
||||
input_0_eth_payload_tkeep=input_0_eth_payload_tkeep,
|
||||
input_0_eth_payload_tvalid=input_0_eth_payload_tvalid,
|
||||
input_0_eth_payload_tready=input_0_eth_payload_tready,
|
||||
input_0_eth_payload_tlast=input_0_eth_payload_tlast,
|
||||
input_0_eth_payload_tuser=input_0_eth_payload_tuser,
|
||||
input_1_eth_hdr_valid=input_1_eth_hdr_valid,
|
||||
input_1_eth_hdr_ready=input_1_eth_hdr_ready,
|
||||
input_1_eth_dest_mac=input_1_eth_dest_mac,
|
||||
input_1_eth_src_mac=input_1_eth_src_mac,
|
||||
input_1_eth_type=input_1_eth_type,
|
||||
input_1_eth_payload_tdata=input_1_eth_payload_tdata,
|
||||
input_1_eth_payload_tkeep=input_1_eth_payload_tkeep,
|
||||
input_1_eth_payload_tvalid=input_1_eth_payload_tvalid,
|
||||
input_1_eth_payload_tready=input_1_eth_payload_tready,
|
||||
input_1_eth_payload_tlast=input_1_eth_payload_tlast,
|
||||
input_1_eth_payload_tuser=input_1_eth_payload_tuser,
|
||||
input_2_eth_hdr_valid=input_2_eth_hdr_valid,
|
||||
input_2_eth_hdr_ready=input_2_eth_hdr_ready,
|
||||
input_2_eth_dest_mac=input_2_eth_dest_mac,
|
||||
input_2_eth_src_mac=input_2_eth_src_mac,
|
||||
input_2_eth_type=input_2_eth_type,
|
||||
input_2_eth_payload_tdata=input_2_eth_payload_tdata,
|
||||
input_2_eth_payload_tkeep=input_2_eth_payload_tkeep,
|
||||
input_2_eth_payload_tvalid=input_2_eth_payload_tvalid,
|
||||
input_2_eth_payload_tready=input_2_eth_payload_tready,
|
||||
input_2_eth_payload_tlast=input_2_eth_payload_tlast,
|
||||
input_2_eth_payload_tuser=input_2_eth_payload_tuser,
|
||||
input_3_eth_hdr_valid=input_3_eth_hdr_valid,
|
||||
input_3_eth_hdr_ready=input_3_eth_hdr_ready,
|
||||
input_3_eth_dest_mac=input_3_eth_dest_mac,
|
||||
input_3_eth_src_mac=input_3_eth_src_mac,
|
||||
input_3_eth_type=input_3_eth_type,
|
||||
input_3_eth_payload_tdata=input_3_eth_payload_tdata,
|
||||
input_3_eth_payload_tkeep=input_3_eth_payload_tkeep,
|
||||
input_3_eth_payload_tvalid=input_3_eth_payload_tvalid,
|
||||
input_3_eth_payload_tready=input_3_eth_payload_tready,
|
||||
input_3_eth_payload_tlast=input_3_eth_payload_tlast,
|
||||
input_3_eth_payload_tuser=input_3_eth_payload_tuser,
|
||||
s_eth_hdr_valid=s_eth_hdr_valid,
|
||||
s_eth_hdr_ready=s_eth_hdr_ready,
|
||||
s_eth_dest_mac=s_eth_dest_mac,
|
||||
s_eth_src_mac=s_eth_src_mac,
|
||||
s_eth_type=s_eth_type,
|
||||
s_eth_payload_axis_tdata=s_eth_payload_axis_tdata,
|
||||
s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep,
|
||||
s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid,
|
||||
s_eth_payload_axis_tready=s_eth_payload_axis_tready,
|
||||
s_eth_payload_axis_tlast=s_eth_payload_axis_tlast,
|
||||
s_eth_payload_axis_tid=s_eth_payload_axis_tid,
|
||||
s_eth_payload_axis_tdest=s_eth_payload_axis_tdest,
|
||||
s_eth_payload_axis_tuser=s_eth_payload_axis_tuser,
|
||||
|
||||
output_eth_hdr_valid=output_eth_hdr_valid,
|
||||
output_eth_hdr_ready=output_eth_hdr_ready,
|
||||
output_eth_dest_mac=output_eth_dest_mac,
|
||||
output_eth_src_mac=output_eth_src_mac,
|
||||
output_eth_type=output_eth_type,
|
||||
output_eth_payload_tdata=output_eth_payload_tdata,
|
||||
output_eth_payload_tkeep=output_eth_payload_tkeep,
|
||||
output_eth_payload_tvalid=output_eth_payload_tvalid,
|
||||
output_eth_payload_tready=output_eth_payload_tready,
|
||||
output_eth_payload_tlast=output_eth_payload_tlast,
|
||||
output_eth_payload_tuser=output_eth_payload_tuser,
|
||||
m_eth_hdr_valid=m_eth_hdr_valid,
|
||||
m_eth_hdr_ready=m_eth_hdr_ready,
|
||||
m_eth_dest_mac=m_eth_dest_mac,
|
||||
m_eth_src_mac=m_eth_src_mac,
|
||||
m_eth_type=m_eth_type,
|
||||
m_eth_payload_axis_tdata=m_eth_payload_axis_tdata,
|
||||
m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep,
|
||||
m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid,
|
||||
m_eth_payload_axis_tready=m_eth_payload_axis_tready,
|
||||
m_eth_payload_axis_tlast=m_eth_payload_axis_tlast,
|
||||
m_eth_payload_axis_tid=m_eth_payload_axis_tid,
|
||||
m_eth_payload_axis_tdest=m_eth_payload_axis_tdest,
|
||||
m_eth_payload_axis_tuser=m_eth_payload_axis_tuser,
|
||||
|
||||
enable=enable,
|
||||
select=select
|
||||
@ -318,7 +231,7 @@ def bench():
|
||||
test_frame.eth_type = 0x8000
|
||||
test_frame.payload = bytearray(range(32))
|
||||
|
||||
source_0.send(test_frame)
|
||||
source_list[0].send(test_frame)
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
@ -339,7 +252,7 @@ def bench():
|
||||
test_frame.eth_type = 0x8000
|
||||
test_frame.payload = bytearray(range(32))
|
||||
|
||||
source_1.send(test_frame)
|
||||
source_list[1].send(test_frame)
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
@ -365,8 +278,8 @@ def bench():
|
||||
test_frame2.eth_type = 0x8000
|
||||
test_frame2.payload = bytearray(range(32))
|
||||
|
||||
source_0.send(test_frame1)
|
||||
source_0.send(test_frame2)
|
||||
source_list[0].send(test_frame1)
|
||||
source_list[0].send(test_frame2)
|
||||
|
||||
yield sink.wait()
|
||||
rx_frame = sink.recv()
|
||||
@ -397,12 +310,12 @@ def bench():
|
||||
test_frame2.eth_type = 0x8000
|
||||
test_frame2.payload = bytearray(range(32))
|
||||
|
||||
source_1.send(test_frame1)
|
||||
source_2.send(test_frame2)
|
||||
source_list[1].send(test_frame1)
|
||||
source_list[2].send(test_frame2)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid:
|
||||
while s_eth_payload_axis_tvalid:
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
@ -435,23 +348,23 @@ def bench():
|
||||
test_frame2.eth_type = 0x8000
|
||||
test_frame2.payload = bytearray(range(32))
|
||||
|
||||
source_1.send(test_frame1)
|
||||
source_2.send(test_frame2)
|
||||
source_list[1].send(test_frame1)
|
||||
source_list[2].send(test_frame2)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid:
|
||||
source_0_pause.next = True
|
||||
source_1_pause.next = True
|
||||
source_2_pause.next = True
|
||||
source_3_pause.next = True
|
||||
while s_eth_payload_axis_tvalid:
|
||||
source_pause_list[0].next = True
|
||||
source_pause_list[1].next = True
|
||||
source_pause_list[2].next = True
|
||||
source_pause_list[3].next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_0_pause.next = False
|
||||
source_1_pause.next = False
|
||||
source_2_pause.next = False
|
||||
source_3_pause.next = False
|
||||
source_pause_list[0].next = False
|
||||
source_pause_list[1].next = False
|
||||
source_pause_list[2].next = False
|
||||
source_pause_list[3].next = False
|
||||
yield clk.posedge
|
||||
select.next = 2
|
||||
|
||||
@ -484,12 +397,12 @@ def bench():
|
||||
test_frame2.eth_type = 0x8000
|
||||
test_frame2.payload = bytearray(range(32))
|
||||
|
||||
source_1.send(test_frame1)
|
||||
source_2.send(test_frame2)
|
||||
source_list[1].send(test_frame1)
|
||||
source_list[2].send(test_frame2)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid:
|
||||
while s_eth_payload_axis_tvalid:
|
||||
sink_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
@ -27,77 +27,60 @@ THE SOFTWARE.
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for eth_mux_64_4
|
||||
* Testbench for eth_mux
|
||||
*/
|
||||
module test_eth_mux_64_4;
|
||||
|
||||
// Parameters
|
||||
parameter S_COUNT = 4;
|
||||
parameter DATA_WIDTH = 64;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter ID_ENABLE = 1;
|
||||
parameter ID_WIDTH = 8;
|
||||
parameter DEST_ENABLE = 1;
|
||||
parameter DEST_WIDTH = 8;
|
||||
parameter USER_ENABLE = 1;
|
||||
parameter USER_WIDTH = 1;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg input_0_eth_hdr_valid = 0;
|
||||
reg [47:0] input_0_eth_dest_mac = 0;
|
||||
reg [47:0] input_0_eth_src_mac = 0;
|
||||
reg [15:0] input_0_eth_type = 0;
|
||||
reg [63:0] input_0_eth_payload_tdata = 0;
|
||||
reg [7:0] input_0_eth_payload_tkeep = 0;
|
||||
reg input_0_eth_payload_tvalid = 0;
|
||||
reg input_0_eth_payload_tlast = 0;
|
||||
reg input_0_eth_payload_tuser = 0;
|
||||
reg input_1_eth_hdr_valid = 0;
|
||||
reg [47:0] input_1_eth_dest_mac = 0;
|
||||
reg [47:0] input_1_eth_src_mac = 0;
|
||||
reg [15:0] input_1_eth_type = 0;
|
||||
reg [63:0] input_1_eth_payload_tdata = 0;
|
||||
reg [7:0] input_1_eth_payload_tkeep = 0;
|
||||
reg input_1_eth_payload_tvalid = 0;
|
||||
reg input_1_eth_payload_tlast = 0;
|
||||
reg input_1_eth_payload_tuser = 0;
|
||||
reg input_2_eth_hdr_valid = 0;
|
||||
reg [47:0] input_2_eth_dest_mac = 0;
|
||||
reg [47:0] input_2_eth_src_mac = 0;
|
||||
reg [15:0] input_2_eth_type = 0;
|
||||
reg [63:0] input_2_eth_payload_tdata = 0;
|
||||
reg [7:0] input_2_eth_payload_tkeep = 0;
|
||||
reg input_2_eth_payload_tvalid = 0;
|
||||
reg input_2_eth_payload_tlast = 0;
|
||||
reg input_2_eth_payload_tuser = 0;
|
||||
reg input_3_eth_hdr_valid = 0;
|
||||
reg [47:0] input_3_eth_dest_mac = 0;
|
||||
reg [47:0] input_3_eth_src_mac = 0;
|
||||
reg [15:0] input_3_eth_type = 0;
|
||||
reg [63:0] input_3_eth_payload_tdata = 0;
|
||||
reg [7:0] input_3_eth_payload_tkeep = 0;
|
||||
reg input_3_eth_payload_tvalid = 0;
|
||||
reg input_3_eth_payload_tlast = 0;
|
||||
reg input_3_eth_payload_tuser = 0;
|
||||
reg [S_COUNT-1:0] s_eth_hdr_valid = 0;
|
||||
reg [S_COUNT*48-1:0] s_eth_dest_mac = 0;
|
||||
reg [S_COUNT*48-1:0] s_eth_src_mac = 0;
|
||||
reg [S_COUNT*16-1:0] s_eth_type = 0;
|
||||
reg [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
|
||||
reg [S_COUNT-1:0] s_eth_payload_axis_tvalid = 0;
|
||||
reg [S_COUNT-1:0] s_eth_payload_axis_tlast = 0;
|
||||
reg [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid = 0;
|
||||
reg [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0;
|
||||
reg [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0;
|
||||
|
||||
reg output_eth_hdr_ready = 0;
|
||||
reg output_eth_payload_tready = 0;
|
||||
reg m_eth_hdr_ready = 0;
|
||||
reg m_eth_payload_axis_tready = 0;
|
||||
|
||||
reg enable = 0;
|
||||
reg [1:0] select = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_0_eth_payload_tready;
|
||||
wire input_0_eth_hdr_ready;
|
||||
wire input_1_eth_payload_tready;
|
||||
wire input_1_eth_hdr_ready;
|
||||
wire input_2_eth_payload_tready;
|
||||
wire input_2_eth_hdr_ready;
|
||||
wire input_3_eth_payload_tready;
|
||||
wire input_3_eth_hdr_ready;
|
||||
wire [S_COUNT-1:0] s_eth_hdr_ready;
|
||||
wire [S_COUNT-1:0] s_eth_payload_axis_tready;
|
||||
|
||||
wire output_eth_hdr_valid;
|
||||
wire [47:0] output_eth_dest_mac;
|
||||
wire [47:0] output_eth_src_mac;
|
||||
wire [15:0] output_eth_type;
|
||||
wire [63:0] output_eth_payload_tdata;
|
||||
wire [7:0] output_eth_payload_tkeep;
|
||||
wire output_eth_payload_tvalid;
|
||||
wire output_eth_payload_tlast;
|
||||
wire output_eth_payload_tuser;
|
||||
wire m_eth_hdr_valid;
|
||||
wire [47:0] m_eth_dest_mac;
|
||||
wire [47:0] m_eth_src_mac;
|
||||
wire [15:0] m_eth_type;
|
||||
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
|
||||
wire m_eth_payload_axis_tvalid;
|
||||
wire m_eth_payload_axis_tlast;
|
||||
wire [ID_WIDTH-1:0] m_eth_payload_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
@ -105,65 +88,36 @@ initial begin
|
||||
clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_0_eth_hdr_valid,
|
||||
input_0_eth_dest_mac,
|
||||
input_0_eth_src_mac,
|
||||
input_0_eth_type,
|
||||
input_0_eth_payload_tdata,
|
||||
input_0_eth_payload_tkeep,
|
||||
input_0_eth_payload_tvalid,
|
||||
input_0_eth_payload_tlast,
|
||||
input_0_eth_payload_tuser,
|
||||
input_1_eth_hdr_valid,
|
||||
input_1_eth_dest_mac,
|
||||
input_1_eth_src_mac,
|
||||
input_1_eth_type,
|
||||
input_1_eth_payload_tdata,
|
||||
input_1_eth_payload_tkeep,
|
||||
input_1_eth_payload_tvalid,
|
||||
input_1_eth_payload_tlast,
|
||||
input_1_eth_payload_tuser,
|
||||
input_2_eth_hdr_valid,
|
||||
input_2_eth_dest_mac,
|
||||
input_2_eth_src_mac,
|
||||
input_2_eth_type,
|
||||
input_2_eth_payload_tdata,
|
||||
input_2_eth_payload_tkeep,
|
||||
input_2_eth_payload_tvalid,
|
||||
input_2_eth_payload_tlast,
|
||||
input_2_eth_payload_tuser,
|
||||
input_3_eth_hdr_valid,
|
||||
input_3_eth_dest_mac,
|
||||
input_3_eth_src_mac,
|
||||
input_3_eth_type,
|
||||
input_3_eth_payload_tdata,
|
||||
input_3_eth_payload_tkeep,
|
||||
input_3_eth_payload_tvalid,
|
||||
input_3_eth_payload_tlast,
|
||||
input_3_eth_payload_tuser,
|
||||
output_eth_hdr_ready,
|
||||
output_eth_payload_tready,
|
||||
s_eth_hdr_valid,
|
||||
s_eth_dest_mac,
|
||||
s_eth_src_mac,
|
||||
s_eth_type,
|
||||
s_eth_payload_axis_tdata,
|
||||
s_eth_payload_axis_tkeep,
|
||||
s_eth_payload_axis_tvalid,
|
||||
s_eth_payload_axis_tlast,
|
||||
s_eth_payload_axis_tid,
|
||||
s_eth_payload_axis_tdest,
|
||||
s_eth_payload_axis_tuser,
|
||||
m_eth_hdr_ready,
|
||||
m_eth_payload_axis_tready,
|
||||
enable,
|
||||
select
|
||||
);
|
||||
$to_myhdl(
|
||||
input_0_eth_hdr_ready,
|
||||
input_0_eth_payload_tready,
|
||||
input_1_eth_hdr_ready,
|
||||
input_1_eth_payload_tready,
|
||||
input_2_eth_hdr_ready,
|
||||
input_2_eth_payload_tready,
|
||||
input_3_eth_hdr_ready,
|
||||
input_3_eth_payload_tready,
|
||||
output_eth_hdr_valid,
|
||||
output_eth_dest_mac,
|
||||
output_eth_src_mac,
|
||||
output_eth_type,
|
||||
output_eth_payload_tdata,
|
||||
output_eth_payload_tkeep,
|
||||
output_eth_payload_tvalid,
|
||||
output_eth_payload_tlast,
|
||||
output_eth_payload_tuser
|
||||
s_eth_hdr_ready,
|
||||
s_eth_payload_axis_tready,
|
||||
m_eth_hdr_valid,
|
||||
m_eth_dest_mac,
|
||||
m_eth_src_mac,
|
||||
m_eth_type,
|
||||
m_eth_payload_axis_tdata,
|
||||
m_eth_payload_axis_tkeep,
|
||||
m_eth_payload_axis_tvalid,
|
||||
m_eth_payload_axis_tlast,
|
||||
m_eth_payload_axis_tid,
|
||||
m_eth_payload_axis_tdest,
|
||||
m_eth_payload_axis_tuser
|
||||
);
|
||||
|
||||
// dump file
|
||||
@ -171,67 +125,49 @@ initial begin
|
||||
$dumpvars(0, test_eth_mux_64_4);
|
||||
end
|
||||
|
||||
eth_mux_64_4
|
||||
eth_mux #(
|
||||
.S_COUNT(S_COUNT),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.ID_ENABLE(ID_ENABLE),
|
||||
.ID_WIDTH(ID_WIDTH),
|
||||
.DEST_ENABLE(DEST_ENABLE),
|
||||
.DEST_WIDTH(DEST_WIDTH),
|
||||
.USER_ENABLE(USER_ENABLE),
|
||||
.USER_WIDTH(USER_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// Ethernet frame inputs
|
||||
.input_0_eth_hdr_valid(input_0_eth_hdr_valid),
|
||||
.input_0_eth_hdr_ready(input_0_eth_hdr_ready),
|
||||
.input_0_eth_dest_mac(input_0_eth_dest_mac),
|
||||
.input_0_eth_src_mac(input_0_eth_src_mac),
|
||||
.input_0_eth_type(input_0_eth_type),
|
||||
.input_0_eth_payload_tdata(input_0_eth_payload_tdata),
|
||||
.input_0_eth_payload_tkeep(input_0_eth_payload_tkeep),
|
||||
.input_0_eth_payload_tvalid(input_0_eth_payload_tvalid),
|
||||
.input_0_eth_payload_tready(input_0_eth_payload_tready),
|
||||
.input_0_eth_payload_tlast(input_0_eth_payload_tlast),
|
||||
.input_0_eth_payload_tuser(input_0_eth_payload_tuser),
|
||||
.input_1_eth_hdr_valid(input_1_eth_hdr_valid),
|
||||
.input_1_eth_hdr_ready(input_1_eth_hdr_ready),
|
||||
.input_1_eth_dest_mac(input_1_eth_dest_mac),
|
||||
.input_1_eth_src_mac(input_1_eth_src_mac),
|
||||
.input_1_eth_type(input_1_eth_type),
|
||||
.input_1_eth_payload_tdata(input_1_eth_payload_tdata),
|
||||
.input_1_eth_payload_tkeep(input_1_eth_payload_tkeep),
|
||||
.input_1_eth_payload_tvalid(input_1_eth_payload_tvalid),
|
||||
.input_1_eth_payload_tready(input_1_eth_payload_tready),
|
||||
.input_1_eth_payload_tlast(input_1_eth_payload_tlast),
|
||||
.input_1_eth_payload_tuser(input_1_eth_payload_tuser),
|
||||
.input_2_eth_hdr_valid(input_2_eth_hdr_valid),
|
||||
.input_2_eth_hdr_ready(input_2_eth_hdr_ready),
|
||||
.input_2_eth_dest_mac(input_2_eth_dest_mac),
|
||||
.input_2_eth_src_mac(input_2_eth_src_mac),
|
||||
.input_2_eth_type(input_2_eth_type),
|
||||
.input_2_eth_payload_tdata(input_2_eth_payload_tdata),
|
||||
.input_2_eth_payload_tkeep(input_2_eth_payload_tkeep),
|
||||
.input_2_eth_payload_tvalid(input_2_eth_payload_tvalid),
|
||||
.input_2_eth_payload_tready(input_2_eth_payload_tready),
|
||||
.input_2_eth_payload_tlast(input_2_eth_payload_tlast),
|
||||
.input_2_eth_payload_tuser(input_2_eth_payload_tuser),
|
||||
.input_3_eth_hdr_valid(input_3_eth_hdr_valid),
|
||||
.input_3_eth_hdr_ready(input_3_eth_hdr_ready),
|
||||
.input_3_eth_dest_mac(input_3_eth_dest_mac),
|
||||
.input_3_eth_src_mac(input_3_eth_src_mac),
|
||||
.input_3_eth_type(input_3_eth_type),
|
||||
.input_3_eth_payload_tdata(input_3_eth_payload_tdata),
|
||||
.input_3_eth_payload_tkeep(input_3_eth_payload_tkeep),
|
||||
.input_3_eth_payload_tvalid(input_3_eth_payload_tvalid),
|
||||
.input_3_eth_payload_tready(input_3_eth_payload_tready),
|
||||
.input_3_eth_payload_tlast(input_3_eth_payload_tlast),
|
||||
.input_3_eth_payload_tuser(input_3_eth_payload_tuser),
|
||||
.s_eth_hdr_valid(s_eth_hdr_valid),
|
||||
.s_eth_hdr_ready(s_eth_hdr_ready),
|
||||
.s_eth_dest_mac(s_eth_dest_mac),
|
||||
.s_eth_src_mac(s_eth_src_mac),
|
||||
.s_eth_type(s_eth_type),
|
||||
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
|
||||
.s_eth_payload_axis_tid(s_eth_payload_axis_tid),
|
||||
.s_eth_payload_axis_tdest(s_eth_payload_axis_tdest),
|
||||
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
|
||||
// Ethernet frame output
|
||||
.output_eth_hdr_valid(output_eth_hdr_valid),
|
||||
.output_eth_hdr_ready(output_eth_hdr_ready),
|
||||
.output_eth_dest_mac(output_eth_dest_mac),
|
||||
.output_eth_src_mac(output_eth_src_mac),
|
||||
.output_eth_type(output_eth_type),
|
||||
.output_eth_payload_tdata(output_eth_payload_tdata),
|
||||
.output_eth_payload_tkeep(output_eth_payload_tkeep),
|
||||
.output_eth_payload_tvalid(output_eth_payload_tvalid),
|
||||
.output_eth_payload_tready(output_eth_payload_tready),
|
||||
.output_eth_payload_tlast(output_eth_payload_tlast),
|
||||
.output_eth_payload_tuser(output_eth_payload_tuser),
|
||||
.m_eth_hdr_valid(m_eth_hdr_valid),
|
||||
.m_eth_hdr_ready(m_eth_hdr_ready),
|
||||
.m_eth_dest_mac(m_eth_dest_mac),
|
||||
.m_eth_src_mac(m_eth_src_mac),
|
||||
.m_eth_type(m_eth_type),
|
||||
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
|
||||
.m_eth_payload_axis_tid(m_eth_payload_axis_tid),
|
||||
.m_eth_payload_axis_tdest(m_eth_payload_axis_tdest),
|
||||
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
|
||||
// Control
|
||||
.enable(enable),
|
||||
.select(select)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user