diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v index 5411ce059..f216470a6 100644 --- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v +++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v @@ -428,10 +428,8 @@ wire btnd_int; wire btnr_int; wire btnc_int; wire [3:0] sw_int; -wire qsfp0_modprsl_int; -wire qsfp1_modprsl_int; -wire qsfp0_intl_int; -wire qsfp1_intl_int; +wire [1:0] qsfp_modprsl_int; +wire [1:0] qsfp_intl_int; wire i2c_scl_i; wire i2c_scl_o; wire i2c_scl_t; @@ -471,7 +469,7 @@ sync_signal_inst ( .clk(pcie_user_clk), .in({qsfp0_modprsl, qsfp1_modprsl, qsfp0_intl, qsfp1_intl, i2c_scl, i2c_sda}), - .out({qsfp0_modprsl_int, qsfp1_modprsl_int, qsfp0_intl_int, qsfp1_intl_int, + .out({qsfp_modprsl_int, qsfp_intl_int, i2c_scl_i, i2c_sda_i}) ); @@ -1094,59 +1092,73 @@ pcie4_uscale_plus_inst ( .phy_rdy_out() ); +// Ethernet +localparam QSFP_CNT = 2; + +wire [QSFP_CNT-1:0] qsfp_tx_clk; +wire [QSFP_CNT-1:0] qsfp_tx_rst; + +wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_tx_axis_tdata; +wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_tx_axis_tkeep; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tvalid; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tready; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tlast; +wire [QSFP_CNT*(16+1)-1:0] qsfp_tx_axis_tuser; + +wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_time; +wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_ts; +wire [QSFP_CNT*16-1:0] qsfp_tx_ptp_ts_tag; +wire [QSFP_CNT-1:0] qsfp_tx_ptp_ts_valid; + +wire [QSFP_CNT-1:0] qsfp_tx_enable; +wire [QSFP_CNT-1:0] qsfp_tx_lfc_en; +wire [QSFP_CNT-1:0] qsfp_tx_lfc_req; +wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_en; +wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_req; + +wire [QSFP_CNT-1:0] qsfp_rx_clk; +wire [QSFP_CNT-1:0] qsfp_rx_rst; + +wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_rx_axis_tdata; +wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_rx_axis_tkeep; +wire [QSFP_CNT-1:0] qsfp_rx_axis_tvalid; +wire [QSFP_CNT-1:0] qsfp_rx_axis_tlast; +wire [QSFP_CNT*(80+1)-1:0] qsfp_rx_axis_tuser; + +wire [QSFP_CNT*80-1:0] qsfp_rx_ptp_time; + +wire [QSFP_CNT-1:0] qsfp_rx_enable; +wire [QSFP_CNT-1:0] qsfp_rx_status; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_en; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_req; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_ack; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_en; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_req; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_ack; + +wire [QSFP_CNT-1:0] qsfp_drp_clk; +wire [QSFP_CNT-1:0] qsfp_drp_rst; +wire [QSFP_CNT*24-1:0] qsfp_drp_addr; +wire [QSFP_CNT*16-1:0] qsfp_drp_di; +wire [QSFP_CNT-1:0] qsfp_drp_en; +wire [QSFP_CNT-1:0] qsfp_drp_we; +wire [QSFP_CNT*16-1:0] qsfp_drp_do; +wire [QSFP_CNT-1:0] qsfp_drp_rdy; + +wire [QSFP_CNT-1:0] qsfp_modsell; +wire [QSFP_CNT-1:0] qsfp_resetl; +wire [QSFP_CNT-1:0] qsfp_lpmode; + // QSFP0 CMAC assign qsfp0_refclk_reset = qsfp_refclk_reset_reg; assign qsfp0_fs = 2'b10; -wire qsfp0_tx_clk_int; -wire qsfp0_tx_rst_int; +assign qsfp_drp_clk[0 +: 1] = clk_125mhz_int; +assign qsfp_drp_rst[0 +: 1] = rst_125mhz_int; -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep_int; -wire qsfp0_tx_axis_tvalid_int; -wire qsfp0_tx_axis_tready_int; -wire qsfp0_tx_axis_tlast_int; -wire [16+1-1:0] qsfp0_tx_axis_tuser_int; - -wire [79:0] qsfp0_tx_ptp_time_int; -wire [79:0] qsfp0_tx_ptp_ts_int; -wire [15:0] qsfp0_tx_ptp_ts_tag_int; -wire qsfp0_tx_ptp_ts_valid_int; - -wire qsfp0_rx_clk_int; -wire qsfp0_rx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep_int; -wire qsfp0_rx_axis_tvalid_int; -wire qsfp0_rx_axis_tlast_int; -wire [80+1-1:0] qsfp0_rx_axis_tuser_int; - -wire [79:0] qsfp0_rx_ptp_time_int; - -wire qsfp0_drp_clk = clk_125mhz_int; -wire qsfp0_drp_rst = rst_125mhz_int; -wire [23:0] qsfp0_drp_addr; -wire [15:0] qsfp0_drp_di; -wire qsfp0_drp_en; -wire qsfp0_drp_we; -wire [15:0] qsfp0_drp_do; -wire qsfp0_drp_rdy; - -wire qsfp0_tx_enable; -wire qsfp0_tx_lfc_en; -wire qsfp0_tx_lfc_req; -wire [7:0] qsfp0_tx_pfc_en; -wire [7:0] qsfp0_tx_pfc_req; - -wire qsfp0_rx_enable; -wire qsfp0_rx_status; -wire qsfp0_rx_lfc_en; -wire qsfp0_rx_lfc_req; -wire qsfp0_rx_lfc_ack; -wire [7:0] qsfp0_rx_pfc_en; -wire [7:0] qsfp0_rx_pfc_req; -wire [7:0] qsfp0_rx_pfc_ack; +assign qsfp0_modsell = qsfp_modsell[0 +: 1]; +assign qsfp0_resetl = qsfp_resetl[0 +: 1]; +assign qsfp0_lpmode = qsfp_lpmode[0 +: 1]; wire qsfp0_gtpowergood; @@ -1206,14 +1218,14 @@ qsfp0_cmac_inst ( /* * DRP */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy), + .drp_clk(qsfp_drp_clk[0 +: 1]), + .drp_rst(qsfp_drp_rst[0 +: 1]), + .drp_addr(qsfp_drp_addr[0*24 +: 24]), + .drp_di(qsfp_drp_di[0*16 +: 16]), + .drp_en(qsfp_drp_en[0 +: 1]), + .drp_we(qsfp_drp_we[0 +: 1]), + .drp_do(qsfp_drp_do[0*16 +: 16]), + .drp_rdy(qsfp_drp_rdy[0 +: 1]), /* * Serial data @@ -1226,101 +1238,58 @@ qsfp0_cmac_inst ( /* * CMAC connections */ - .tx_clk(qsfp0_tx_clk_int), - .tx_rst(qsfp0_tx_rst_int), + .tx_clk(qsfp_tx_clk[0 +: 1]), + .tx_rst(qsfp_tx_rst[0 +: 1]), - .tx_axis_tdata(qsfp0_tx_axis_tdata_int), - .tx_axis_tkeep(qsfp0_tx_axis_tkeep_int), - .tx_axis_tvalid(qsfp0_tx_axis_tvalid_int), - .tx_axis_tready(qsfp0_tx_axis_tready_int), - .tx_axis_tlast(qsfp0_tx_axis_tlast_int), - .tx_axis_tuser(qsfp0_tx_axis_tuser_int), + .tx_axis_tdata(qsfp_tx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .tx_axis_tkeep(qsfp_tx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .tx_axis_tvalid(qsfp_tx_axis_tvalid[0 +: 1]), + .tx_axis_tready(qsfp_tx_axis_tready[0 +: 1]), + .tx_axis_tlast(qsfp_tx_axis_tlast[0 +: 1]), + .tx_axis_tuser(qsfp_tx_axis_tuser[0*(16+1) +: (16+1)]), - .tx_ptp_time(qsfp0_tx_ptp_time_int), - .tx_ptp_ts(qsfp0_tx_ptp_ts_int), - .tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), - .tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), + .tx_ptp_time(qsfp_tx_ptp_time[0*80 +: 80]), + .tx_ptp_ts(qsfp_tx_ptp_ts[0*80 +: 80]), + .tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag[0*16 +: 16]), + .tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid[0 +: 1]), - .tx_enable(qsfp0_tx_enable), - .tx_lfc_en(qsfp0_tx_lfc_en), - .tx_lfc_req(qsfp0_tx_lfc_req), - .tx_pfc_en(qsfp0_tx_pfc_en), - .tx_pfc_req(qsfp0_tx_pfc_req), + .tx_enable(qsfp_tx_enable[0 +: 1]), + .tx_lfc_en(qsfp_tx_lfc_en[0 +: 1]), + .tx_lfc_req(qsfp_tx_lfc_req[0 +: 1]), + .tx_pfc_en(qsfp_tx_pfc_en[0*8 +: 8]), + .tx_pfc_req(qsfp_tx_pfc_req[0*8 +: 8]), - .rx_clk(qsfp0_rx_clk_int), - .rx_rst(qsfp0_rx_rst_int), + .rx_clk(qsfp_rx_clk[0 +: 1]), + .rx_rst(qsfp_rx_rst[0 +: 1]), - .rx_axis_tdata(qsfp0_rx_axis_tdata_int), - .rx_axis_tkeep(qsfp0_rx_axis_tkeep_int), - .rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), - .rx_axis_tlast(qsfp0_rx_axis_tlast_int), - .rx_axis_tuser(qsfp0_rx_axis_tuser_int), + .rx_axis_tdata(qsfp_rx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .rx_axis_tkeep(qsfp_rx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .rx_axis_tvalid(qsfp_rx_axis_tvalid[0 +: 1]), + .rx_axis_tlast(qsfp_rx_axis_tlast[0 +: 1]), + .rx_axis_tuser(qsfp_rx_axis_tuser[0*(80+1) +: (80+1)]), - .rx_ptp_time(qsfp0_rx_ptp_time_int), + .rx_ptp_time(qsfp_rx_ptp_time[0*80 +: 80]), - .rx_enable(qsfp0_rx_enable), - .rx_status(qsfp0_rx_status), - .rx_lfc_en(qsfp0_rx_lfc_en), - .rx_lfc_req(qsfp0_rx_lfc_req), - .rx_lfc_ack(qsfp0_rx_lfc_ack), - .rx_pfc_en(qsfp0_rx_pfc_en), - .rx_pfc_req(qsfp0_rx_pfc_req), - .rx_pfc_ack(qsfp0_rx_pfc_ack) + .rx_enable(qsfp_rx_enable[0 +: 1]), + .rx_status(qsfp_rx_status[0 +: 1]), + .rx_lfc_en(qsfp_rx_lfc_en[0 +: 1]), + .rx_lfc_req(qsfp_rx_lfc_req[0 +: 1]), + .rx_lfc_ack(qsfp_rx_lfc_ack[0 +: 1]), + .rx_pfc_en(qsfp_rx_pfc_en[0*8 +: 8]), + .rx_pfc_req(qsfp_rx_pfc_req[0*8 +: 8]), + .rx_pfc_ack(qsfp_rx_pfc_ack[0*8 +: 8]) ); // QSFP1 CMAC assign qsfp1_refclk_reset = qsfp_refclk_reset_reg; assign qsfp1_fs = 2'b10; -wire qsfp1_tx_clk_int; -wire qsfp1_tx_rst_int; +assign qsfp_drp_clk[1 +: 1] = clk_125mhz_int; +assign qsfp_drp_rst[1 +: 1] = rst_125mhz_int; -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep_int; -wire qsfp1_tx_axis_tvalid_int; -wire qsfp1_tx_axis_tready_int; -wire qsfp1_tx_axis_tlast_int; -wire [16+1-1:0] qsfp1_tx_axis_tuser_int; - -wire [79:0] qsfp1_tx_ptp_time_int; -wire [79:0] qsfp1_tx_ptp_ts_int; -wire [15:0] qsfp1_tx_ptp_ts_tag_int; -wire qsfp1_tx_ptp_ts_valid_int; - -wire qsfp1_rx_clk_int; -wire qsfp1_rx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep_int; -wire qsfp1_rx_axis_tvalid_int; -wire qsfp1_rx_axis_tlast_int; -wire [80+1-1:0] qsfp1_rx_axis_tuser_int; - -wire [79:0] qsfp1_rx_ptp_time_int; - -wire qsfp1_drp_clk = clk_125mhz_int; -wire qsfp1_drp_rst = rst_125mhz_int; -wire [23:0] qsfp1_drp_addr; -wire [15:0] qsfp1_drp_di; -wire qsfp1_drp_en; -wire qsfp1_drp_we; -wire [15:0] qsfp1_drp_do; -wire qsfp1_drp_rdy; - -wire qsfp1_tx_enable; -wire qsfp1_tx_lfc_en; -wire qsfp1_tx_lfc_req; -wire [7:0] qsfp1_tx_pfc_en; -wire [7:0] qsfp1_tx_pfc_req; - -wire qsfp1_rx_enable; -wire qsfp1_rx_status; -wire qsfp1_rx_lfc_en; -wire qsfp1_rx_lfc_req; -wire qsfp1_rx_lfc_ack; -wire [7:0] qsfp1_rx_pfc_en; -wire [7:0] qsfp1_rx_pfc_req; -wire [7:0] qsfp1_rx_pfc_ack; +assign qsfp1_modsell = qsfp_modsell[1 +: 1]; +assign qsfp1_resetl = qsfp_resetl[1 +: 1]; +assign qsfp1_lpmode = qsfp_lpmode[1 +: 1]; wire qsfp1_gtpowergood; @@ -1378,14 +1347,14 @@ qsfp1_cmac_inst ( /* * DRP */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy), + .drp_clk(qsfp_drp_clk[1 +: 1]), + .drp_rst(qsfp_drp_rst[1 +: 1]), + .drp_addr(qsfp_drp_addr[1*24 +: 24]), + .drp_di(qsfp_drp_di[1*16 +: 16]), + .drp_en(qsfp_drp_en[1 +: 1]), + .drp_we(qsfp_drp_we[1 +: 1]), + .drp_do(qsfp_drp_do[1*16 +: 16]), + .drp_rdy(qsfp_drp_rdy[1 +: 1]), /* * Serial data @@ -1398,46 +1367,46 @@ qsfp1_cmac_inst ( /* * CMAC connections */ - .tx_clk(qsfp1_tx_clk_int), - .tx_rst(qsfp1_tx_rst_int), + .tx_clk(qsfp_tx_clk[1 +: 1]), + .tx_rst(qsfp_tx_rst[1 +: 1]), - .tx_axis_tdata(qsfp1_tx_axis_tdata_int), - .tx_axis_tkeep(qsfp1_tx_axis_tkeep_int), - .tx_axis_tvalid(qsfp1_tx_axis_tvalid_int), - .tx_axis_tready(qsfp1_tx_axis_tready_int), - .tx_axis_tlast(qsfp1_tx_axis_tlast_int), - .tx_axis_tuser(qsfp1_tx_axis_tuser_int), + .tx_axis_tdata(qsfp_tx_axis_tdata[1*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .tx_axis_tkeep(qsfp_tx_axis_tkeep[1*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .tx_axis_tvalid(qsfp_tx_axis_tvalid[1 +: 1]), + .tx_axis_tready(qsfp_tx_axis_tready[1 +: 1]), + .tx_axis_tlast(qsfp_tx_axis_tlast[1 +: 1]), + .tx_axis_tuser(qsfp_tx_axis_tuser[1*(16+1) +: (16+1)]), - .tx_ptp_time(qsfp1_tx_ptp_time_int), - .tx_ptp_ts(qsfp1_tx_ptp_ts_int), - .tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), - .tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), + .tx_ptp_time(qsfp_tx_ptp_time[1*80 +: 80]), + .tx_ptp_ts(qsfp_tx_ptp_ts[1*80 +: 80]), + .tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag[1*16 +: 16]), + .tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid[1 +: 1]), - .tx_enable(qsfp1_tx_enable), - .tx_lfc_en(qsfp1_tx_lfc_en), - .tx_lfc_req(qsfp1_tx_lfc_req), - .tx_pfc_en(qsfp1_tx_pfc_en), - .tx_pfc_req(qsfp1_tx_pfc_req), + .tx_enable(qsfp_tx_enable[1 +: 1]), + .tx_lfc_en(qsfp_tx_lfc_en[1 +: 1]), + .tx_lfc_req(qsfp_tx_lfc_req[1 +: 1]), + .tx_pfc_en(qsfp_tx_pfc_en[1*8 +: 8]), + .tx_pfc_req(qsfp_tx_pfc_req[1*8 +: 8]), - .rx_clk(qsfp1_rx_clk_int), - .rx_rst(qsfp1_rx_rst_int), + .rx_clk(qsfp_rx_clk[1 +: 1]), + .rx_rst(qsfp_rx_rst[1 +: 1]), - .rx_axis_tdata(qsfp1_rx_axis_tdata_int), - .rx_axis_tkeep(qsfp1_rx_axis_tkeep_int), - .rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), - .rx_axis_tlast(qsfp1_rx_axis_tlast_int), - .rx_axis_tuser(qsfp1_rx_axis_tuser_int), + .rx_axis_tdata(qsfp_rx_axis_tdata[1*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .rx_axis_tkeep(qsfp_rx_axis_tkeep[1*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .rx_axis_tvalid(qsfp_rx_axis_tvalid[1 +: 1]), + .rx_axis_tlast(qsfp_rx_axis_tlast[1 +: 1]), + .rx_axis_tuser(qsfp_rx_axis_tuser[1*(80+1) +: (80+1)]), - .rx_ptp_time(qsfp1_rx_ptp_time_int), + .rx_ptp_time(qsfp_rx_ptp_time[1*80 +: 80]), - .rx_enable(qsfp1_rx_enable), - .rx_status(qsfp1_rx_status), - .rx_lfc_en(qsfp1_rx_lfc_en), - .rx_lfc_req(qsfp1_rx_lfc_req), - .rx_lfc_ack(qsfp1_rx_lfc_ack), - .rx_pfc_en(qsfp1_rx_pfc_en), - .rx_pfc_req(qsfp1_rx_pfc_req), - .rx_pfc_ack(qsfp1_rx_pfc_ack) + .rx_enable(qsfp_rx_enable[1 +: 1]), + .rx_status(qsfp_rx_status[1 +: 1]), + .rx_lfc_en(qsfp_rx_lfc_en[1 +: 1]), + .rx_lfc_req(qsfp_rx_lfc_req[1 +: 1]), + .rx_lfc_ack(qsfp_rx_lfc_ack[1 +: 1]), + .rx_pfc_en(qsfp_rx_pfc_en[1*8 +: 8]), + .rx_pfc_req(qsfp_rx_pfc_req[1*8 +: 8]), + .rx_pfc_ack(qsfp_rx_pfc_ack[1*8 +: 8]) ); wire ptp_clk; @@ -1451,8 +1420,8 @@ assign ptp_sample_clk = clk_125mhz_int; wire [2:0] led_int; assign led[0] = led_int[0]; // red -assign led[1] = qsfp1_rx_status; // yellow -assign led[2] = qsfp0_rx_status; // green +assign led[1] = qsfp_rx_status[1]; // yellow +assign led[2] = qsfp_rx_status[0]; // green // DDR4 wire [DDR_CH-1:0] ddr_clk; @@ -2019,6 +1988,8 @@ fpga_core #( .RELEASE_INFO(RELEASE_INFO), // Board configuration + .QSFP_CNT(QSFP_CNT), + .CH_CNT(QSFP_CNT*4), .CMS_ENABLE(CMS_ENABLE), // Structural configuration @@ -2265,109 +2236,57 @@ core_inst ( /* * Ethernet: QSFP28 */ - .qsfp0_tx_clk(qsfp0_tx_clk_int), - .qsfp0_tx_rst(qsfp0_tx_rst_int), - .qsfp0_tx_axis_tdata(qsfp0_tx_axis_tdata_int), - .qsfp0_tx_axis_tkeep(qsfp0_tx_axis_tkeep_int), - .qsfp0_tx_axis_tvalid(qsfp0_tx_axis_tvalid_int), - .qsfp0_tx_axis_tready(qsfp0_tx_axis_tready_int), - .qsfp0_tx_axis_tlast(qsfp0_tx_axis_tlast_int), - .qsfp0_tx_axis_tuser(qsfp0_tx_axis_tuser_int), - .qsfp0_tx_ptp_time(qsfp0_tx_ptp_time_int), - .qsfp0_tx_ptp_ts(qsfp0_tx_ptp_ts_int), - .qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), - .qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), + .qsfp_tx_clk(qsfp_tx_clk), + .qsfp_tx_rst(qsfp_tx_rst), + .qsfp_tx_axis_tdata(qsfp_tx_axis_tdata), + .qsfp_tx_axis_tkeep(qsfp_tx_axis_tkeep), + .qsfp_tx_axis_tvalid(qsfp_tx_axis_tvalid), + .qsfp_tx_axis_tready(qsfp_tx_axis_tready), + .qsfp_tx_axis_tlast(qsfp_tx_axis_tlast), + .qsfp_tx_axis_tuser(qsfp_tx_axis_tuser), + .qsfp_tx_ptp_time(qsfp_tx_ptp_time), + .qsfp_tx_ptp_ts(qsfp_tx_ptp_ts), + .qsfp_tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag), + .qsfp_tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid), - .qsfp0_tx_enable(qsfp0_tx_enable), - .qsfp0_tx_lfc_en(qsfp0_tx_lfc_en), - .qsfp0_tx_lfc_req(qsfp0_tx_lfc_req), - .qsfp0_tx_pfc_en(qsfp0_tx_pfc_en), - .qsfp0_tx_pfc_req(qsfp0_tx_pfc_req), + .qsfp_tx_enable(qsfp_tx_enable), + .qsfp_tx_lfc_en(qsfp_tx_lfc_en), + .qsfp_tx_lfc_req(qsfp_tx_lfc_req), + .qsfp_tx_pfc_en(qsfp_tx_pfc_en), + .qsfp_tx_pfc_req(qsfp_tx_pfc_req), - .qsfp0_rx_clk(qsfp0_rx_clk_int), - .qsfp0_rx_rst(qsfp0_rx_rst_int), - .qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int), - .qsfp0_rx_axis_tkeep(qsfp0_rx_axis_tkeep_int), - .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), - .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int), - .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), + .qsfp_rx_clk(qsfp_rx_clk), + .qsfp_rx_rst(qsfp_rx_rst), + .qsfp_rx_axis_tdata(qsfp_rx_axis_tdata), + .qsfp_rx_axis_tkeep(qsfp_rx_axis_tkeep), + .qsfp_rx_axis_tvalid(qsfp_rx_axis_tvalid), + .qsfp_rx_axis_tlast(qsfp_rx_axis_tlast), + .qsfp_rx_axis_tuser(qsfp_rx_axis_tuser), + .qsfp_rx_ptp_time(qsfp_rx_ptp_time), - .qsfp0_rx_enable(qsfp0_rx_enable), - .qsfp0_rx_status(qsfp0_rx_status), - .qsfp0_rx_lfc_en(qsfp0_rx_lfc_en), - .qsfp0_rx_lfc_req(qsfp0_rx_lfc_req), - .qsfp0_rx_lfc_ack(qsfp0_rx_lfc_ack), - .qsfp0_rx_pfc_en(qsfp0_rx_pfc_en), - .qsfp0_rx_pfc_req(qsfp0_rx_pfc_req), - .qsfp0_rx_pfc_ack(qsfp0_rx_pfc_ack), + .qsfp_rx_enable(qsfp_rx_enable), + .qsfp_rx_status(qsfp_rx_status), + .qsfp_rx_lfc_en(qsfp_rx_lfc_en), + .qsfp_rx_lfc_req(qsfp_rx_lfc_req), + .qsfp_rx_lfc_ack(qsfp_rx_lfc_ack), + .qsfp_rx_pfc_en(qsfp_rx_pfc_en), + .qsfp_rx_pfc_req(qsfp_rx_pfc_req), + .qsfp_rx_pfc_ack(qsfp_rx_pfc_ack), - .qsfp0_drp_clk(qsfp0_drp_clk), - .qsfp0_drp_rst(qsfp0_drp_rst), - .qsfp0_drp_addr(qsfp0_drp_addr), - .qsfp0_drp_di(qsfp0_drp_di), - .qsfp0_drp_en(qsfp0_drp_en), - .qsfp0_drp_we(qsfp0_drp_we), - .qsfp0_drp_do(qsfp0_drp_do), - .qsfp0_drp_rdy(qsfp0_drp_rdy), + .qsfp_drp_clk(qsfp_drp_clk), + .qsfp_drp_rst(qsfp_drp_rst), + .qsfp_drp_addr(qsfp_drp_addr), + .qsfp_drp_di(qsfp_drp_di), + .qsfp_drp_en(qsfp_drp_en), + .qsfp_drp_we(qsfp_drp_we), + .qsfp_drp_do(qsfp_drp_do), + .qsfp_drp_rdy(qsfp_drp_rdy), - .qsfp0_modprsl(qsfp0_modprsl_int), - .qsfp0_modsell(qsfp0_modsell), - .qsfp0_resetl(qsfp0_resetl), - .qsfp0_intl(qsfp0_intl_int), - .qsfp0_lpmode(qsfp0_lpmode), - - .qsfp1_tx_clk(qsfp1_tx_clk_int), - .qsfp1_tx_rst(qsfp1_tx_rst_int), - .qsfp1_tx_axis_tdata(qsfp1_tx_axis_tdata_int), - .qsfp1_tx_axis_tkeep(qsfp1_tx_axis_tkeep_int), - .qsfp1_tx_axis_tvalid(qsfp1_tx_axis_tvalid_int), - .qsfp1_tx_axis_tready(qsfp1_tx_axis_tready_int), - .qsfp1_tx_axis_tlast(qsfp1_tx_axis_tlast_int), - .qsfp1_tx_axis_tuser(qsfp1_tx_axis_tuser_int), - .qsfp1_tx_ptp_time(qsfp1_tx_ptp_time_int), - .qsfp1_tx_ptp_ts(qsfp1_tx_ptp_ts_int), - .qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), - .qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), - - .qsfp1_tx_enable(qsfp1_tx_enable), - .qsfp1_tx_lfc_en(qsfp1_tx_lfc_en), - .qsfp1_tx_lfc_req(qsfp1_tx_lfc_req), - .qsfp1_tx_pfc_en(qsfp1_tx_pfc_en), - .qsfp1_tx_pfc_req(qsfp1_tx_pfc_req), - - .qsfp1_rx_clk(qsfp1_rx_clk_int), - .qsfp1_rx_rst(qsfp1_rx_rst_int), - .qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int), - .qsfp1_rx_axis_tkeep(qsfp1_rx_axis_tkeep_int), - .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), - .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), - .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), - - .qsfp1_rx_enable(qsfp1_rx_enable), - .qsfp1_rx_status(qsfp1_rx_status), - .qsfp1_rx_lfc_en(qsfp1_rx_lfc_en), - .qsfp1_rx_lfc_req(qsfp1_rx_lfc_req), - .qsfp1_rx_lfc_ack(qsfp1_rx_lfc_ack), - .qsfp1_rx_pfc_en(qsfp1_rx_pfc_en), - .qsfp1_rx_pfc_req(qsfp1_rx_pfc_req), - .qsfp1_rx_pfc_ack(qsfp1_rx_pfc_ack), - - .qsfp1_drp_clk(qsfp1_drp_clk), - .qsfp1_drp_rst(qsfp1_drp_rst), - .qsfp1_drp_addr(qsfp1_drp_addr), - .qsfp1_drp_di(qsfp1_drp_di), - .qsfp1_drp_en(qsfp1_drp_en), - .qsfp1_drp_we(qsfp1_drp_we), - .qsfp1_drp_do(qsfp1_drp_do), - .qsfp1_drp_rdy(qsfp1_drp_rdy), - - .qsfp1_modprsl(qsfp1_modprsl_int), - .qsfp1_modsell(qsfp1_modsell), - .qsfp1_resetl(qsfp1_resetl), - .qsfp1_intl(qsfp1_intl_int), - .qsfp1_lpmode(qsfp1_lpmode), + .qsfp_modprsl(qsfp_modprsl_int), + .qsfp_modsell(qsfp_modsell), + .qsfp_resetl(qsfp_resetl), + .qsfp_intl(qsfp_intl_int), + .qsfp_lpmode(qsfp_lpmode), /* * DDR diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v index 141ad5b6c..bdfe9c74d 100644 --- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v @@ -25,6 +25,8 @@ module fpga_core # parameter RELEASE_INFO = 32'h00000000, // Board configuration + parameter QSFP_CNT = 2, + parameter CH_CNT = QSFP_CNT*4, parameter CMS_ENABLE = 1, // Structural configuration @@ -271,117 +273,61 @@ module fpga_core # /* * Ethernet: QSFP28 */ - input wire qsfp0_tx_clk, - input wire qsfp0_tx_rst, + input wire [QSFP_CNT-1:0] qsfp_tx_clk, + input wire [QSFP_CNT-1:0] qsfp_tx_rst, - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep, - output wire qsfp0_tx_axis_tvalid, - input wire qsfp0_tx_axis_tready, - output wire qsfp0_tx_axis_tlast, - output wire [16+1-1:0] qsfp0_tx_axis_tuser, + output wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_tx_axis_tdata, + output wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_tx_axis_tkeep, + output wire [QSFP_CNT-1:0] qsfp_tx_axis_tvalid, + input wire [QSFP_CNT-1:0] qsfp_tx_axis_tready, + output wire [QSFP_CNT-1:0] qsfp_tx_axis_tlast, + output wire [QSFP_CNT*(16+1)-1:0] qsfp_tx_axis_tuser, - output wire [79:0] qsfp0_tx_ptp_time, - input wire [79:0] qsfp0_tx_ptp_ts, - input wire [15:0] qsfp0_tx_ptp_ts_tag, - input wire qsfp0_tx_ptp_ts_valid, + output wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_time, + input wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_ts, + input wire [QSFP_CNT*16-1:0] qsfp_tx_ptp_ts_tag, + input wire [QSFP_CNT-1:0] qsfp_tx_ptp_ts_valid, - output wire qsfp0_tx_enable, - output wire qsfp0_tx_lfc_en, - output wire qsfp0_tx_lfc_req, - output wire [7:0] qsfp0_tx_pfc_en, - output wire [7:0] qsfp0_tx_pfc_req, + output wire [QSFP_CNT-1:0] qsfp_tx_enable, + output wire [QSFP_CNT-1:0] qsfp_tx_lfc_en, + output wire [QSFP_CNT-1:0] qsfp_tx_lfc_req, + output wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_en, + output wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_req, - input wire qsfp0_rx_clk, - input wire qsfp0_rx_rst, + input wire [QSFP_CNT-1:0] qsfp_rx_clk, + input wire [QSFP_CNT-1:0] qsfp_rx_rst, - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep, - input wire qsfp0_rx_axis_tvalid, - input wire qsfp0_rx_axis_tlast, - input wire [80+1-1:0] qsfp0_rx_axis_tuser, + input wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_rx_axis_tdata, + input wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_rx_axis_tkeep, + input wire [QSFP_CNT-1:0] qsfp_rx_axis_tvalid, + input wire [QSFP_CNT-1:0] qsfp_rx_axis_tlast, + input wire [QSFP_CNT*(80+1)-1:0] qsfp_rx_axis_tuser, - output wire [79:0] qsfp0_rx_ptp_time, + output wire [QSFP_CNT*80-1:0] qsfp_rx_ptp_time, - output wire qsfp0_rx_enable, - input wire qsfp0_rx_status, - output wire qsfp0_rx_lfc_en, - input wire qsfp0_rx_lfc_req, - output wire qsfp0_rx_lfc_ack, - output wire [7:0] qsfp0_rx_pfc_en, - input wire [7:0] qsfp0_rx_pfc_req, - output wire [7:0] qsfp0_rx_pfc_ack, + output wire [QSFP_CNT-1:0] qsfp_rx_enable, + input wire [QSFP_CNT-1:0] qsfp_rx_status, + output wire [QSFP_CNT-1:0] qsfp_rx_lfc_en, + input wire [QSFP_CNT-1:0] qsfp_rx_lfc_req, + output wire [QSFP_CNT-1:0] qsfp_rx_lfc_ack, + output wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_en, + input wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_req, + output wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_ack, - input wire qsfp0_drp_clk, - input wire qsfp0_drp_rst, - output wire [23:0] qsfp0_drp_addr, - output wire [15:0] qsfp0_drp_di, - output wire qsfp0_drp_en, - output wire qsfp0_drp_we, - input wire [15:0] qsfp0_drp_do, - input wire qsfp0_drp_rdy, + input wire [QSFP_CNT-1:0] qsfp_drp_clk, + input wire [QSFP_CNT-1:0] qsfp_drp_rst, + output wire [QSFP_CNT*24-1:0] qsfp_drp_addr, + output wire [QSFP_CNT*16-1:0] qsfp_drp_di, + output wire [QSFP_CNT-1:0] qsfp_drp_en, + output wire [QSFP_CNT-1:0] qsfp_drp_we, + input wire [QSFP_CNT*16-1:0] qsfp_drp_do, + input wire [QSFP_CNT-1:0] qsfp_drp_rdy, - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - - input wire qsfp1_tx_clk, - input wire qsfp1_tx_rst, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep, - output wire qsfp1_tx_axis_tvalid, - input wire qsfp1_tx_axis_tready, - output wire qsfp1_tx_axis_tlast, - output wire [16+1-1:0] qsfp1_tx_axis_tuser, - - output wire [79:0] qsfp1_tx_ptp_time, - input wire [79:0] qsfp1_tx_ptp_ts, - input wire [15:0] qsfp1_tx_ptp_ts_tag, - input wire qsfp1_tx_ptp_ts_valid, - - output wire qsfp1_tx_enable, - output wire qsfp1_tx_lfc_en, - output wire qsfp1_tx_lfc_req, - output wire [7:0] qsfp1_tx_pfc_en, - output wire [7:0] qsfp1_tx_pfc_req, - - input wire qsfp1_rx_clk, - input wire qsfp1_rx_rst, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep, - input wire qsfp1_rx_axis_tvalid, - input wire qsfp1_rx_axis_tlast, - input wire [80+1-1:0] qsfp1_rx_axis_tuser, - - output wire [79:0] qsfp1_rx_ptp_time, - - output wire qsfp1_rx_enable, - input wire qsfp1_rx_status, - output wire qsfp1_rx_lfc_en, - input wire qsfp1_rx_lfc_req, - output wire qsfp1_rx_lfc_ack, - output wire [7:0] qsfp1_rx_pfc_en, - input wire [7:0] qsfp1_rx_pfc_req, - output wire [7:0] qsfp1_rx_pfc_ack, - - input wire qsfp1_drp_clk, - input wire qsfp1_drp_rst, - output wire [23:0] qsfp1_drp_addr, - output wire [15:0] qsfp1_drp_di, - output wire qsfp1_drp_en, - output wire qsfp1_drp_we, - input wire [15:0] qsfp1_drp_do, - input wire qsfp1_drp_rdy, - - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, + output wire [QSFP_CNT-1:0] qsfp_modsell, + output wire [QSFP_CNT-1:0] qsfp_resetl, + input wire [QSFP_CNT-1:0] qsfp_modprsl, + input wire [QSFP_CNT-1:0] qsfp_intl, + output wire [QSFP_CNT-1:0] qsfp_lpmode, /* * DDR @@ -476,16 +422,17 @@ parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3 localparam RB_BASE_ADDR = 16'h1000; localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; -localparam RB_DRP_QSFP0_BASE = RB_BASE_ADDR + 16'h60; -localparam RB_DRP_QSFP1_BASE = RB_DRP_QSFP0_BASE + 16'h20; +localparam RB_DRP_QSFP_BASE = RB_BASE_ADDR + 16'h60; initial begin - if (PORT_COUNT > 2) begin + if (PORT_COUNT > QSFP_CNT) begin $error("Error: Max port count exceeded (instance %m)"); $finish; end end +genvar n; + // PTP wire ptp_td_sd; wire ptp_pps; @@ -515,27 +462,18 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; wire ctrl_reg_rd_wait; wire ctrl_reg_rd_ack; -wire qsfp0_drp_reg_wr_wait; -wire qsfp0_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp0_drp_reg_rd_data; -wire qsfp0_drp_reg_rd_wait; -wire qsfp0_drp_reg_rd_ack; - -wire qsfp1_drp_reg_wr_wait; -wire qsfp1_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data; -wire qsfp1_drp_reg_rd_wait; -wire qsfp1_drp_reg_rd_ack; +wire qsfp_drp_reg_wr_wait[0:QSFP_CNT-1]; +wire qsfp_drp_reg_wr_ack[0:QSFP_CNT-1]; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_drp_reg_rd_data[0:QSFP_CNT-1]; +wire qsfp_drp_reg_rd_wait[0:QSFP_CNT-1]; +wire qsfp_drp_reg_rd_ack[0:QSFP_CNT-1]; reg ctrl_reg_wr_ack_reg = 1'b0; reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; reg ctrl_reg_rd_ack_reg = 1'b0; -reg qsfp0_reset_reg = 1'b0; -reg qsfp1_reset_reg = 1'b0; - -reg qsfp0_lpmode_reg = 1'b0; -reg qsfp1_lpmode_reg = 1'b0; +reg [QSFP_CNT-1:0] qsfp_reset_reg = {QSFP_CNT{1'b0}}; +reg [QSFP_CNT-1:0] qsfp_lpmode_reg = {QSFP_CNT{1'b0}}; reg i2c_scl_o_reg = 1'b1; reg i2c_sda_o_reg = 1'b1; @@ -554,20 +492,39 @@ reg [3:0] m_axil_cms_wstrb_reg = 4'b0000; reg m_axil_cms_wvalid_reg = 1'b0; reg m_axil_cms_arvalid_reg = 1'b0; -assign ctrl_reg_wr_wait = qsfp0_drp_reg_wr_wait | qsfp1_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp0_drp_reg_wr_ack | qsfp1_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp0_drp_reg_rd_data | qsfp1_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp0_drp_reg_rd_wait | qsfp1_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp0_drp_reg_rd_ack | qsfp1_drp_reg_rd_ack; +reg ctrl_reg_wr_wait_cmb; +reg ctrl_reg_wr_ack_cmb; +reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_cmb; +reg ctrl_reg_rd_wait_cmb; +reg ctrl_reg_rd_ack_cmb; -assign qsfp0_modsell = 1'b0; -assign qsfp1_modsell = 1'b0; +assign ctrl_reg_wr_wait = ctrl_reg_wr_wait_cmb; +assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_cmb; +assign ctrl_reg_rd_data = ctrl_reg_rd_data_cmb; +assign ctrl_reg_rd_wait = ctrl_reg_rd_wait_cmb; +assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_cmb; -assign qsfp0_resetl = !qsfp0_reset_reg; -assign qsfp1_resetl = !qsfp1_reset_reg; +integer k; -assign qsfp0_lpmode = qsfp0_lpmode_reg; -assign qsfp1_lpmode = qsfp1_lpmode_reg; +always @* begin + ctrl_reg_wr_wait_cmb = 1'b0; + ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_reg; + ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_reg; + ctrl_reg_rd_wait_cmb = 1'b0; + ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_reg; + + for (k = 0; k < QSFP_CNT; k = k + 1) begin + ctrl_reg_wr_wait_cmb = ctrl_reg_wr_wait_cmb | qsfp_drp_reg_wr_wait[k]; + ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_cmb | qsfp_drp_reg_wr_ack[k]; + ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_cmb | qsfp_drp_reg_rd_data[k]; + ctrl_reg_rd_wait_cmb = ctrl_reg_rd_wait_cmb | qsfp_drp_reg_rd_wait[k]; + ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_cmb | qsfp_drp_reg_rd_ack[k]; + end +end + +assign qsfp_modsell = {QSFP_CNT{1'b0}}; +assign qsfp_resetl = ~qsfp_reset_reg; +assign qsfp_lpmode = qsfp_lpmode_reg; assign i2c_scl_o = i2c_scl_o_reg; assign i2c_scl_t = i2c_scl_o_reg; @@ -595,6 +552,8 @@ assign m_axil_cms_arprot = 3'b000; assign m_axil_cms_arvalid = m_axil_cms_arvalid_reg; assign m_axil_cms_rready = 1'b1; +integer i; + always @(posedge clk_250mhz) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; @@ -626,13 +585,11 @@ always @(posedge clk_250mhz) begin // XCVR GPIO RBB+8'h1C: begin // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - qsfp0_reset_reg <= ctrl_reg_wr_data[4]; - qsfp0_lpmode_reg <= ctrl_reg_wr_data[5]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp1_reset_reg <= ctrl_reg_wr_data[12]; - qsfp1_lpmode_reg <= ctrl_reg_wr_data[13]; + for (i = 0; i < QSFP_CNT; i = i + 1) begin + if (ctrl_reg_wr_strb[i]) begin + qsfp_reset_reg[i] <= ctrl_reg_wr_data[i*8+4]; + qsfp_lpmode_reg[i] <= ctrl_reg_wr_data[i*8+5]; + end end end // QSPI flash @@ -695,14 +652,12 @@ always @(posedge clk_250mhz) begin RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // XCVR GPIO: Next header RBB+8'h1C: begin // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !qsfp0_modprsl; - ctrl_reg_rd_data_reg[1] <= !qsfp0_intl; - ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg; - ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg; - ctrl_reg_rd_data_reg[8] <= !qsfp1_modprsl; - ctrl_reg_rd_data_reg[9] <= !qsfp1_intl; - ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg; - ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg; + for (i = 0; i < QSFP_CNT; i = i + 1) begin + ctrl_reg_rd_data_reg[i*8+0] <= !qsfp_modprsl[i]; + ctrl_reg_rd_data_reg[i*8+1] <= !qsfp_intl[i]; + ctrl_reg_rd_data_reg[i*8+4] <= qsfp_reset_reg[i]; + ctrl_reg_rd_data_reg[i*8+5] <= qsfp_lpmode_reg[i]; + end end // QSPI flash RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type @@ -725,7 +680,7 @@ always @(posedge clk_250mhz) begin // Alveo BMC RBB+8'h40: ctrl_reg_rd_data_reg <= CMS_ENABLE ? 32'h0000C140 : 0; // BMC ctrl: Type RBB+8'h44: ctrl_reg_rd_data_reg <= CMS_ENABLE ? 32'h00000100 : 0; // BMC ctrl: Version - RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // BMC ctrl: Next header + RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_BASE; // BMC ctrl: Next header RBB+8'h4C: ctrl_reg_rd_data_reg <= CMS_ENABLE ? m_axil_cms_addr_reg : 0; // BMC ctrl: Addr RBB+8'h50: ctrl_reg_rd_data_reg <= CMS_ENABLE ? m_axil_cms_rdata : 0; // BMC ctrl: Data default: ctrl_reg_rd_ack_reg <= 1'b0; @@ -736,11 +691,8 @@ always @(posedge clk_250mhz) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_ack_reg <= 1'b0; - qsfp0_reset_reg <= 1'b0; - qsfp1_reset_reg <= 1'b0; - - qsfp0_lpmode_reg <= 1'b0; - qsfp1_lpmode_reg <= 1'b0; + qsfp_reset_reg <= {QSFP_CNT{1'b0}}; + qsfp_lpmode_reg <= {QSFP_CNT{1'b0}}; i2c_scl_o_reg <= 1'b1; i2c_sda_o_reg <= 1'b1; @@ -758,89 +710,55 @@ always @(posedge clk_250mhz) begin end end -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP0_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP1_BASE) -) -qsfp0_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), +generate - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp0_drp_reg_wr_wait), - .reg_wr_ack(qsfp0_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp0_drp_reg_rd_data), - .reg_rd_wait(qsfp0_drp_reg_rd_wait), - .reg_rd_ack(qsfp0_drp_reg_rd_ack), +for (n = 0; n < QSFP_CNT; n = n + 1) begin : qsfp - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy) -); + rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP_BASE + n*16'h20), + .RB_NEXT_PTR(RB_DRP_QSFP_BASE + (n+1)*16'h20) + ) + qsfp0_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP1_BASE), - .RB_NEXT_PTR(0) -) -qsfp1_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp_drp_reg_wr_wait[n]), + .reg_wr_ack(qsfp_drp_reg_wr_ack[n]), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp_drp_reg_rd_data[n]), + .reg_rd_wait(qsfp_drp_reg_rd_wait[n]), + .reg_rd_ack(qsfp_drp_reg_rd_ack[n]), - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp1_drp_reg_wr_wait), - .reg_wr_ack(qsfp1_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp1_drp_reg_rd_data), - .reg_rd_wait(qsfp1_drp_reg_rd_wait), - .reg_rd_ack(qsfp1_drp_reg_rd_ack), + /* + * DRP + */ + .drp_clk(qsfp_drp_clk[n +: 1]), + .drp_rst(qsfp_drp_rst[n +: 1]), + .drp_addr(qsfp_drp_addr[n*24 +: 24]), + .drp_di(qsfp_drp_di[n*16 +: 16]), + .drp_en(qsfp_drp_en[n +: 1]), + .drp_we(qsfp_drp_we[n +: 1]), + .drp_do(qsfp_drp_do[n*16 +: 16]), + .drp_rdy(qsfp_drp_rdy[n +: 1]) + ); - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy) -); +end + +endgenerate assign led[0] = ptp_pps_str; assign led[2:1] = 0; @@ -896,18 +814,28 @@ wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; -wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_rx_ptp_time_int; +wire [QSFP_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_tx_axis_tuser_int; +wire [QSFP_CNT*PTP_TS_WIDTH-1:0] qsfp_tx_ptp_time_int; +wire [QSFP_CNT*PTP_TS_WIDTH-1:0] qsfp_tx_ptp_ts_int; -assign qsfp0_tx_ptp_time = qsfp0_tx_ptp_time_int >> 16; -assign qsfp1_tx_ptp_time = qsfp1_tx_ptp_time_int >> 16; -assign qsfp0_rx_ptp_time = qsfp0_rx_ptp_time_int >> 16; -assign qsfp1_rx_ptp_time = qsfp1_rx_ptp_time_int >> 16; +wire [QSFP_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_rx_axis_tuser_int; +wire [QSFP_CNT*PTP_TS_WIDTH-1:0] qsfp_rx_ptp_time_int; + +generate + +for (n = 0; n < QSFP_CNT; n = n + 1) begin + assign qsfp_tx_axis_tuser_int[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH] = qsfp_tx_axis_tuser[n*(16+1) +: 16+1]; + assign qsfp_tx_ptp_time[n*80 +: 80] = qsfp_tx_ptp_time_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] >> 16; + assign qsfp_tx_ptp_ts_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {qsfp_tx_ptp_ts[n*80 +: 80], 16'd0}; + + assign qsfp_rx_axis_tuser_int[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = {qsfp_rx_axis_tuser[n*81+1 +: 80], 16'd0, qsfp_rx_axis_tuser[n*81+0 +: 1]}; + assign qsfp_rx_ptp_time[n*80 +: 80] = qsfp_rx_ptp_time_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] >> 16; +end + +endgenerate mqnic_port_map_mac_axis #( - .MAC_COUNT(2), + .MAC_COUNT(QSFP_CNT), .PORT_MASK(PORT_MASK), .PORT_GROUP_SIZE(1), @@ -925,56 +853,56 @@ mqnic_port_map_mac_axis #( ) mqnic_port_map_mac_axis_inst ( // towards MAC - .mac_tx_clk({qsfp1_tx_clk, qsfp0_tx_clk}), - .mac_tx_rst({qsfp1_tx_rst, qsfp0_tx_rst}), + .mac_tx_clk(qsfp_tx_clk), + .mac_tx_rst(qsfp_tx_rst), - .mac_tx_ptp_clk(2'b00), - .mac_tx_ptp_rst(2'b00), - .mac_tx_ptp_ts_96({qsfp1_tx_ptp_time_int, qsfp0_tx_ptp_time_int}), + .mac_tx_ptp_clk({QSFP_CNT{1'b0}}), + .mac_tx_ptp_rst({QSFP_CNT{1'b0}}), + .mac_tx_ptp_ts_96(qsfp_tx_ptp_time_int), .mac_tx_ptp_ts_step(), - .m_axis_mac_tx_tdata({qsfp1_tx_axis_tdata, qsfp0_tx_axis_tdata}), - .m_axis_mac_tx_tkeep({qsfp1_tx_axis_tkeep, qsfp0_tx_axis_tkeep}), - .m_axis_mac_tx_tvalid({qsfp1_tx_axis_tvalid, qsfp0_tx_axis_tvalid}), - .m_axis_mac_tx_tready({qsfp1_tx_axis_tready, qsfp0_tx_axis_tready}), - .m_axis_mac_tx_tlast({qsfp1_tx_axis_tlast, qsfp0_tx_axis_tlast}), - .m_axis_mac_tx_tuser({qsfp1_tx_axis_tuser, qsfp0_tx_axis_tuser}), + .m_axis_mac_tx_tdata(qsfp_tx_axis_tdata), + .m_axis_mac_tx_tkeep(qsfp_tx_axis_tkeep), + .m_axis_mac_tx_tvalid(qsfp_tx_axis_tvalid), + .m_axis_mac_tx_tready(qsfp_tx_axis_tready), + .m_axis_mac_tx_tlast(qsfp_tx_axis_tlast), + .m_axis_mac_tx_tuser(qsfp_tx_axis_tuser), - .s_axis_mac_tx_ptp_ts({{qsfp1_tx_ptp_ts, 16'd0}, {qsfp0_tx_ptp_ts, 16'd0}}), - .s_axis_mac_tx_ptp_ts_tag({qsfp1_tx_ptp_ts_tag, qsfp0_tx_ptp_ts_tag}), - .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}), + .s_axis_mac_tx_ptp_ts(qsfp_tx_ptp_ts_int), + .s_axis_mac_tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag), + .s_axis_mac_tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid), .s_axis_mac_tx_ptp_ts_ready(), - .mac_tx_enable({qsfp1_tx_enable, qsfp0_tx_enable}), - .mac_tx_status(2'b11), - .mac_tx_lfc_en({qsfp1_tx_lfc_en, qsfp0_tx_lfc_en}), - .mac_tx_lfc_req({qsfp1_tx_lfc_req, qsfp0_tx_lfc_req}), - .mac_tx_pfc_en({qsfp1_tx_pfc_en, qsfp0_tx_pfc_en}), - .mac_tx_pfc_req({qsfp1_tx_pfc_req, qsfp0_tx_pfc_req}), + .mac_tx_enable(qsfp_tx_enable), + .mac_tx_status({QSFP_CNT{1'b1}}), + .mac_tx_lfc_en(qsfp_tx_lfc_en), + .mac_tx_lfc_req(qsfp_tx_lfc_req), + .mac_tx_pfc_en(qsfp_tx_pfc_en), + .mac_tx_pfc_req(qsfp_tx_pfc_req), - .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), - .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), + .mac_rx_clk(qsfp_rx_clk), + .mac_rx_rst(qsfp_rx_rst), - .mac_rx_ptp_clk(2'b00), - .mac_rx_ptp_rst(2'b00), - .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}), + .mac_rx_ptp_clk({QSFP_CNT{1'b0}}), + .mac_rx_ptp_rst({QSFP_CNT{1'b0}}), + .mac_rx_ptp_ts_96(qsfp_rx_ptp_time_int), .mac_rx_ptp_ts_step(), - .s_axis_mac_rx_tdata({qsfp1_rx_axis_tdata, qsfp0_rx_axis_tdata}), - .s_axis_mac_rx_tkeep({qsfp1_rx_axis_tkeep, qsfp0_rx_axis_tkeep}), - .s_axis_mac_rx_tvalid({qsfp1_rx_axis_tvalid, qsfp0_rx_axis_tvalid}), + .s_axis_mac_rx_tdata(qsfp_rx_axis_tdata), + .s_axis_mac_rx_tkeep(qsfp_rx_axis_tkeep), + .s_axis_mac_rx_tvalid(qsfp_rx_axis_tvalid), .s_axis_mac_rx_tready(), - .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}), - .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}), + .s_axis_mac_rx_tlast(qsfp_rx_axis_tlast), + .s_axis_mac_rx_tuser(qsfp_rx_axis_tuser_int), - .mac_rx_enable({qsfp1_rx_enable, qsfp0_rx_enable}), - .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}), - .mac_rx_lfc_en({qsfp1_rx_lfc_en, qsfp0_rx_lfc_en}), - .mac_rx_lfc_req({qsfp1_rx_lfc_req, qsfp0_rx_lfc_req}), - .mac_rx_lfc_ack({qsfp1_rx_lfc_ack, qsfp0_rx_lfc_ack}), - .mac_rx_pfc_en({qsfp1_rx_pfc_en, qsfp0_rx_pfc_en}), - .mac_rx_pfc_req({qsfp1_rx_pfc_req, qsfp0_rx_pfc_req}), - .mac_rx_pfc_ack({qsfp1_rx_pfc_ack, qsfp0_rx_pfc_ack}), + .mac_rx_enable(qsfp_rx_enable), + .mac_rx_status(qsfp_rx_status), + .mac_rx_lfc_en(qsfp_rx_lfc_en), + .mac_rx_lfc_req(qsfp_rx_lfc_req), + .mac_rx_lfc_ack(qsfp_rx_lfc_ack), + .mac_rx_pfc_en(qsfp_rx_pfc_en), + .mac_rx_pfc_req(qsfp_rx_pfc_req), + .mac_rx_pfc_ack(qsfp_rx_pfc_ack), // towards datapath .tx_clk(eth_tx_clk), diff --git a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile index dfa809ebf..748f3fd78 100644 --- a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile @@ -10,8 +10,9 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps DUT = fpga_core -TOPLEVEL = $(DUT) +TOPLEVEL = test_$(DUT) MODULE = test_$(DUT) +VERILOG_SOURCES += $(TOPLEVEL).v VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v diff --git a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py index 5e1e67e99..3ee7864d2 100644 --- a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -51,11 +51,11 @@ class TB(object): pcie_link_width=16, user_clk_frequency=250e6, alignment="dword", - cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, - cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, - rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, + cq_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, + cc_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, + rq_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, + rc_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, + rc_4tlp_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, pf_count=1, max_payload_size=1024, enable_client_tag=True, @@ -267,9 +267,9 @@ class TB(object): self.driver = mqnic.Driver() - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + self.dev.functions[0].configure_bar(0, 2**len(dut.uut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.uut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.uut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) dut.ptp_rst.setimmediatevalue(0) @@ -278,38 +278,38 @@ class TB(object): # Ethernet self.qsfp_mac = [] - for k in range(2): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_rx_clk"), 3.102, units="ns").start()) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_tx_clk"), 3.102, units="ns").start()) + for ch in self.dut.ch: + cocotb.start_soon(Clock(ch.ch_rx_clk, 3.102, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_tx_clk, 3.102, units="ns").start()) mac = EthMac( - tx_clk=getattr(dut, f"qsfp{k}_tx_clk"), - tx_rst=getattr(dut, f"qsfp{k}_tx_rst"), - tx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{k}_tx_axis"), - tx_ptp_time=getattr(dut, f"qsfp{k}_tx_ptp_time"), - tx_ptp_ts=getattr(dut, f"qsfp{k}_tx_ptp_ts"), - tx_ptp_ts_tag=getattr(dut, f"qsfp{k}_tx_ptp_ts_tag"), - tx_ptp_ts_valid=getattr(dut, f"qsfp{k}_tx_ptp_ts_valid"), - rx_clk=getattr(dut, f"qsfp{k}_rx_clk"), - rx_rst=getattr(dut, f"qsfp{k}_rx_rst"), - rx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{k}_rx_axis"), - rx_ptp_time=getattr(dut, f"qsfp{k}_rx_ptp_time"), + tx_clk=ch.ch_tx_clk, + tx_rst=ch.ch_tx_rst, + tx_bus=AxiStreamBus.from_prefix(ch, "ch_tx_axis"), + tx_ptp_time=ch.ch_tx_ptp_time, + tx_ptp_ts=ch.ch_tx_ptp_ts, + tx_ptp_ts_tag=ch.ch_tx_ptp_ts_tag, + tx_ptp_ts_valid=ch.ch_tx_ptp_ts_valid, + rx_clk=ch.ch_rx_clk, + rx_rst=ch.ch_rx_rst, + rx_bus=AxiStreamBus.from_prefix(ch, "ch_rx_axis"), + rx_ptp_time=ch.ch_rx_ptp_time, ifg=12, speed=100e9 ) self.qsfp_mac.append(mac) - getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1) - getattr(dut, f"qsfp{k}_rx_lfc_req").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_rx_pfc_req").setimmediatevalue(0) + ch.ch_rx_status.setimmediatevalue(1) + ch.ch_rx_lfc_req.setimmediatevalue(0) + ch.ch_rx_pfc_req.setimmediatevalue(0) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start()) - getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_drp_do").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_drp_rdy").setimmediatevalue(0) + cocotb.start_soon(Clock(dut.qsfp_drp_clk, 8, units="ns").start()) + dut.qsfp_drp_rst.setimmediatevalue(0) + dut.qsfp_drp_do.setimmediatevalue(0) + dut.qsfp_drp_rdy.setimmediatevalue(0) - getattr(dut, f"qsfp{k}_modprsl").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_intl").setimmediatevalue(1) + dut.qsfp_modprsl.setimmediatevalue(0) + dut.qsfp_intl.setimmediatevalue(1) dut.sw.setimmediatevalue(0) @@ -326,17 +326,17 @@ class TB(object): async def init(self): self.dut.ptp_rst.setimmediatevalue(0) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(0) + for ch in self.dut.ch: + ch.ch_rx_rst.setimmediatevalue(0) + ch.ch_tx_rst.setimmediatevalue(0) await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.ptp_rst.setimmediatevalue(1) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(1) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(1) + for ch in self.dut.ch: + ch.ch_rx_rst.setimmediatevalue(1) + ch.ch_tx_rst.setimmediatevalue(1) await FallingEdge(self.dut.rst_250mhz) await Timer(100, 'ns') @@ -345,9 +345,9 @@ class TB(object): await RisingEdge(self.dut.clk_250mhz) self.dut.ptp_rst.setimmediatevalue(0) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(0) + for ch in self.dut.ch: + ch.ch_rx_rst.setimmediatevalue(0) + ch.ch_tx_rst.setimmediatevalue(0) await self.rc.enumerate() @@ -364,7 +364,7 @@ class TB(object): @cocotb.test() async def run_test_nic(dut): - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) + tb = TB(dut, msix_count=2**len(dut.uut.core_inst.core_pcie_inst.irq_index)) await tb.init() @@ -572,9 +572,10 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) def test_fpga_core(request): dut = "fpga_core" module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut + toplevel = f"test_{dut}" verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.v"), os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), diff --git a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v new file mode 100644 index 000000000..456c129af --- /dev/null +++ b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v @@ -0,0 +1,966 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Testbench top-level module + */ +module test_fpga_core # +( + // FW and board IDs + parameter FPGA_ID = 32'h4B37093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h10ee_90c8, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter QSFP_CNT = 2, + parameter CH_CNT = QSFP_CNT*4, + parameter CMS_ENABLE = 1, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 1024, + parameter PTP_CLK_PERIOD_NS_DENOM = 165, + parameter PTP_TS_WIDTH = 96, + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 0, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_TAG_WIDTH = 16, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter PFC_ENABLE = 1, + parameter LFC_ENABLE = PFC_ENABLE, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 131072, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 131072, + parameter RX_RAM_SIZE = 131072, + + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 0, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_WIDTH = 512, + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, + parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, + parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, + parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, + parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, + parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + parameter PCIE_TAG_COUNT = 256, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter AXIS_ETH_DATA_WIDTH = 512, + parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, + parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH, + parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, + parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + parameter AXIS_ETH_TX_PIPELINE = 4, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, + parameter AXIS_ETH_TX_TS_PIPELINE = 4, + parameter AXIS_ETH_RX_PIPELINE = 4, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 250 MHz + * Synchronous reset + */ + input wire clk_250mhz, + input wire rst_250mhz, + + /* + * PTP clock + */ + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + + /* + * GPIO + */ + input wire [3:0] sw, + output wire [2:0] led, + + /* + * I2C + */ + input wire i2c_scl_i, + output wire i2c_scl_o, + output wire i2c_scl_t, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_t, + + /* + * PCIe + */ + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tlast, + input wire m_axis_rq_tready, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, + output wire m_axis_rq_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tlast, + output wire s_axis_rc_tready, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, + input wire s_axis_rc_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tlast, + output wire s_axis_cq_tready, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, + input wire s_axis_cq_tvalid, + + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tlast, + input wire m_axis_cc_tready, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, + output wire m_axis_cc_tvalid, + + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, + input wire s_axis_rq_seq_num_valid_0, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, + input wire s_axis_rq_seq_num_valid_1, + + input wire [1:0] pcie_tfc_nph_av, + input wire [1:0] pcie_tfc_npd_av, + + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, + input wire [3:0] cfg_rcb_status, + + output wire [9:0] cfg_mgmt_addr, + output wire [7:0] cfg_mgmt_function_number, + output wire cfg_mgmt_write, + output wire [31:0] cfg_mgmt_write_data, + output wire [3:0] cfg_mgmt_byte_enable, + output wire cfg_mgmt_read, + input wire [31:0] cfg_mgmt_read_data, + input wire cfg_mgmt_read_write_done, + + input wire [7:0] cfg_fc_ph, + input wire [11:0] cfg_fc_pd, + input wire [7:0] cfg_fc_nph, + input wire [11:0] cfg_fc_npd, + input wire [7:0] cfg_fc_cplh, + input wire [11:0] cfg_fc_cpld, + output wire [2:0] cfg_fc_sel, + + input wire [3:0] cfg_interrupt_msix_enable, + input wire [3:0] cfg_interrupt_msix_mask, + input wire [251:0] cfg_interrupt_msix_vf_enable, + input wire [251:0] cfg_interrupt_msix_vf_mask, + output wire [63:0] cfg_interrupt_msix_address, + output wire [31:0] cfg_interrupt_msix_data, + output wire cfg_interrupt_msix_int, + output wire [1:0] cfg_interrupt_msix_vec_pending, + input wire cfg_interrupt_msix_vec_pending_status, + input wire cfg_interrupt_msix_sent, + input wire cfg_interrupt_msix_fail, + output wire [7:0] cfg_interrupt_msi_function_number, + + output wire status_error_cor, + output wire status_error_uncor, + + /* + * Ethernet: QSFP28 + */ + // input wire [QSFP_CNT-1:0] qsfp_tx_clk, + // input wire [QSFP_CNT-1:0] qsfp_tx_rst, + + // output wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_tx_axis_tdata, + // output wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_tx_axis_tkeep, + // output wire [QSFP_CNT-1:0] qsfp_tx_axis_tvalid, + // input wire [QSFP_CNT-1:0] qsfp_tx_axis_tready, + // output wire [QSFP_CNT-1:0] qsfp_tx_axis_tlast, + // output wire [QSFP_CNT*(16+1)-1:0] qsfp_tx_axis_tuser, + + // output wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_time, + // input wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_ts, + // input wire [QSFP_CNT*16-1:0] qsfp_tx_ptp_ts_tag, + // input wire [QSFP_CNT-1:0] qsfp_tx_ptp_ts_valid, + + // output wire [QSFP_CNT-1:0] qsfp_tx_enable, + // output wire [QSFP_CNT-1:0] qsfp_tx_lfc_en, + // output wire [QSFP_CNT-1:0] qsfp_tx_lfc_req, + // output wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_en, + // output wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_req, + + // input wire [QSFP_CNT-1:0] qsfp_rx_clk, + // input wire [QSFP_CNT-1:0] qsfp_rx_rst, + + // input wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_rx_axis_tdata, + // input wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_rx_axis_tkeep, + // input wire [QSFP_CNT-1:0] qsfp_rx_axis_tvalid, + // input wire [QSFP_CNT-1:0] qsfp_rx_axis_tlast, + // input wire [QSFP_CNT*(80+1)-1:0] qsfp_rx_axis_tuser, + + // output wire [QSFP_CNT*80-1:0] qsfp_rx_ptp_time, + + // output wire [QSFP_CNT-1:0] qsfp_rx_enable, + // input wire [QSFP_CNT-1:0] qsfp_rx_status, + // output wire [QSFP_CNT-1:0] qsfp_rx_lfc_en, + // input wire [QSFP_CNT-1:0] qsfp_rx_lfc_req, + // output wire [QSFP_CNT-1:0] qsfp_rx_lfc_ack, + // output wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_en, + // input wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_req, + // output wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_ack, + + input wire [QSFP_CNT-1:0] qsfp_drp_clk, + input wire [QSFP_CNT-1:0] qsfp_drp_rst, + output wire [QSFP_CNT*24-1:0] qsfp_drp_addr, + output wire [QSFP_CNT*16-1:0] qsfp_drp_di, + output wire [QSFP_CNT-1:0] qsfp_drp_en, + output wire [QSFP_CNT-1:0] qsfp_drp_we, + input wire [QSFP_CNT*16-1:0] qsfp_drp_do, + input wire [QSFP_CNT-1:0] qsfp_drp_rdy, + + output wire [QSFP_CNT-1:0] qsfp_modsell, + output wire [QSFP_CNT-1:0] qsfp_resetl, + input wire [QSFP_CNT-1:0] qsfp_modprsl, + input wire [QSFP_CNT-1:0] qsfp_intl, + output wire [QSFP_CNT-1:0] qsfp_lpmode, + + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * QSPI flash + */ + output wire fpga_boot, + output wire qspi_clk, + input wire [3:0] qspi_dq_i, + output wire [3:0] qspi_dq_o, + output wire [3:0] qspi_dq_oe, + output wire qspi_cs, + + /* + * AXI-Lite interface to CMS + */ + output wire m_axil_cms_clk, + output wire m_axil_cms_rst, + output wire [17:0] m_axil_cms_awaddr, + output wire [2:0] m_axil_cms_awprot, + output wire m_axil_cms_awvalid, + input wire m_axil_cms_awready, + output wire [31:0] m_axil_cms_wdata, + output wire [3:0] m_axil_cms_wstrb, + output wire m_axil_cms_wvalid, + input wire m_axil_cms_wready, + input wire [1:0] m_axil_cms_bresp, + input wire m_axil_cms_bvalid, + output wire m_axil_cms_bready, + output wire [17:0] m_axil_cms_araddr, + output wire [2:0] m_axil_cms_arprot, + output wire m_axil_cms_arvalid, + input wire m_axil_cms_arready, + input wire [31:0] m_axil_cms_rdata, + input wire [1:0] m_axil_cms_rresp, + input wire m_axil_cms_rvalid, + output wire m_axil_cms_rready +); + +genvar n; + +wire [QSFP_CNT-1:0] qsfp_tx_clk; +wire [QSFP_CNT-1:0] qsfp_tx_rst; + +wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_tx_axis_tdata; +wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_tx_axis_tkeep; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tvalid; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tready; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tlast; +wire [QSFP_CNT*(16+1)-1:0] qsfp_tx_axis_tuser; + +wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_time; +wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_ts; +wire [QSFP_CNT*16-1:0] qsfp_tx_ptp_ts_tag; +wire [QSFP_CNT-1:0] qsfp_tx_ptp_ts_valid; + +wire [QSFP_CNT-1:0] qsfp_tx_enable; +wire [QSFP_CNT-1:0] qsfp_tx_lfc_en; +wire [QSFP_CNT-1:0] qsfp_tx_lfc_req; +wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_en; +wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_req; + +wire [QSFP_CNT-1:0] qsfp_rx_clk; +wire [QSFP_CNT-1:0] qsfp_rx_rst; + +wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_rx_axis_tdata; +wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_rx_axis_tkeep; +wire [QSFP_CNT-1:0] qsfp_rx_axis_tvalid; +wire [QSFP_CNT-1:0] qsfp_rx_axis_tlast; +wire [QSFP_CNT*(80+1)-1:0] qsfp_rx_axis_tuser; + +wire [QSFP_CNT*80-1:0] qsfp_rx_ptp_time; + +wire [QSFP_CNT-1:0] qsfp_rx_enable; +wire [QSFP_CNT-1:0] qsfp_rx_status; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_en; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_req; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_ack; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_en; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_req; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_ack; + +generate + +for (n = 0; n < QSFP_CNT; n = n + 1) begin : ch + + input wire ch_tx_clk; + input wire ch_tx_rst; + + output wire [AXIS_ETH_DATA_WIDTH-1:0] ch_tx_axis_tdata; + output wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_tx_axis_tkeep; + output wire ch_tx_axis_tvalid; + input wire ch_tx_axis_tready; + output wire ch_tx_axis_tlast; + output wire [(16+1)-1:0] ch_tx_axis_tuser; + + output wire [79:0] ch_tx_ptp_time; + input wire [79:0] ch_tx_ptp_ts; + input wire [15:0] ch_tx_ptp_ts_tag; + input wire ch_tx_ptp_ts_valid; + + output wire ch_tx_enable; + output wire ch_tx_lfc_en; + output wire ch_tx_lfc_req; + output wire [7:0] ch_tx_pfc_en; + output wire [7:0] ch_tx_pfc_req; + + input wire ch_rx_clk; + input wire ch_rx_rst; + + input wire [AXIS_ETH_DATA_WIDTH-1:0] ch_rx_axis_tdata; + input wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_rx_axis_tkeep; + input wire ch_rx_axis_tvalid; + input wire ch_rx_axis_tlast; + input wire [(80+1)-1:0] ch_rx_axis_tuser; + + output wire [79:0] ch_rx_ptp_time; + + output wire ch_rx_enable; + input wire ch_rx_status; + output wire ch_rx_lfc_en; + input wire ch_rx_lfc_req; + output wire ch_rx_lfc_ack; + output wire [7:0] ch_rx_pfc_en; + input wire [7:0] ch_rx_pfc_req; + output wire [7:0] ch_rx_pfc_ack; + + assign qsfp_tx_clk[n +: 1] = ch_tx_clk; + assign qsfp_tx_rst[n +: 1] = ch_tx_rst; + + assign ch_tx_axis_tdata = qsfp_tx_axis_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]; + assign ch_tx_axis_tkeep = qsfp_tx_axis_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]; + assign ch_tx_axis_tvalid = qsfp_tx_axis_tvalid[n +: 1]; + assign qsfp_tx_axis_tready[n +: 1] = ch_tx_axis_tready; + assign ch_tx_axis_tlast = qsfp_tx_axis_tlast[n +: 1]; + assign ch_tx_axis_tuser = qsfp_tx_axis_tuser[n*(16+1) +: (16+1)]; + + assign ch_tx_ptp_time = qsfp_tx_ptp_time[n*80 +: 80]; + assign qsfp_tx_ptp_ts[n*80 +: 80] = ch_tx_ptp_ts; + assign qsfp_tx_ptp_ts_tag[n*16 +: 16] = ch_tx_ptp_ts_tag; + assign qsfp_tx_ptp_ts_valid[n +: 1] = ch_tx_ptp_ts_valid; + + assign ch_tx_enable = qsfp_tx_enable[n +: 1]; + assign ch_tx_lfc_en = qsfp_tx_lfc_en[n +: 1]; + assign ch_tx_lfc_req = qsfp_tx_lfc_req[n +: 1]; + assign ch_tx_pfc_en = qsfp_tx_pfc_en[n*8 +: 8]; + assign ch_tx_pfc_req = qsfp_tx_pfc_req[n*8 +: 8]; + + assign qsfp_rx_clk[n +: 1] = ch_rx_clk; + assign qsfp_rx_rst[n +: 1] = ch_rx_rst; + + assign qsfp_rx_axis_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH] = ch_rx_axis_tdata; + assign qsfp_rx_axis_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH] = ch_rx_axis_tkeep; + assign qsfp_rx_axis_tvalid[n +: 1] = ch_rx_axis_tvalid; + assign qsfp_rx_axis_tlast[n +: 1] = ch_rx_axis_tlast; + assign qsfp_rx_axis_tuser[n*(80+1) +: (80+1)] = ch_rx_axis_tuser; + + assign ch_rx_ptp_time = qsfp_rx_ptp_time[n*80 +: 80]; + + assign ch_rx_enable = qsfp_rx_enable[n +: 1]; + assign qsfp_rx_status[n +: 1] = ch_rx_status; + assign ch_rx_lfc_en = qsfp_rx_lfc_en[n +: 1]; + assign qsfp_rx_lfc_req[n +: 1] = ch_rx_lfc_req; + assign ch_rx_lfc_ack = qsfp_rx_lfc_ack[n +: 1]; + assign ch_rx_pfc_en = qsfp_rx_pfc_en[n*8 +: 8]; + assign qsfp_rx_pfc_req[n*8 +: 8] = ch_rx_pfc_req; + assign ch_rx_pfc_ack = qsfp_rx_pfc_ack[n*8 +: 8]; + +end + +endgenerate + +fpga_core #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Board configuration + .QSFP_CNT(QSFP_CNT), + .CH_CNT(CH_CNT), + .CMS_ENABLE(CMS_ENABLE), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + .PORT_MASK(PORT_MASK), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .PFC_ENABLE(PFC_ENABLE), + .LFC_ENABLE(LFC_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RC_STRADDLE(RC_STRADDLE), + .RQ_STRADDLE(RQ_STRADDLE), + .CQ_STRADDLE(CQ_STRADDLE), + .CC_STRADDLE(CC_STRADDLE), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +uut ( + /* + * Clock: 250 MHz + * Synchronous reset + */ + .clk_250mhz(clk_250mhz), + .rst_250mhz(rst_250mhz), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + + /* + * GPIO + */ + .sw(sw), + .led(led), + + /* + * I2C + */ + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_scl_t(i2c_scl_t), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o), + .i2c_sda_t(i2c_sda_t), + + /* + * PCIe + */ + .m_axis_rq_tdata(m_axis_rq_tdata), + .m_axis_rq_tkeep(m_axis_rq_tkeep), + .m_axis_rq_tlast(m_axis_rq_tlast), + .m_axis_rq_tready(m_axis_rq_tready), + .m_axis_rq_tuser(m_axis_rq_tuser), + .m_axis_rq_tvalid(m_axis_rq_tvalid), + + .s_axis_rc_tdata(s_axis_rc_tdata), + .s_axis_rc_tkeep(s_axis_rc_tkeep), + .s_axis_rc_tlast(s_axis_rc_tlast), + .s_axis_rc_tready(s_axis_rc_tready), + .s_axis_rc_tuser(s_axis_rc_tuser), + .s_axis_rc_tvalid(s_axis_rc_tvalid), + + .s_axis_cq_tdata(s_axis_cq_tdata), + .s_axis_cq_tkeep(s_axis_cq_tkeep), + .s_axis_cq_tlast(s_axis_cq_tlast), + .s_axis_cq_tready(s_axis_cq_tready), + .s_axis_cq_tuser(s_axis_cq_tuser), + .s_axis_cq_tvalid(s_axis_cq_tvalid), + + .m_axis_cc_tdata(m_axis_cc_tdata), + .m_axis_cc_tkeep(m_axis_cc_tkeep), + .m_axis_cc_tlast(m_axis_cc_tlast), + .m_axis_cc_tready(m_axis_cc_tready), + .m_axis_cc_tuser(m_axis_cc_tuser), + .m_axis_cc_tvalid(m_axis_cc_tvalid), + + .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), + .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), + .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), + .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * Ethernet: QSFP28 + */ + .qsfp_tx_clk(qsfp_tx_clk), + .qsfp_tx_rst(qsfp_tx_rst), + + .qsfp_tx_axis_tdata(qsfp_tx_axis_tdata), + .qsfp_tx_axis_tkeep(qsfp_tx_axis_tkeep), + .qsfp_tx_axis_tvalid(qsfp_tx_axis_tvalid), + .qsfp_tx_axis_tready(qsfp_tx_axis_tready), + .qsfp_tx_axis_tlast(qsfp_tx_axis_tlast), + .qsfp_tx_axis_tuser(qsfp_tx_axis_tuser), + + .qsfp_tx_ptp_time(qsfp_tx_ptp_time), + .qsfp_tx_ptp_ts(qsfp_tx_ptp_ts), + .qsfp_tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag), + .qsfp_tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid), + + .qsfp_tx_enable(qsfp_tx_enable), + .qsfp_tx_lfc_en(qsfp_tx_lfc_en), + .qsfp_tx_lfc_req(qsfp_tx_lfc_req), + .qsfp_tx_pfc_en(qsfp_tx_pfc_en), + .qsfp_tx_pfc_req(qsfp_tx_pfc_req), + + .qsfp_rx_clk(qsfp_rx_clk), + .qsfp_rx_rst(qsfp_rx_rst), + + .qsfp_rx_axis_tdata(qsfp_rx_axis_tdata), + .qsfp_rx_axis_tkeep(qsfp_rx_axis_tkeep), + .qsfp_rx_axis_tvalid(qsfp_rx_axis_tvalid), + .qsfp_rx_axis_tlast(qsfp_rx_axis_tlast), + .qsfp_rx_axis_tuser(qsfp_rx_axis_tuser), + + .qsfp_rx_ptp_time(qsfp_rx_ptp_time), + + .qsfp_rx_enable(qsfp_rx_enable), + .qsfp_rx_status(qsfp_rx_status), + .qsfp_rx_lfc_en(qsfp_rx_lfc_en), + .qsfp_rx_lfc_req(qsfp_rx_lfc_req), + .qsfp_rx_lfc_ack(qsfp_rx_lfc_ack), + .qsfp_rx_pfc_en(qsfp_rx_pfc_en), + .qsfp_rx_pfc_req(qsfp_rx_pfc_req), + .qsfp_rx_pfc_ack(qsfp_rx_pfc_ack), + + .qsfp_drp_clk(qsfp_drp_clk), + .qsfp_drp_rst(qsfp_drp_rst), + .qsfp_drp_addr(qsfp_drp_addr), + .qsfp_drp_di(qsfp_drp_di), + .qsfp_drp_en(qsfp_drp_en), + .qsfp_drp_we(qsfp_drp_we), + .qsfp_drp_do(qsfp_drp_do), + .qsfp_drp_rdy(qsfp_drp_rdy), + + .qsfp_modsell(qsfp_modsell), + .qsfp_resetl(qsfp_resetl), + .qsfp_modprsl(qsfp_modprsl), + .qsfp_intl(qsfp_intl), + .qsfp_lpmode(qsfp_lpmode), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk), + .qspi_dq_i(qspi_dq_i), + .qspi_dq_o(qspi_dq_o), + .qspi_dq_oe(qspi_dq_oe), + .qspi_cs(qspi_cs), + + /* + * AXI-Lite interface to CMS + */ + .m_axil_cms_clk(m_axil_cms_clk), + .m_axil_cms_rst(m_axil_cms_rst), + .m_axil_cms_awaddr(m_axil_cms_awaddr), + .m_axil_cms_awprot(m_axil_cms_awprot), + .m_axil_cms_awvalid(m_axil_cms_awvalid), + .m_axil_cms_awready(m_axil_cms_awready), + .m_axil_cms_wdata(m_axil_cms_wdata), + .m_axil_cms_wstrb(m_axil_cms_wstrb), + .m_axil_cms_wvalid(m_axil_cms_wvalid), + .m_axil_cms_wready(m_axil_cms_wready), + .m_axil_cms_bresp(m_axil_cms_bresp), + .m_axil_cms_bvalid(m_axil_cms_bvalid), + .m_axil_cms_bready(m_axil_cms_bready), + .m_axil_cms_araddr(m_axil_cms_araddr), + .m_axil_cms_arprot(m_axil_cms_arprot), + .m_axil_cms_arvalid(m_axil_cms_arvalid), + .m_axil_cms_arready(m_axil_cms_arready), + .m_axil_cms_rdata(m_axil_cms_rdata), + .m_axil_cms_rresp(m_axil_cms_rresp), + .m_axil_cms_rvalid(m_axil_cms_rvalid), + .m_axil_cms_rready(m_axil_cms_rready) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v index 0beb3997a..1792697a8 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v @@ -437,10 +437,8 @@ wire btnd_int; wire btnr_int; wire btnc_int; wire [3:0] sw_int; -wire qsfp0_modprsl_int; -wire qsfp1_modprsl_int; -wire qsfp0_intl_int; -wire qsfp1_intl_int; +wire [1:0] qsfp_modprsl_int; +wire [1:0] qsfp_intl_int; wire i2c_scl_i; wire i2c_scl_o; wire i2c_scl_t; @@ -480,7 +478,7 @@ sync_signal_inst ( .clk(pcie_user_clk), .in({qsfp0_modprsl, qsfp1_modprsl, qsfp0_intl, qsfp1_intl, i2c_scl, i2c_sda}), - .out({qsfp0_modprsl_int, qsfp1_modprsl_int, qsfp0_intl_int, qsfp1_intl_int, + .out({qsfp_modprsl_int, qsfp_intl_int, i2c_scl_i, i2c_sda_i}) ); @@ -1103,74 +1101,46 @@ pcie4_uscale_plus_inst ( .phy_rdy_out() ); -// XGMII 10G PHY +// XGMII 25G PHY +localparam QSFP_CNT = 2; +localparam CH_CNT = QSFP_CNT*4; + +wire [CH_CNT-1:0] qsfp_tx_clk; +wire [CH_CNT-1:0] qsfp_tx_rst; +wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_txd; +wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_txc; +wire [CH_CNT-1:0] qsfp_cfg_tx_prbs31_enable; +wire [CH_CNT-1:0] qsfp_rx_clk; +wire [CH_CNT-1:0] qsfp_rx_rst; +wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_rxd; +wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_rxc; +wire [CH_CNT-1:0] qsfp_cfg_rx_prbs31_enable; +wire [CH_CNT*7-1:0] qsfp_rx_error_count; +wire [CH_CNT-1:0] qsfp_rx_status; + +wire [QSFP_CNT-1:0] qsfp_drp_clk; +wire [QSFP_CNT-1:0] qsfp_drp_rst; +wire [QSFP_CNT*24-1:0] qsfp_drp_addr; +wire [QSFP_CNT*16-1:0] qsfp_drp_di; +wire [QSFP_CNT-1:0] qsfp_drp_en; +wire [QSFP_CNT-1:0] qsfp_drp_we; +wire [QSFP_CNT*16-1:0] qsfp_drp_do; +wire [QSFP_CNT-1:0] qsfp_drp_rdy; + +wire [QSFP_CNT-1:0] qsfp_modsell; +wire [QSFP_CNT-1:0] qsfp_resetl; +wire [QSFP_CNT-1:0] qsfp_lpmode; // QSFP0 assign qsfp0_refclk_reset = qsfp_refclk_reset_reg; assign qsfp0_fs = 2'b10; -wire qsfp0_tx_clk_1_int; -wire qsfp0_tx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int; -wire qsfp0_cfg_tx_prbs31_enable_1_int; -wire qsfp0_rx_clk_1_int; -wire qsfp0_rx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int; -wire qsfp0_cfg_rx_prbs31_enable_1_int; -wire [6:0] qsfp0_rx_error_count_1_int; -wire qsfp0_tx_clk_2_int; -wire qsfp0_tx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int; -wire qsfp0_cfg_tx_prbs31_enable_2_int; -wire qsfp0_rx_clk_2_int; -wire qsfp0_rx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int; -wire qsfp0_cfg_rx_prbs31_enable_2_int; -wire [6:0] qsfp0_rx_error_count_2_int; -wire qsfp0_tx_clk_3_int; -wire qsfp0_tx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int; -wire qsfp0_cfg_tx_prbs31_enable_3_int; -wire qsfp0_rx_clk_3_int; -wire qsfp0_rx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int; -wire qsfp0_cfg_rx_prbs31_enable_3_int; -wire [6:0] qsfp0_rx_error_count_3_int; -wire qsfp0_tx_clk_4_int; -wire qsfp0_tx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int; -wire qsfp0_cfg_tx_prbs31_enable_4_int; -wire qsfp0_rx_clk_4_int; -wire qsfp0_rx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int; -wire qsfp0_cfg_rx_prbs31_enable_4_int; -wire [6:0] qsfp0_rx_error_count_4_int; +assign qsfp_drp_clk[0 +: 1] = clk_125mhz_int; +assign qsfp_drp_rst[0 +: 1] = rst_125mhz_int; -wire qsfp0_drp_clk = clk_125mhz_int; -wire qsfp0_drp_rst = rst_125mhz_int; -wire [23:0] qsfp0_drp_addr; -wire [15:0] qsfp0_drp_di; -wire qsfp0_drp_en; -wire qsfp0_drp_we; -wire [15:0] qsfp0_drp_do; -wire qsfp0_drp_rdy; - -wire qsfp0_rx_block_lock_1; -wire qsfp0_rx_status_1; -wire qsfp0_rx_block_lock_2; -wire qsfp0_rx_status_2; -wire qsfp0_rx_block_lock_3; -wire qsfp0_rx_status_3; -wire qsfp0_rx_block_lock_4; -wire qsfp0_rx_status_4; +assign qsfp0_modsell = qsfp_modsell[0 +: 1]; +assign qsfp0_resetl = qsfp_resetl[0 +: 1]; +assign qsfp0_lpmode = qsfp_lpmode[0 +: 1]; wire qsfp0_gtpowergood; @@ -1228,14 +1198,14 @@ qsfp0_phy_quad_inst ( /* * DRP */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy), + .drp_clk(qsfp_drp_clk[0 +: 1]), + .drp_rst(qsfp_drp_rst[0 +: 1]), + .drp_addr(qsfp_drp_addr[0*24 +: 24]), + .drp_di(qsfp_drp_di[0*16 +: 16]), + .drp_en(qsfp_drp_en[0 +: 1]), + .drp_we(qsfp_drp_we[0 +: 1]), + .drp_do(qsfp_drp_do[0*16 +: 16]), + .drp_rdy(qsfp_drp_rdy[0 +: 1]), /* * Serial data @@ -1248,145 +1218,89 @@ qsfp0_phy_quad_inst ( /* * PHY connections */ - .phy_1_tx_clk(qsfp0_tx_clk_1_int), - .phy_1_tx_rst(qsfp0_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp0_txd_1_int), - .phy_1_xgmii_txc(qsfp0_txc_1_int), - .phy_1_rx_clk(qsfp0_rx_clk_1_int), - .phy_1_rx_rst(qsfp0_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp0_rxd_1_int), - .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_clk(qsfp_tx_clk[0*4+0 +: 1]), + .phy_1_tx_rst(qsfp_tx_rst[0*4+0 +: 1]), + .phy_1_xgmii_txd(qsfp_txd[(0*4+0)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_1_xgmii_txc(qsfp_txc[(0*4+0)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_1_rx_clk(qsfp_rx_clk[0*4+0 +: 1]), + .phy_1_rx_rst(qsfp_rx_rst[0*4+0 +: 1]), + .phy_1_xgmii_rxd(qsfp_rxd[(0*4+0)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_1_xgmii_rxc(qsfp_rxc[(0*4+0)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .phy_1_tx_bad_block(), - .phy_1_rx_error_count(qsfp0_rx_error_count_1_int), + .phy_1_rx_error_count(qsfp_rx_error_count[(0*4+0)*7 +: 7]), .phy_1_rx_bad_block(), .phy_1_rx_sequence_error(), - .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_block_lock(), .phy_1_rx_high_ber(), - .phy_1_rx_status(qsfp0_rx_status_1), - .phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int), - .phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int), + .phy_1_rx_status(qsfp_rx_status[0*4+0 +: 1]), + .phy_1_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[0*4+0 +: 1]), + .phy_1_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[0*4+0 +: 1]), - .phy_2_tx_clk(qsfp0_tx_clk_2_int), - .phy_2_tx_rst(qsfp0_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp0_txd_2_int), - .phy_2_xgmii_txc(qsfp0_txc_2_int), - .phy_2_rx_clk(qsfp0_rx_clk_2_int), - .phy_2_rx_rst(qsfp0_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp0_rxd_2_int), - .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_clk(qsfp_tx_clk[0*4+1 +: 1]), + .phy_2_tx_rst(qsfp_tx_rst[0*4+1 +: 1]), + .phy_2_xgmii_txd(qsfp_txd[(0*4+1)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_2_xgmii_txc(qsfp_txc[(0*4+1)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_2_rx_clk(qsfp_rx_clk[0*4+1 +: 1]), + .phy_2_rx_rst(qsfp_rx_rst[0*4+1 +: 1]), + .phy_2_xgmii_rxd(qsfp_rxd[(0*4+1)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_2_xgmii_rxc(qsfp_rxc[(0*4+1)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .phy_2_tx_bad_block(), - .phy_2_rx_error_count(qsfp0_rx_error_count_2_int), + .phy_2_rx_error_count(qsfp_rx_error_count[(0*4+1)*7 +: 7]), .phy_2_rx_bad_block(), .phy_2_rx_sequence_error(), - .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_block_lock(), .phy_2_rx_high_ber(), - .phy_2_rx_status(qsfp0_rx_status_2), - .phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int), - .phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int), + .phy_2_rx_status(qsfp_rx_status[0*4+1 +: 1]), + .phy_2_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[0*4+1 +: 1]), + .phy_2_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[0*4+1 +: 1]), - .phy_3_tx_clk(qsfp0_tx_clk_3_int), - .phy_3_tx_rst(qsfp0_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp0_txd_3_int), - .phy_3_xgmii_txc(qsfp0_txc_3_int), - .phy_3_rx_clk(qsfp0_rx_clk_3_int), - .phy_3_rx_rst(qsfp0_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp0_rxd_3_int), - .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_clk(qsfp_tx_clk[0*4+2 +: 1]), + .phy_3_tx_rst(qsfp_tx_rst[0*4+2 +: 1]), + .phy_3_xgmii_txd(qsfp_txd[(0*4+2)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_3_xgmii_txc(qsfp_txc[(0*4+2)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_3_rx_clk(qsfp_rx_clk[0*4+2 +: 1]), + .phy_3_rx_rst(qsfp_rx_rst[0*4+2 +: 1]), + .phy_3_xgmii_rxd(qsfp_rxd[(0*4+2)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_3_xgmii_rxc(qsfp_rxc[(0*4+2)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .phy_3_tx_bad_block(), - .phy_3_rx_error_count(qsfp0_rx_error_count_3_int), + .phy_3_rx_error_count(qsfp_rx_error_count[(0*4+2)*7 +: 7]), .phy_3_rx_bad_block(), .phy_3_rx_sequence_error(), - .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_block_lock(), .phy_3_rx_high_ber(), - .phy_3_rx_status(qsfp0_rx_status_3), - .phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int), - .phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int), + .phy_3_rx_status(qsfp_rx_status[0*4+2 +: 1]), + .phy_3_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[0*4+2 +: 1]), + .phy_3_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[0*4+2 +: 1]), - .phy_4_tx_clk(qsfp0_tx_clk_4_int), - .phy_4_tx_rst(qsfp0_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp0_txd_4_int), - .phy_4_xgmii_txc(qsfp0_txc_4_int), - .phy_4_rx_clk(qsfp0_rx_clk_4_int), - .phy_4_rx_rst(qsfp0_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp0_rxd_4_int), - .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_clk(qsfp_tx_clk[0*4+3 +: 1]), + .phy_4_tx_rst(qsfp_tx_rst[0*4+3 +: 1]), + .phy_4_xgmii_txd(qsfp_txd[(0*4+3)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_4_xgmii_txc(qsfp_txc[(0*4+3)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_4_rx_clk(qsfp_rx_clk[0*4+3 +: 1]), + .phy_4_rx_rst(qsfp_rx_rst[0*4+3 +: 1]), + .phy_4_xgmii_rxd(qsfp_rxd[(0*4+3)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_4_xgmii_rxc(qsfp_rxc[(0*4+3)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .phy_4_tx_bad_block(), - .phy_4_rx_error_count(qsfp0_rx_error_count_4_int), + .phy_4_rx_error_count(qsfp_rx_error_count[(0*4+3)*7 +: 7]), .phy_4_rx_bad_block(), .phy_4_rx_sequence_error(), - .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_block_lock(), .phy_4_rx_high_ber(), - .phy_4_rx_status(qsfp0_rx_status_4), - .phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int), - .phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int) + .phy_4_rx_status(qsfp_rx_status[0*4+3 +: 1]), + .phy_4_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[0*4+3 +: 1]), + .phy_4_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[0*4+3 +: 1]) ); // QSFP1 assign qsfp1_refclk_reset = qsfp_refclk_reset_reg; assign qsfp1_fs = 2'b10; -wire qsfp1_tx_clk_1_int; -wire qsfp1_tx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int; -wire qsfp1_cfg_tx_prbs31_enable_1_int; -wire qsfp1_rx_clk_1_int; -wire qsfp1_rx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int; -wire qsfp1_cfg_rx_prbs31_enable_1_int; -wire [6:0] qsfp1_rx_error_count_1_int; -wire qsfp1_tx_clk_2_int; -wire qsfp1_tx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int; -wire qsfp1_cfg_tx_prbs31_enable_2_int; -wire qsfp1_rx_clk_2_int; -wire qsfp1_rx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int; -wire qsfp1_cfg_rx_prbs31_enable_2_int; -wire [6:0] qsfp1_rx_error_count_2_int; -wire qsfp1_tx_clk_3_int; -wire qsfp1_tx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int; -wire qsfp1_cfg_tx_prbs31_enable_3_int; -wire qsfp1_rx_clk_3_int; -wire qsfp1_rx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int; -wire qsfp1_cfg_rx_prbs31_enable_3_int; -wire [6:0] qsfp1_rx_error_count_3_int; -wire qsfp1_tx_clk_4_int; -wire qsfp1_tx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int; -wire qsfp1_cfg_tx_prbs31_enable_4_int; -wire qsfp1_rx_clk_4_int; -wire qsfp1_rx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int; -wire qsfp1_cfg_rx_prbs31_enable_4_int; -wire [6:0] qsfp1_rx_error_count_4_int; +assign qsfp_drp_clk[1 +: 1] = clk_125mhz_int; +assign qsfp_drp_rst[1 +: 1] = rst_125mhz_int; -wire qsfp1_drp_clk = clk_125mhz_int; -wire qsfp1_drp_rst = rst_125mhz_int; -wire [23:0] qsfp1_drp_addr; -wire [15:0] qsfp1_drp_di; -wire qsfp1_drp_en; -wire qsfp1_drp_we; -wire [15:0] qsfp1_drp_do; -wire qsfp1_drp_rdy; - -wire qsfp1_rx_block_lock_1; -wire qsfp1_rx_status_1; -wire qsfp1_rx_block_lock_2; -wire qsfp1_rx_status_2; -wire qsfp1_rx_block_lock_3; -wire qsfp1_rx_status_3; -wire qsfp1_rx_block_lock_4; -wire qsfp1_rx_status_4; +assign qsfp1_modsell = qsfp_modsell[1 +: 1]; +assign qsfp1_resetl = qsfp_resetl[1 +: 1]; +assign qsfp1_lpmode = qsfp_lpmode[1 +: 1]; wire qsfp1_gtpowergood; @@ -1442,14 +1356,14 @@ qsfp1_phy_quad_inst ( /* * DRP */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy), + .drp_clk(qsfp_drp_clk[1 +: 1]), + .drp_rst(qsfp_drp_rst[1 +: 1]), + .drp_addr(qsfp_drp_addr[1*24 +: 24]), + .drp_di(qsfp_drp_di[1*16 +: 16]), + .drp_en(qsfp_drp_en[1 +: 1]), + .drp_we(qsfp_drp_we[1 +: 1]), + .drp_do(qsfp_drp_do[1*16 +: 16]), + .drp_rdy(qsfp_drp_rdy[1 +: 1]), /* * Serial data @@ -1462,77 +1376,77 @@ qsfp1_phy_quad_inst ( /* * PHY connections */ - .phy_1_tx_clk(qsfp1_tx_clk_1_int), - .phy_1_tx_rst(qsfp1_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp1_txd_1_int), - .phy_1_xgmii_txc(qsfp1_txc_1_int), - .phy_1_rx_clk(qsfp1_rx_clk_1_int), - .phy_1_rx_rst(qsfp1_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp1_rxd_1_int), - .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_clk(qsfp_tx_clk[1*4+0 +: 1]), + .phy_1_tx_rst(qsfp_tx_rst[1*4+0 +: 1]), + .phy_1_xgmii_txd(qsfp_txd[(1*4+0)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_1_xgmii_txc(qsfp_txc[(1*4+0)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_1_rx_clk(qsfp_rx_clk[1*4+0 +: 1]), + .phy_1_rx_rst(qsfp_rx_rst[1*4+0 +: 1]), + .phy_1_xgmii_rxd(qsfp_rxd[(1*4+0)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_1_xgmii_rxc(qsfp_rxc[(1*4+0)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .phy_1_tx_bad_block(), - .phy_1_rx_error_count(qsfp1_rx_error_count_1_int), + .phy_1_rx_error_count(qsfp_rx_error_count[(1*4+0)*7 +: 7]), .phy_1_rx_bad_block(), .phy_1_rx_sequence_error(), - .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_block_lock(), .phy_1_rx_high_ber(), - .phy_1_rx_status(qsfp1_rx_status_1), - .phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int), - .phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int), + .phy_1_rx_status(qsfp_rx_status[1*4+0 +: 1]), + .phy_1_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[1*4+0 +: 1]), + .phy_1_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[1*4+0 +: 1]), - .phy_2_tx_clk(qsfp1_tx_clk_2_int), - .phy_2_tx_rst(qsfp1_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp1_txd_2_int), - .phy_2_xgmii_txc(qsfp1_txc_2_int), - .phy_2_rx_clk(qsfp1_rx_clk_2_int), - .phy_2_rx_rst(qsfp1_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp1_rxd_2_int), - .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_clk(qsfp_tx_clk[1*4+1 +: 1]), + .phy_2_tx_rst(qsfp_tx_rst[1*4+1 +: 1]), + .phy_2_xgmii_txd(qsfp_txd[(1*4+1)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_2_xgmii_txc(qsfp_txc[(1*4+1)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_2_rx_clk(qsfp_rx_clk[1*4+1 +: 1]), + .phy_2_rx_rst(qsfp_rx_rst[1*4+1 +: 1]), + .phy_2_xgmii_rxd(qsfp_rxd[(1*4+1)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_2_xgmii_rxc(qsfp_rxc[(1*4+1)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .phy_2_tx_bad_block(), - .phy_2_rx_error_count(qsfp1_rx_error_count_2_int), + .phy_2_rx_error_count(qsfp_rx_error_count[(1*4+1)*7 +: 7]), .phy_2_rx_bad_block(), .phy_2_rx_sequence_error(), - .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_block_lock(), .phy_2_rx_high_ber(), - .phy_2_rx_status(qsfp1_rx_status_2), - .phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int), - .phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int), + .phy_2_rx_status(qsfp_rx_status[1*4+1 +: 1]), + .phy_2_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[1*4+1 +: 1]), + .phy_2_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[1*4+1 +: 1]), - .phy_3_tx_clk(qsfp1_tx_clk_3_int), - .phy_3_tx_rst(qsfp1_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp1_txd_3_int), - .phy_3_xgmii_txc(qsfp1_txc_3_int), - .phy_3_rx_clk(qsfp1_rx_clk_3_int), - .phy_3_rx_rst(qsfp1_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp1_rxd_3_int), - .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_clk(qsfp_tx_clk[1*4+2 +: 1]), + .phy_3_tx_rst(qsfp_tx_rst[1*4+2 +: 1]), + .phy_3_xgmii_txd(qsfp_txd[(1*4+2)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_3_xgmii_txc(qsfp_txc[(1*4+2)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_3_rx_clk(qsfp_rx_clk[1*4+2 +: 1]), + .phy_3_rx_rst(qsfp_rx_rst[1*4+2 +: 1]), + .phy_3_xgmii_rxd(qsfp_rxd[(1*4+2)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_3_xgmii_rxc(qsfp_rxc[(1*4+2)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .phy_3_tx_bad_block(), - .phy_3_rx_error_count(qsfp1_rx_error_count_3_int), + .phy_3_rx_error_count(qsfp_rx_error_count[(1*4+2)*7 +: 7]), .phy_3_rx_bad_block(), .phy_3_rx_sequence_error(), - .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_block_lock(), .phy_3_rx_high_ber(), - .phy_3_rx_status(qsfp1_rx_status_3), - .phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int), - .phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int), + .phy_3_rx_status(qsfp_rx_status[1*4+2 +: 1]), + .phy_3_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[1*4+2 +: 1]), + .phy_3_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[1*4+2 +: 1]), - .phy_4_tx_clk(qsfp1_tx_clk_4_int), - .phy_4_tx_rst(qsfp1_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp1_txd_4_int), - .phy_4_xgmii_txc(qsfp1_txc_4_int), - .phy_4_rx_clk(qsfp1_rx_clk_4_int), - .phy_4_rx_rst(qsfp1_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp1_rxd_4_int), - .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_clk(qsfp_tx_clk[1*4+3 +: 1]), + .phy_4_tx_rst(qsfp_tx_rst[1*4+3 +: 1]), + .phy_4_xgmii_txd(qsfp_txd[(1*4+3)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_4_xgmii_txc(qsfp_txc[(1*4+3)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_4_rx_clk(qsfp_rx_clk[1*4+3 +: 1]), + .phy_4_rx_rst(qsfp_rx_rst[1*4+3 +: 1]), + .phy_4_xgmii_rxd(qsfp_rxd[(1*4+3)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_4_xgmii_rxc(qsfp_rxc[(1*4+3)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), .phy_4_tx_bad_block(), - .phy_4_rx_error_count(qsfp1_rx_error_count_4_int), + .phy_4_rx_error_count(qsfp_rx_error_count[(1*4+3)*7 +: 7]), .phy_4_rx_bad_block(), .phy_4_rx_sequence_error(), - .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_block_lock(), .phy_4_rx_high_ber(), - .phy_4_rx_status(qsfp1_rx_status_4), - .phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int), - .phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int) + .phy_4_rx_status(qsfp_rx_status[1*4+3 +: 1]), + .phy_4_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[1*4+3 +: 1]), + .phy_4_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[1*4+3 +: 1]) ); wire ptp_clk; @@ -2108,6 +2022,8 @@ fpga_core #( .RELEASE_INFO(RELEASE_INFO), // Board configuration + .QSFP_CNT(QSFP_CNT), + .CH_CNT(CH_CNT), .CMS_ENABLE(CMS_ENABLE), .TDMA_BER_ENABLE(TDMA_BER_ENABLE), @@ -2360,133 +2276,33 @@ core_inst ( /* * Ethernet: QSFP28 */ - .qsfp0_tx_clk_1(qsfp0_tx_clk_1_int), - .qsfp0_tx_rst_1(qsfp0_tx_rst_1_int), - .qsfp0_txd_1(qsfp0_txd_1_int), - .qsfp0_txc_1(qsfp0_txc_1_int), - .qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int), - .qsfp0_rx_clk_1(qsfp0_rx_clk_1_int), - .qsfp0_rx_rst_1(qsfp0_rx_rst_1_int), - .qsfp0_rxd_1(qsfp0_rxd_1_int), - .qsfp0_rxc_1(qsfp0_rxc_1_int), - .qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int), - .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int), - .qsfp0_rx_status_1(qsfp0_rx_status_1), - .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int), - .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int), - .qsfp0_txd_2(qsfp0_txd_2_int), - .qsfp0_txc_2(qsfp0_txc_2_int), - .qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int), - .qsfp0_rx_clk_2(qsfp0_rx_clk_2_int), - .qsfp0_rx_rst_2(qsfp0_rx_rst_2_int), - .qsfp0_rxd_2(qsfp0_rxd_2_int), - .qsfp0_rxc_2(qsfp0_rxc_2_int), - .qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int), - .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int), - .qsfp0_rx_status_2(qsfp0_rx_status_2), - .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int), - .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int), - .qsfp0_txd_3(qsfp0_txd_3_int), - .qsfp0_txc_3(qsfp0_txc_3_int), - .qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int), - .qsfp0_rx_clk_3(qsfp0_rx_clk_3_int), - .qsfp0_rx_rst_3(qsfp0_rx_rst_3_int), - .qsfp0_rxd_3(qsfp0_rxd_3_int), - .qsfp0_rxc_3(qsfp0_rxc_3_int), - .qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int), - .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int), - .qsfp0_rx_status_3(qsfp0_rx_status_3), - .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int), - .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int), - .qsfp0_txd_4(qsfp0_txd_4_int), - .qsfp0_txc_4(qsfp0_txc_4_int), - .qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int), - .qsfp0_rx_clk_4(qsfp0_rx_clk_4_int), - .qsfp0_rx_rst_4(qsfp0_rx_rst_4_int), - .qsfp0_rxd_4(qsfp0_rxd_4_int), - .qsfp0_rxc_4(qsfp0_rxc_4_int), - .qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int), - .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int), - .qsfp0_rx_status_4(qsfp0_rx_status_4), + .qsfp_tx_clk(qsfp_tx_clk), + .qsfp_tx_rst(qsfp_tx_rst), + .qsfp_txd(qsfp_txd), + .qsfp_txc(qsfp_txc), + .qsfp_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable), + .qsfp_rx_clk(qsfp_rx_clk), + .qsfp_rx_rst(qsfp_rx_rst), + .qsfp_rxd(qsfp_rxd), + .qsfp_rxc(qsfp_rxc), + .qsfp_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable), + .qsfp_rx_error_count(qsfp_rx_error_count), + .qsfp_rx_status(qsfp_rx_status), - .qsfp0_drp_clk(qsfp0_drp_clk), - .qsfp0_drp_rst(qsfp0_drp_rst), - .qsfp0_drp_addr(qsfp0_drp_addr), - .qsfp0_drp_di(qsfp0_drp_di), - .qsfp0_drp_en(qsfp0_drp_en), - .qsfp0_drp_we(qsfp0_drp_we), - .qsfp0_drp_do(qsfp0_drp_do), - .qsfp0_drp_rdy(qsfp0_drp_rdy), + .qsfp_drp_clk(qsfp_drp_clk), + .qsfp_drp_rst(qsfp_drp_rst), + .qsfp_drp_addr(qsfp_drp_addr), + .qsfp_drp_di(qsfp_drp_di), + .qsfp_drp_en(qsfp_drp_en), + .qsfp_drp_we(qsfp_drp_we), + .qsfp_drp_do(qsfp_drp_do), + .qsfp_drp_rdy(qsfp_drp_rdy), - .qsfp0_modprsl(qsfp0_modprsl_int), - .qsfp0_modsell(qsfp0_modsell), - .qsfp0_resetl(qsfp0_resetl), - .qsfp0_intl(qsfp0_intl_int), - .qsfp0_lpmode(qsfp0_lpmode), - - .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), - .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), - .qsfp1_txd_1(qsfp1_txd_1_int), - .qsfp1_txc_1(qsfp1_txc_1_int), - .qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int), - .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), - .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), - .qsfp1_rxd_1(qsfp1_rxd_1_int), - .qsfp1_rxc_1(qsfp1_rxc_1_int), - .qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int), - .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int), - .qsfp1_rx_status_1(qsfp1_rx_status_1), - .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), - .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), - .qsfp1_txd_2(qsfp1_txd_2_int), - .qsfp1_txc_2(qsfp1_txc_2_int), - .qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int), - .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), - .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), - .qsfp1_rxd_2(qsfp1_rxd_2_int), - .qsfp1_rxc_2(qsfp1_rxc_2_int), - .qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int), - .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int), - .qsfp1_rx_status_2(qsfp1_rx_status_2), - .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), - .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), - .qsfp1_txd_3(qsfp1_txd_3_int), - .qsfp1_txc_3(qsfp1_txc_3_int), - .qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int), - .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), - .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), - .qsfp1_rxd_3(qsfp1_rxd_3_int), - .qsfp1_rxc_3(qsfp1_rxc_3_int), - .qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int), - .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int), - .qsfp1_rx_status_3(qsfp1_rx_status_3), - .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), - .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), - .qsfp1_txd_4(qsfp1_txd_4_int), - .qsfp1_txc_4(qsfp1_txc_4_int), - .qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int), - .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), - .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), - .qsfp1_rxd_4(qsfp1_rxd_4_int), - .qsfp1_rxc_4(qsfp1_rxc_4_int), - .qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int), - .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int), - .qsfp1_rx_status_4(qsfp1_rx_status_4), - - .qsfp1_drp_clk(qsfp1_drp_clk), - .qsfp1_drp_rst(qsfp1_drp_rst), - .qsfp1_drp_addr(qsfp1_drp_addr), - .qsfp1_drp_di(qsfp1_drp_di), - .qsfp1_drp_en(qsfp1_drp_en), - .qsfp1_drp_we(qsfp1_drp_we), - .qsfp1_drp_do(qsfp1_drp_do), - .qsfp1_drp_rdy(qsfp1_drp_rdy), - - .qsfp1_modprsl(qsfp1_modprsl_int), - .qsfp1_modsell(qsfp1_modsell), - .qsfp1_resetl(qsfp1_resetl), - .qsfp1_intl(qsfp1_intl_int), - .qsfp1_lpmode(qsfp1_lpmode), + .qsfp_modprsl(qsfp_modprsl_int), + .qsfp_modsell(qsfp_modsell), + .qsfp_resetl(qsfp_resetl), + .qsfp_intl(qsfp_intl_int), + .qsfp_lpmode(qsfp_lpmode), /* * DDR diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v index 54ab880fb..baa9cb5d6 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v @@ -25,6 +25,8 @@ module fpga_core # parameter RELEASE_INFO = 32'h00000000, // Board configuration + parameter QSFP_CNT = 2, + parameter CH_CNT = QSFP_CNT*4, parameter CMS_ENABLE = 1, parameter TDMA_BER_ENABLE = 0, @@ -279,133 +281,33 @@ module fpga_core # /* * Ethernet: QSFP28 */ - input wire qsfp0_tx_clk_1, - input wire qsfp0_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1, - output wire qsfp0_cfg_tx_prbs31_enable_1, - input wire qsfp0_rx_clk_1, - input wire qsfp0_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1, - output wire qsfp0_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp0_rx_error_count_1, - input wire qsfp0_rx_status_1, - input wire qsfp0_tx_clk_2, - input wire qsfp0_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2, - output wire qsfp0_cfg_tx_prbs31_enable_2, - input wire qsfp0_rx_clk_2, - input wire qsfp0_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2, - output wire qsfp0_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp0_rx_error_count_2, - input wire qsfp0_rx_status_2, - input wire qsfp0_tx_clk_3, - input wire qsfp0_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3, - output wire qsfp0_cfg_tx_prbs31_enable_3, - input wire qsfp0_rx_clk_3, - input wire qsfp0_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3, - output wire qsfp0_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp0_rx_error_count_3, - input wire qsfp0_rx_status_3, - input wire qsfp0_tx_clk_4, - input wire qsfp0_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4, - output wire qsfp0_cfg_tx_prbs31_enable_4, - input wire qsfp0_rx_clk_4, - input wire qsfp0_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4, - output wire qsfp0_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp0_rx_error_count_4, - input wire qsfp0_rx_status_4, + input wire [CH_CNT-1:0] qsfp_tx_clk, + input wire [CH_CNT-1:0] qsfp_tx_rst, + output wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_txd, + output wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_txc, + output wire [CH_CNT-1:0] qsfp_cfg_tx_prbs31_enable, + input wire [CH_CNT-1:0] qsfp_rx_clk, + input wire [CH_CNT-1:0] qsfp_rx_rst, + input wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_rxd, + input wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_rxc, + output wire [CH_CNT-1:0] qsfp_cfg_rx_prbs31_enable, + input wire [CH_CNT*7-1:0] qsfp_rx_error_count, + input wire [CH_CNT-1:0] qsfp_rx_status, - input wire qsfp0_drp_clk, - input wire qsfp0_drp_rst, - output wire [23:0] qsfp0_drp_addr, - output wire [15:0] qsfp0_drp_di, - output wire qsfp0_drp_en, - output wire qsfp0_drp_we, - input wire [15:0] qsfp0_drp_do, - input wire qsfp0_drp_rdy, + input wire [QSFP_CNT-1:0] qsfp_drp_clk, + input wire [QSFP_CNT-1:0] qsfp_drp_rst, + output wire [QSFP_CNT*24-1:0] qsfp_drp_addr, + output wire [QSFP_CNT*16-1:0] qsfp_drp_di, + output wire [QSFP_CNT-1:0] qsfp_drp_en, + output wire [QSFP_CNT-1:0] qsfp_drp_we, + input wire [QSFP_CNT*16-1:0] qsfp_drp_do, + input wire [QSFP_CNT-1:0] qsfp_drp_rdy, - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - - input wire qsfp1_tx_clk_1, - input wire qsfp1_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1, - output wire qsfp1_cfg_tx_prbs31_enable_1, - input wire qsfp1_rx_clk_1, - input wire qsfp1_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1, - output wire qsfp1_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp1_rx_error_count_1, - input wire qsfp1_rx_status_1, - input wire qsfp1_tx_clk_2, - input wire qsfp1_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2, - output wire qsfp1_cfg_tx_prbs31_enable_2, - input wire qsfp1_rx_clk_2, - input wire qsfp1_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2, - output wire qsfp1_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp1_rx_error_count_2, - input wire qsfp1_rx_status_2, - input wire qsfp1_tx_clk_3, - input wire qsfp1_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3, - output wire qsfp1_cfg_tx_prbs31_enable_3, - input wire qsfp1_rx_clk_3, - input wire qsfp1_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3, - output wire qsfp1_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp1_rx_error_count_3, - input wire qsfp1_rx_status_3, - input wire qsfp1_tx_clk_4, - input wire qsfp1_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4, - output wire qsfp1_cfg_tx_prbs31_enable_4, - input wire qsfp1_rx_clk_4, - input wire qsfp1_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4, - output wire qsfp1_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp1_rx_error_count_4, - input wire qsfp1_rx_status_4, - - input wire qsfp1_drp_clk, - input wire qsfp1_drp_rst, - output wire [23:0] qsfp1_drp_addr, - output wire [15:0] qsfp1_drp_di, - output wire qsfp1_drp_en, - output wire qsfp1_drp_we, - input wire [15:0] qsfp1_drp_do, - input wire qsfp1_drp_rdy, - - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, + output wire [QSFP_CNT-1:0] qsfp_modsell, + output wire [QSFP_CNT-1:0] qsfp_resetl, + input wire [QSFP_CNT-1:0] qsfp_modprsl, + input wire [QSFP_CNT-1:0] qsfp_intl, + output wire [QSFP_CNT-1:0] qsfp_lpmode, /* * DDR @@ -500,16 +402,17 @@ parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3 localparam RB_BASE_ADDR = 16'h1000; localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; -localparam RB_DRP_QSFP0_BASE = RB_BASE_ADDR + 16'h60; -localparam RB_DRP_QSFP1_BASE = RB_DRP_QSFP0_BASE + 16'h20; +localparam RB_DRP_QSFP_BASE = RB_BASE_ADDR + 16'h60; initial begin - if (PORT_COUNT > 8) begin + if (PORT_COUNT > CH_CNT) begin $error("Error: Max port count exceeded (instance %m)"); $finish; end end +genvar n; + // AXI lite connections wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; wire [2:0] axil_csr_awprot; @@ -560,27 +463,18 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; wire ctrl_reg_rd_wait; wire ctrl_reg_rd_ack; -wire qsfp0_drp_reg_wr_wait; -wire qsfp0_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp0_drp_reg_rd_data; -wire qsfp0_drp_reg_rd_wait; -wire qsfp0_drp_reg_rd_ack; - -wire qsfp1_drp_reg_wr_wait; -wire qsfp1_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data; -wire qsfp1_drp_reg_rd_wait; -wire qsfp1_drp_reg_rd_ack; +wire qsfp_drp_reg_wr_wait[0:QSFP_CNT-1]; +wire qsfp_drp_reg_wr_ack[0:QSFP_CNT-1]; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_drp_reg_rd_data[0:QSFP_CNT-1]; +wire qsfp_drp_reg_rd_wait[0:QSFP_CNT-1]; +wire qsfp_drp_reg_rd_ack[0:QSFP_CNT-1]; reg ctrl_reg_wr_ack_reg = 1'b0; reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; reg ctrl_reg_rd_ack_reg = 1'b0; -reg qsfp0_reset_reg = 1'b0; -reg qsfp1_reset_reg = 1'b0; - -reg qsfp0_lpmode_reg = 1'b0; -reg qsfp1_lpmode_reg = 1'b0; +reg [QSFP_CNT-1:0] qsfp_reset_reg = {QSFP_CNT{1'b0}}; +reg [QSFP_CNT-1:0] qsfp_lpmode_reg = {QSFP_CNT{1'b0}}; reg i2c_scl_o_reg = 1'b1; reg i2c_sda_o_reg = 1'b1; @@ -599,20 +493,39 @@ reg [3:0] m_axil_cms_wstrb_reg = 4'b0000; reg m_axil_cms_wvalid_reg = 1'b0; reg m_axil_cms_arvalid_reg = 1'b0; -assign ctrl_reg_wr_wait = qsfp0_drp_reg_wr_wait | qsfp1_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp0_drp_reg_wr_ack | qsfp1_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp0_drp_reg_rd_data | qsfp1_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp0_drp_reg_rd_wait | qsfp1_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp0_drp_reg_rd_ack | qsfp1_drp_reg_rd_ack; +reg ctrl_reg_wr_wait_cmb; +reg ctrl_reg_wr_ack_cmb; +reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_cmb; +reg ctrl_reg_rd_wait_cmb; +reg ctrl_reg_rd_ack_cmb; -assign qsfp0_modsell = 1'b0; -assign qsfp1_modsell = 1'b0; +assign ctrl_reg_wr_wait = ctrl_reg_wr_wait_cmb; +assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_cmb; +assign ctrl_reg_rd_data = ctrl_reg_rd_data_cmb; +assign ctrl_reg_rd_wait = ctrl_reg_rd_wait_cmb; +assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_cmb; -assign qsfp0_resetl = !qsfp0_reset_reg; -assign qsfp1_resetl = !qsfp1_reset_reg; +integer k; -assign qsfp0_lpmode = qsfp0_lpmode_reg; -assign qsfp1_lpmode = qsfp1_lpmode_reg; +always @* begin + ctrl_reg_wr_wait_cmb = 1'b0; + ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_reg; + ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_reg; + ctrl_reg_rd_wait_cmb = 1'b0; + ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_reg; + + for (k = 0; k < QSFP_CNT; k = k + 1) begin + ctrl_reg_wr_wait_cmb = ctrl_reg_wr_wait_cmb | qsfp_drp_reg_wr_wait[k]; + ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_cmb | qsfp_drp_reg_wr_ack[k]; + ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_cmb | qsfp_drp_reg_rd_data[k]; + ctrl_reg_rd_wait_cmb = ctrl_reg_rd_wait_cmb | qsfp_drp_reg_rd_wait[k]; + ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_cmb | qsfp_drp_reg_rd_ack[k]; + end +end + +assign qsfp_modsell = {QSFP_CNT{1'b0}}; +assign qsfp_resetl = ~qsfp_reset_reg; +assign qsfp_lpmode = qsfp_lpmode_reg; assign i2c_scl_o = i2c_scl_o_reg; assign i2c_scl_t = i2c_scl_o_reg; @@ -640,6 +553,8 @@ assign m_axil_cms_arprot = 3'b000; assign m_axil_cms_arvalid = m_axil_cms_arvalid_reg; assign m_axil_cms_rready = 1'b1; +integer i; + always @(posedge clk_250mhz) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; @@ -671,13 +586,11 @@ always @(posedge clk_250mhz) begin // XCVR GPIO RBB+8'h1C: begin // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - qsfp0_reset_reg <= ctrl_reg_wr_data[4]; - qsfp0_lpmode_reg <= ctrl_reg_wr_data[5]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp1_reset_reg <= ctrl_reg_wr_data[12]; - qsfp1_lpmode_reg <= ctrl_reg_wr_data[13]; + for (i = 0; i < QSFP_CNT; i = i + 1) begin + if (ctrl_reg_wr_strb[i]) begin + qsfp_reset_reg[i] <= ctrl_reg_wr_data[i*8+4]; + qsfp_lpmode_reg[i] <= ctrl_reg_wr_data[i*8+5]; + end end end // QSPI flash @@ -740,14 +653,12 @@ always @(posedge clk_250mhz) begin RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // XCVR GPIO: Next header RBB+8'h1C: begin // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !qsfp0_modprsl; - ctrl_reg_rd_data_reg[1] <= !qsfp0_intl; - ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg; - ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg; - ctrl_reg_rd_data_reg[8] <= !qsfp1_modprsl; - ctrl_reg_rd_data_reg[9] <= !qsfp1_intl; - ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg; - ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg; + for (i = 0; i < QSFP_CNT; i = i + 1) begin + ctrl_reg_rd_data_reg[i*8+0] <= !qsfp_modprsl[i]; + ctrl_reg_rd_data_reg[i*8+1] <= !qsfp_intl[i]; + ctrl_reg_rd_data_reg[i*8+4] <= qsfp_reset_reg[i]; + ctrl_reg_rd_data_reg[i*8+5] <= qsfp_lpmode_reg[i]; + end end // QSPI flash RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type @@ -770,7 +681,7 @@ always @(posedge clk_250mhz) begin // Alveo BMC RBB+8'h40: ctrl_reg_rd_data_reg <= CMS_ENABLE ? 32'h0000C140 : 0; // BMC ctrl: Type RBB+8'h44: ctrl_reg_rd_data_reg <= CMS_ENABLE ? 32'h00000100 : 0; // BMC ctrl: Version - RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // BMC ctrl: Next header + RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_BASE; // BMC ctrl: Next header RBB+8'h4C: ctrl_reg_rd_data_reg <= CMS_ENABLE ? m_axil_cms_addr_reg : 0; // BMC ctrl: Addr RBB+8'h50: ctrl_reg_rd_data_reg <= CMS_ENABLE ? m_axil_cms_rdata : 0; // BMC ctrl: Data default: ctrl_reg_rd_ack_reg <= 1'b0; @@ -781,11 +692,8 @@ always @(posedge clk_250mhz) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_ack_reg <= 1'b0; - qsfp0_reset_reg <= 1'b0; - qsfp1_reset_reg <= 1'b0; - - qsfp0_lpmode_reg <= 1'b0; - qsfp1_lpmode_reg <= 1'b0; + qsfp_reset_reg <= {QSFP_CNT{1'b0}}; + qsfp_lpmode_reg <= {QSFP_CNT{1'b0}}; i2c_scl_o_reg <= 1'b1; i2c_sda_o_reg <= 1'b1; @@ -803,92 +711,54 @@ always @(posedge clk_250mhz) begin end end -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP0_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP1_BASE) -) -qsfp0_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp0_drp_reg_wr_wait), - .reg_wr_ack(qsfp0_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp0_drp_reg_rd_data), - .reg_rd_wait(qsfp0_drp_reg_rd_wait), - .reg_rd_ack(qsfp0_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy) -); - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP1_BASE), - .RB_NEXT_PTR(0) -) -qsfp1_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp1_drp_reg_wr_wait), - .reg_wr_ack(qsfp1_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp1_drp_reg_rd_data), - .reg_rd_wait(qsfp1_drp_reg_rd_wait), - .reg_rd_ack(qsfp1_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy) -); - generate +for (n = 0; n < QSFP_CNT; n = n + 1) begin : qsfp + + rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP_BASE + n*16'h20), + .RB_NEXT_PTR(RB_DRP_QSFP_BASE + (n+1)*16'h20) + ) + qsfp0_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp_drp_reg_wr_wait[n]), + .reg_wr_ack(qsfp_drp_reg_wr_ack[n]), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp_drp_reg_rd_data[n]), + .reg_rd_wait(qsfp_drp_reg_rd_wait[n]), + .reg_rd_ack(qsfp_drp_reg_rd_ack[n]), + + /* + * DRP + */ + .drp_clk(qsfp_drp_clk[n +: 1]), + .drp_rst(qsfp_drp_rst[n +: 1]), + .drp_addr(qsfp_drp_addr[n*24 +: 24]), + .drp_di(qsfp_drp_di[n*16 +: 16]), + .drp_en(qsfp_drp_en[n +: 1]), + .drp_we(qsfp_drp_we[n +: 1]), + .drp_do(qsfp_drp_do[n*16 +: 16]), + .drp_rdy(qsfp_drp_rdy[n +: 1]) + ); + +end + if (TDMA_BER_ENABLE) begin // BER tester @@ -912,11 +782,11 @@ if (TDMA_BER_ENABLE) begin tdma_ber_inst ( .clk(clk_250mhz), .rst(rst_250mhz), - .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}), - .phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}), + .phy_tx_clk(qsfp_tx_clk), + .phy_rx_clk(qsfp_rx_clk), + .phy_rx_error_count(qsfp_rx_error_count), + .phy_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable), .s_axil_awaddr(axil_csr_awaddr), .s_axil_awprot(axil_csr_awprot), .s_axil_awvalid(axil_csr_awvalid), @@ -942,22 +812,8 @@ if (TDMA_BER_ENABLE) begin end else begin - assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0; + assign qsfp_cfg_tx_prbs31_enable = {CH_CNT{1'b0}}; + assign qsfp_cfg_rx_prbs31_enable = {CH_CNT{1'b0}}; end @@ -1024,7 +880,7 @@ wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; mqnic_port_map_phy_xgmii #( - .PHY_COUNT(8), + .PHY_COUNT(CH_CNT), .PORT_MASK(PORT_MASK), .PORT_GROUP_SIZE(4), @@ -1038,17 +894,17 @@ mqnic_port_map_phy_xgmii #( ) mqnic_port_map_phy_xgmii_inst ( // towards PHY - .phy_xgmii_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}), - .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}), - .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}), - .phy_tx_status(8'hff), + .phy_xgmii_tx_clk(qsfp_tx_clk), + .phy_xgmii_tx_rst(qsfp_tx_rst), + .phy_xgmii_txd(qsfp_txd), + .phy_xgmii_txc(qsfp_txc), + .phy_tx_status({CH_CNT{1'b1}}), - .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}), - .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}), - .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}), - .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}), + .phy_xgmii_rx_clk(qsfp_rx_clk), + .phy_xgmii_rx_rst(qsfp_rx_rst), + .phy_xgmii_rxd(qsfp_rxd), + .phy_xgmii_rxc(qsfp_rxc), + .phy_rx_status(qsfp_rx_status), // towards MAC .port_xgmii_tx_clk(port_xgmii_tx_clk), @@ -1065,7 +921,6 @@ mqnic_port_map_phy_xgmii_inst ( ); generate - genvar n; for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile index d65dea17f..2e051b0ad 100644 --- a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile @@ -10,8 +10,9 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps DUT = fpga_core -TOPLEVEL = $(DUT) +TOPLEVEL = test_$(DUT) MODULE = test_$(DUT) +VERILOG_SOURCES += $(TOPLEVEL).v VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py index f65c69d52..fc6b0897e 100644 --- a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -52,11 +52,11 @@ class TB(object): pcie_link_width=16, user_clk_frequency=250e6, alignment="dword", - cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, - cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, - rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, + cq_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, + cc_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, + rq_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, + rc_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, + rc_4tlp_straddle=len(dut.uut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, pf_count=1, max_payload_size=1024, enable_client_tag=True, @@ -268,9 +268,9 @@ class TB(object): self.driver = mqnic.Driver() - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + self.dev.functions[0].configure_bar(0, 2**len(dut.uut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.uut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.uut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) dut.ptp_rst.setimmediatevalue(0) @@ -280,28 +280,23 @@ class TB(object): self.qsfp_source = [] self.qsfp_sink = [] - for x in range(2): - sources = [] - sinks = [] - for y in range(1, 5): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) - source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) - sources.append(source) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) - sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) - sinks.append(sink) - getattr(dut, f"qsfp{x}_rx_status_{y}").setimmediatevalue(1) - getattr(dut, f"qsfp{x}_rx_error_count_{y}").setimmediatevalue(0) - self.qsfp_source.append(sources) - self.qsfp_sink.append(sinks) + for ch in self.dut.ch: + cocotb.start_soon(Clock(ch.ch_rx_clk, 2.56, units="ns").start()) + source = XgmiiSource(ch.ch_rxd, ch.ch_rxc, ch.ch_rx_clk, ch.ch_rx_rst) + self.qsfp_source.append(source) + cocotb.start_soon(Clock(ch.ch_tx_clk, 2.56, units="ns").start()) + sink = XgmiiSink(ch.ch_txd, ch.ch_txc, ch.ch_tx_clk, ch.ch_tx_rst) + self.qsfp_sink.append(sink) + ch.ch_rx_status.setimmediatevalue(1) + ch.ch_rx_error_count.setimmediatevalue(0) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_drp_clk"), 8, units="ns").start()) - getattr(dut, f"qsfp{x}_drp_rst").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_drp_do").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_drp_rdy").setimmediatevalue(0) + cocotb.start_soon(Clock(dut.qsfp_drp_clk, 8, units="ns").start()) + dut.qsfp_drp_rst.setimmediatevalue(0) + dut.qsfp_drp_do.setimmediatevalue(0) + dut.qsfp_drp_rdy.setimmediatevalue(0) - getattr(dut, f"qsfp{x}_modprsl").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_intl").setimmediatevalue(1) + dut.qsfp_modprsl.setimmediatevalue(0) + dut.qsfp_intl.setimmediatevalue(1) dut.sw.setimmediatevalue(0) @@ -310,7 +305,7 @@ class TB(object): dut.qspi_dq_i.setimmediatevalue(0) - self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024) + self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut.uut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024) self.loopback_enable = False cocotb.start_soon(self._run_loopback()) @@ -318,19 +313,17 @@ class TB(object): async def init(self): self.dut.ptp_rst.setimmediatevalue(0) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) + for ch in self.dut.ch: + ch.ch_rx_rst.setimmediatevalue(0) + ch.ch_tx_rst.setimmediatevalue(0) await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.ptp_rst.setimmediatevalue(1) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(1) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(1) + for ch in self.dut.ch: + ch.ch_rx_rst.setimmediatevalue(1) + ch.ch_tx_rst.setimmediatevalue(1) await FallingEdge(self.dut.rst_250mhz) await Timer(100, 'ns') @@ -339,10 +332,9 @@ class TB(object): await RisingEdge(self.dut.clk_250mhz) self.dut.ptp_rst.setimmediatevalue(0) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) + for ch in self.dut.ch: + ch.ch_rx_rst.setimmediatevalue(0) + ch.ch_tx_rst.setimmediatevalue(0) await self.rc.enumerate() @@ -352,15 +344,14 @@ class TB(object): if self.loopback_enable: for x in range(len(self.qsfp_sink)): - for y in range(len(self.qsfp_sink[x])): - if not self.qsfp_sink[x][y].empty(): - await self.qsfp_source[x][y].send(await self.qsfp_sink[x][y].recv()) + if not self.qsfp_sink[x].empty(): + await self.qsfp_source[x].send(await self.qsfp_sink[x].recv()) @cocotb.test() async def run_test_nic(dut): - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) + tb = TB(dut, msix_count=2**len(dut.uut.core_inst.core_pcie_inst.irq_index)) await tb.init() @@ -385,10 +376,10 @@ async def run_test_nic(dut): await tb.driver.interfaces[0].start_xmit(data, 0) - pkt = await tb.qsfp_sink[0][0].recv() + pkt = await tb.qsfp_sink[0].recv() tb.log.info("Packet: %s", pkt) - await tb.qsfp_source[0][0].send(pkt) + await tb.qsfp_source[0].send(pkt) pkt = await tb.driver.interfaces[0].recv() @@ -397,10 +388,10 @@ async def run_test_nic(dut): # await tb.driver.interfaces[1].start_xmit(data, 0) - # pkt = await tb.qsfp_sink[1][0].recv() + # pkt = await tb.qsfp_sink[4].recv() # tb.log.info("Packet: %s", pkt) - # await tb.qsfp_source[1][0].send(pkt) + # await tb.qsfp_source[4].send(pkt) # pkt = await tb.driver.interfaces[1].recv() @@ -420,10 +411,10 @@ async def run_test_nic(dut): await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - pkt = await tb.qsfp_sink[0][0].recv() + pkt = await tb.qsfp_sink[0].recv() tb.log.info("Packet: %s", pkt) - await tb.qsfp_source[0][0].send(pkt) + await tb.qsfp_source[0].send(pkt) pkt = await tb.driver.interfaces[0].recv() @@ -537,7 +528,7 @@ async def run_test_nic(dut): lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000) - await tb.qsfp_source[0][0].send(XgmiiFrame.from_payload(bytes(lfc_xoff))) + await tb.qsfp_source[0].send(XgmiiFrame.from_payload(bytes(lfc_xoff))) count = 16 @@ -577,9 +568,10 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) def test_fpga_core(request): dut = "fpga_core" module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut + toplevel = f"test_{dut}" verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.v"), os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v new file mode 100644 index 000000000..1af6c2b7a --- /dev/null +++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v @@ -0,0 +1,842 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Testbench top-level module + */ +module test_fpga_core # +( + // FW and board IDs + parameter FPGA_ID = 32'h4B37093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h10ee_90c8, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter QSFP_CNT = 2, + parameter CH_CNT = QSFP_CNT*4, + parameter CMS_ENABLE = 1, + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 1024, + parameter PTP_CLK_PERIOD_NS_DENOM = 165, + parameter PTP_TS_WIDTH = 96, + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 0, + parameter PTP_PEROUT_COUNT = 1, + parameter IF_PTP_PERIOD_NS = 6'h6, + parameter IF_PTP_PERIOD_FNS = 16'h6666, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_TAG_WIDTH = 16, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter PFC_ENABLE = 1, + parameter LFC_ENABLE = PFC_ENABLE, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 0, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_WIDTH = 512, + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, + parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, + parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, + parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, + parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, + parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + parameter PCIE_TAG_COUNT = 256, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter XGMII_DATA_WIDTH = 64, + parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, + parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, + parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, + parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, + parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, + parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + parameter AXIS_ETH_TX_PIPELINE = 4, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, + parameter AXIS_ETH_TX_TS_PIPELINE = 4, + parameter AXIS_ETH_RX_PIPELINE = 4, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 250 MHz + * Synchronous reset + */ + input wire clk_250mhz, + input wire rst_250mhz, + + /* + * PTP clock + */ + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + + /* + * GPIO + */ + input wire [3:0] sw, + output wire [2:0] led, + + /* + * I2C + */ + input wire i2c_scl_i, + output wire i2c_scl_o, + output wire i2c_scl_t, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_t, + + /* + * PCIe + */ + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tlast, + input wire m_axis_rq_tready, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, + output wire m_axis_rq_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tlast, + output wire s_axis_rc_tready, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, + input wire s_axis_rc_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tlast, + output wire s_axis_cq_tready, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, + input wire s_axis_cq_tvalid, + + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tlast, + input wire m_axis_cc_tready, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, + output wire m_axis_cc_tvalid, + + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, + input wire s_axis_rq_seq_num_valid_0, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, + input wire s_axis_rq_seq_num_valid_1, + + input wire [1:0] pcie_tfc_nph_av, + input wire [1:0] pcie_tfc_npd_av, + + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, + input wire [3:0] cfg_rcb_status, + + output wire [9:0] cfg_mgmt_addr, + output wire [7:0] cfg_mgmt_function_number, + output wire cfg_mgmt_write, + output wire [31:0] cfg_mgmt_write_data, + output wire [3:0] cfg_mgmt_byte_enable, + output wire cfg_mgmt_read, + input wire [31:0] cfg_mgmt_read_data, + input wire cfg_mgmt_read_write_done, + + input wire [7:0] cfg_fc_ph, + input wire [11:0] cfg_fc_pd, + input wire [7:0] cfg_fc_nph, + input wire [11:0] cfg_fc_npd, + input wire [7:0] cfg_fc_cplh, + input wire [11:0] cfg_fc_cpld, + output wire [2:0] cfg_fc_sel, + + input wire [3:0] cfg_interrupt_msix_enable, + input wire [3:0] cfg_interrupt_msix_mask, + input wire [251:0] cfg_interrupt_msix_vf_enable, + input wire [251:0] cfg_interrupt_msix_vf_mask, + output wire [63:0] cfg_interrupt_msix_address, + output wire [31:0] cfg_interrupt_msix_data, + output wire cfg_interrupt_msix_int, + output wire [1:0] cfg_interrupt_msix_vec_pending, + input wire cfg_interrupt_msix_vec_pending_status, + input wire cfg_interrupt_msix_sent, + input wire cfg_interrupt_msix_fail, + output wire [7:0] cfg_interrupt_msi_function_number, + + output wire status_error_cor, + output wire status_error_uncor, + + /* + * Ethernet: QSFP28 + */ + // input wire [CH_CNT-1:0] qsfp_tx_clk, + // input wire [CH_CNT-1:0] qsfp_tx_rst, + // output wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_txd, + // output wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_txc, + // output wire [CH_CNT-1:0] qsfp_cfg_tx_prbs31_enable, + // input wire [CH_CNT-1:0] qsfp_rx_clk, + // input wire [CH_CNT-1:0] qsfp_rx_rst, + // input wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_rxd, + // input wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_rxc, + // output wire [CH_CNT-1:0] qsfp_cfg_rx_prbs31_enable, + // input wire [CH_CNT*7-1:0] qsfp_rx_error_count, + // input wire [CH_CNT-1:0] qsfp_rx_status, + + input wire [QSFP_CNT-1:0] qsfp_drp_clk, + input wire [QSFP_CNT-1:0] qsfp_drp_rst, + output wire [QSFP_CNT*24-1:0] qsfp_drp_addr, + output wire [QSFP_CNT*16-1:0] qsfp_drp_di, + output wire [QSFP_CNT-1:0] qsfp_drp_en, + output wire [QSFP_CNT-1:0] qsfp_drp_we, + input wire [QSFP_CNT*16-1:0] qsfp_drp_do, + input wire [QSFP_CNT-1:0] qsfp_drp_rdy, + + output wire [QSFP_CNT-1:0] qsfp_modsell, + output wire [QSFP_CNT-1:0] qsfp_resetl, + input wire [QSFP_CNT-1:0] qsfp_modprsl, + input wire [QSFP_CNT-1:0] qsfp_intl, + output wire [QSFP_CNT-1:0] qsfp_lpmode, + + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * QSPI flash + */ + output wire fpga_boot, + output wire qspi_clk, + input wire [3:0] qspi_dq_i, + output wire [3:0] qspi_dq_o, + output wire [3:0] qspi_dq_oe, + output wire qspi_cs, + + /* + * AXI-Lite interface to CMS + */ + output wire m_axil_cms_clk, + output wire m_axil_cms_rst, + output wire [17:0] m_axil_cms_awaddr, + output wire [2:0] m_axil_cms_awprot, + output wire m_axil_cms_awvalid, + input wire m_axil_cms_awready, + output wire [31:0] m_axil_cms_wdata, + output wire [3:0] m_axil_cms_wstrb, + output wire m_axil_cms_wvalid, + input wire m_axil_cms_wready, + input wire [1:0] m_axil_cms_bresp, + input wire m_axil_cms_bvalid, + output wire m_axil_cms_bready, + output wire [17:0] m_axil_cms_araddr, + output wire [2:0] m_axil_cms_arprot, + output wire m_axil_cms_arvalid, + input wire m_axil_cms_arready, + input wire [31:0] m_axil_cms_rdata, + input wire [1:0] m_axil_cms_rresp, + input wire m_axil_cms_rvalid, + output wire m_axil_cms_rready +); + +genvar n; + +wire [CH_CNT-1:0] qsfp_tx_clk; +wire [CH_CNT-1:0] qsfp_tx_rst; +wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_txd; +wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_txc; +wire [CH_CNT-1:0] qsfp_cfg_tx_prbs31_enable; +wire [CH_CNT-1:0] qsfp_rx_clk; +wire [CH_CNT-1:0] qsfp_rx_rst; +wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_rxd; +wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_rxc; +wire [CH_CNT-1:0] qsfp_cfg_rx_prbs31_enable; +wire [CH_CNT*7-1:0] qsfp_rx_error_count; +wire [CH_CNT-1:0] qsfp_rx_status; + +generate + +for (n = 0; n < CH_CNT; n = n + 1) begin : ch + + wire ch_tx_clk; + wire ch_tx_rst; + wire [XGMII_DATA_WIDTH-1:0] ch_txd; + wire [XGMII_CTRL_WIDTH-1:0] ch_txc; + wire ch_cfg_tx_prbs31_enable; + wire ch_rx_clk; + wire ch_rx_rst; + wire [XGMII_DATA_WIDTH-1:0] ch_rxd; + wire [XGMII_CTRL_WIDTH-1:0] ch_rxc; + wire ch_cfg_rx_prbs31_enable; + wire [6:0] ch_rx_error_count; + wire ch_rx_status; + + assign qsfp_tx_clk[n +: 1] = ch_tx_clk; + assign qsfp_tx_rst[n +: 1] = ch_tx_rst; + assign ch_txd = qsfp_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]; + assign ch_txc = qsfp_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]; + assign ch_cfg_tx_prbs31_enable = qsfp_cfg_tx_prbs31_enable[n +: 1]; + assign qsfp_rx_clk[n +: 1] = ch_rx_clk; + assign qsfp_rx_rst[n +: 1] = ch_rx_rst; + assign qsfp_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH] = ch_rxd; + assign qsfp_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH] = ch_rxc; + assign ch_cfg_rx_prbs31_enable = qsfp_cfg_rx_prbs31_enable[n +: 1]; + assign qsfp_rx_error_count[n*7 +: 7] = ch_rx_error_count; + assign qsfp_rx_status[n +: 1] = ch_rx_status; + +end + +endgenerate + +fpga_core #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Board configuration + .QSFP_CNT(QSFP_CNT), + .CH_CNT(CH_CNT), + .CMS_ENABLE(CMS_ENABLE), + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + .PORT_MASK(PORT_MASK), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + .IF_PTP_PERIOD_NS(IF_PTP_PERIOD_NS), + .IF_PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .PFC_ENABLE(PFC_ENABLE), + .LFC_ENABLE(LFC_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RC_STRADDLE(RC_STRADDLE), + .RQ_STRADDLE(RQ_STRADDLE), + .CQ_STRADDLE(CQ_STRADDLE), + .CC_STRADDLE(CC_STRADDLE), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +uut ( + /* + * Clock: 250 MHz + * Synchronous reset + */ + .clk_250mhz(clk_250mhz), + .rst_250mhz(rst_250mhz), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + + /* + * GPIO + */ + .sw(sw), + .led(led), + + /* + * I2C + */ + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_scl_t(i2c_scl_t), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o), + .i2c_sda_t(i2c_sda_t), + + /* + * PCIe + */ + .m_axis_rq_tdata(m_axis_rq_tdata), + .m_axis_rq_tkeep(m_axis_rq_tkeep), + .m_axis_rq_tlast(m_axis_rq_tlast), + .m_axis_rq_tready(m_axis_rq_tready), + .m_axis_rq_tuser(m_axis_rq_tuser), + .m_axis_rq_tvalid(m_axis_rq_tvalid), + + .s_axis_rc_tdata(s_axis_rc_tdata), + .s_axis_rc_tkeep(s_axis_rc_tkeep), + .s_axis_rc_tlast(s_axis_rc_tlast), + .s_axis_rc_tready(s_axis_rc_tready), + .s_axis_rc_tuser(s_axis_rc_tuser), + .s_axis_rc_tvalid(s_axis_rc_tvalid), + + .s_axis_cq_tdata(s_axis_cq_tdata), + .s_axis_cq_tkeep(s_axis_cq_tkeep), + .s_axis_cq_tlast(s_axis_cq_tlast), + .s_axis_cq_tready(s_axis_cq_tready), + .s_axis_cq_tuser(s_axis_cq_tuser), + .s_axis_cq_tvalid(s_axis_cq_tvalid), + + .m_axis_cc_tdata(m_axis_cc_tdata), + .m_axis_cc_tkeep(m_axis_cc_tkeep), + .m_axis_cc_tlast(m_axis_cc_tlast), + .m_axis_cc_tready(m_axis_cc_tready), + .m_axis_cc_tuser(m_axis_cc_tuser), + .m_axis_cc_tvalid(m_axis_cc_tvalid), + + .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), + .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), + .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), + .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * Ethernet: QSFP28 + */ + .qsfp_tx_clk(qsfp_tx_clk), + .qsfp_tx_rst(qsfp_tx_rst), + .qsfp_txd(qsfp_txd), + .qsfp_txc(qsfp_txc), + .qsfp_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable), + .qsfp_rx_clk(qsfp_rx_clk), + .qsfp_rx_rst(qsfp_rx_rst), + .qsfp_rxd(qsfp_rxd), + .qsfp_rxc(qsfp_rxc), + .qsfp_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable), + .qsfp_rx_error_count(qsfp_rx_error_count), + .qsfp_rx_status(qsfp_rx_status), + + .qsfp_drp_clk(qsfp_drp_clk), + .qsfp_drp_rst(qsfp_drp_rst), + .qsfp_drp_addr(qsfp_drp_addr), + .qsfp_drp_di(qsfp_drp_di), + .qsfp_drp_en(qsfp_drp_en), + .qsfp_drp_we(qsfp_drp_we), + .qsfp_drp_do(qsfp_drp_do), + .qsfp_drp_rdy(qsfp_drp_rdy), + + .qsfp_modsell(qsfp_modsell), + .qsfp_resetl(qsfp_resetl), + .qsfp_modprsl(qsfp_modprsl), + .qsfp_intl(qsfp_intl), + .qsfp_lpmode(qsfp_lpmode), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk), + .qspi_dq_i(qspi_dq_i), + .qspi_dq_o(qspi_dq_o), + .qspi_dq_oe(qspi_dq_oe), + .qspi_cs(qspi_cs), + + /* + * AXI-Lite interface to CMS + */ + .m_axil_cms_clk(m_axil_cms_clk), + .m_axil_cms_rst(m_axil_cms_rst), + .m_axil_cms_awaddr(m_axil_cms_awaddr), + .m_axil_cms_awprot(m_axil_cms_awprot), + .m_axil_cms_awvalid(m_axil_cms_awvalid), + .m_axil_cms_awready(m_axil_cms_awready), + .m_axil_cms_wdata(m_axil_cms_wdata), + .m_axil_cms_wstrb(m_axil_cms_wstrb), + .m_axil_cms_wvalid(m_axil_cms_wvalid), + .m_axil_cms_wready(m_axil_cms_wready), + .m_axil_cms_bresp(m_axil_cms_bresp), + .m_axil_cms_bvalid(m_axil_cms_bvalid), + .m_axil_cms_bready(m_axil_cms_bready), + .m_axil_cms_araddr(m_axil_cms_araddr), + .m_axil_cms_arprot(m_axil_cms_arprot), + .m_axil_cms_arvalid(m_axil_cms_arvalid), + .m_axil_cms_arready(m_axil_cms_arready), + .m_axil_cms_rdata(m_axil_cms_rdata), + .m_axil_cms_rresp(m_axil_cms_rresp), + .m_axil_cms_rvalid(m_axil_cms_rvalid), + .m_axil_cms_rready(m_axil_cms_rready) +); + +endmodule + +`resetall