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fpga: Add clock info register block

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-10-15 19:45:02 -07:00
parent 6fa30bc94c
commit d3942da875
150 changed files with 703 additions and 8 deletions
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1
docs/source/rb/index.rst
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@ -70,6 +70,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea
0x0000C005 0x00000200 application
0x0000C006 0x00000100 stats
0x0000C007 0x00000100 IRQ config
0x0000C008 0x00000100 Clock info
0x0000C010 0x00000100 :ref:`rb_cqm_event`
0x0000C020 0x00000100 :ref:`rb_qm_tx`
0x0000C021 0x00000100 :ref:`rb_qm_rx`

1
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v

1
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -875,6 +875,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),

1
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
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@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v

1
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -715,6 +715,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),

66
fpga/common/rtl/mqnic_core.v
View File

@ -606,6 +606,7 @@ parameter AXIS_IF_RX_USER_WIDTH = AXIS_RX_USER_WIDTH;
localparam CLK_CYCLES_PER_US = (1000*CLK_PERIOD_NS_DENOM)/CLK_PERIOD_NS_NUM;
localparam PHC_RB_BASE_ADDR = 32'h100;
localparam CLK_RB_BASE_ADDR = PHC_RB_BASE_ADDR + 32'h100;
// check configuration
initial begin
@ -743,17 +744,23 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ptp_ctrl_reg_rd_data;
wire ptp_ctrl_reg_rd_wait;
wire ptp_ctrl_reg_rd_ack;
wire clk_ctrl_reg_wr_wait;
wire clk_ctrl_reg_wr_ack;
wire [AXIL_CTRL_DATA_WIDTH-1:0] clk_ctrl_reg_rd_data;
wire clk_ctrl_reg_rd_wait;
wire clk_ctrl_reg_rd_ack;
reg ctrl_reg_wr_ack_reg = 1'b0;
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0;
reg [15:0] irq_rate_limit_min_interval_reg = 10;
assign ctrl_reg_wr_wait_int = ctrl_reg_wr_wait | ptp_ctrl_reg_wr_wait;
assign ctrl_reg_wr_ack_int = ctrl_reg_wr_ack | ctrl_reg_wr_ack_reg | ptp_ctrl_reg_wr_ack;
assign ctrl_reg_rd_data_int = ctrl_reg_rd_data | ctrl_reg_rd_data_reg | ptp_ctrl_reg_rd_data;
assign ctrl_reg_rd_wait_int = ctrl_reg_rd_wait | ptp_ctrl_reg_rd_wait;
assign ctrl_reg_rd_ack_int = ctrl_reg_rd_ack | ctrl_reg_rd_ack_reg | ptp_ctrl_reg_rd_ack;
assign ctrl_reg_wr_wait_int = ctrl_reg_wr_wait | ptp_ctrl_reg_wr_wait | clk_ctrl_reg_wr_wait;
assign ctrl_reg_wr_ack_int = ctrl_reg_wr_ack | ctrl_reg_wr_ack_reg | ptp_ctrl_reg_wr_ack | clk_ctrl_reg_wr_ack;
assign ctrl_reg_rd_data_int = ctrl_reg_rd_data | ctrl_reg_rd_data_reg | ptp_ctrl_reg_rd_data | clk_ctrl_reg_rd_data;
assign ctrl_reg_rd_wait_int = ctrl_reg_rd_wait | ptp_ctrl_reg_rd_wait | clk_ctrl_reg_rd_wait;
assign ctrl_reg_rd_ack_int = ctrl_reg_rd_ack | ctrl_reg_rd_ack_reg | ptp_ctrl_reg_rd_ack | clk_ctrl_reg_rd_ack;
always @(posedge clk) begin
ctrl_reg_wr_ack_reg <= 1'b0;
@ -836,7 +843,7 @@ mqnic_ptp #(
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.RB_BASE_ADDR(PHC_RB_BASE_ADDR),
.RB_NEXT_PTR(RB_NEXT_PTR)
.RB_NEXT_PTR(CLK_RB_BASE_ADDR)
)
mqnic_ptp_inst (
.clk(clk),
@ -875,6 +882,50 @@ mqnic_ptp_inst (
.ptp_perout_pulse(ptp_perout_pulse)
);
localparam CLK_CNT = PORT_COUNT*2;
wire [CLK_CNT-1:0] all_clocks;
mqnic_rb_clk_info #(
.CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM),
.CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM),
.REF_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.REF_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.CH_CNT(PORT_COUNT*2),
.REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.RB_BASE_ADDR(CLK_RB_BASE_ADDR),
.RB_NEXT_PTR(RB_NEXT_PTR)
)
mqnic_rb_clk_info_inst (
.clk(clk),
.rst(rst),
/*
* Register interface
*/
.reg_wr_addr(ctrl_reg_wr_addr),
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(clk_ctrl_reg_wr_wait),
.reg_wr_ack(clk_ctrl_reg_wr_ack),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(clk_ctrl_reg_rd_data),
.reg_rd_wait(clk_ctrl_reg_rd_wait),
.reg_rd_ack(clk_ctrl_reg_rd_ack),
/*
* Clock inputs
*/
.ref_clk(ptp_clk),
.ref_rst(ptp_rst),
.ch_clk(all_clocks)
);
localparam CTRL_XBAR_MAIN_OFFSET = 0;
localparam CTRL_XBAR_APP_OFFSET = CTRL_XBAR_MAIN_OFFSET + 1;
localparam CTRL_XBAR_S_COUNT = CTRL_XBAR_APP_OFFSET + (APP_ENABLE && APP_CTRL_ENABLE ? 1 : 0);
@ -2996,6 +3047,9 @@ generate
assign app_direct_rx_clk[n*PORTS_PER_IF+m] = port_rx_clk;
assign app_direct_rx_rst[n*PORTS_PER_IF+m] = port_rx_rst;
assign all_clocks[(n*PORTS_PER_IF+m)*2+0] = port_tx_clk;
assign all_clocks[(n*PORTS_PER_IF+m)*2+1] = port_rx_clk;
wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_96;
wire port_rx_ptp_ts_step;

273
fpga/common/rtl/mqnic_rb_clk_info.v Normal file
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@ -0,0 +1,273 @@
/*
Copyright 2022, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Clock info register block
*/
module mqnic_rb_clk_info #
(
parameter CLK_PERIOD_NS_NUM = 4,
parameter CLK_PERIOD_NS_DENOM = 1,
parameter REF_CLK_PERIOD_NS_NUM = 32,
parameter REF_CLK_PERIOD_NS_DENOM = 5,
parameter CH_CNT = 2,
parameter REG_ADDR_WIDTH = 16,
parameter REG_DATA_WIDTH = 32,
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
parameter RB_TYPE = 32'h0000C008,
parameter RB_BASE_ADDR = 0,
parameter RB_NEXT_PTR = 0
)
(
input wire clk,
input wire rst,
/*
* Register interface
*/
input wire [REG_ADDR_WIDTH-1:0] reg_wr_addr,
input wire [REG_DATA_WIDTH-1:0] reg_wr_data,
input wire [REG_STRB_WIDTH-1:0] reg_wr_strb,
input wire reg_wr_en,
output wire reg_wr_wait,
output wire reg_wr_ack,
input wire [REG_ADDR_WIDTH-1:0] reg_rd_addr,
input wire reg_rd_en,
output wire [REG_DATA_WIDTH-1:0] reg_rd_data,
output wire reg_rd_wait,
output wire reg_rd_ack,
/*
* Clock inputs
*/
input wire ref_clk,
input wire ref_rst,
input wire [CH_CNT-1:0] ch_clk
);
localparam SHIFT = 8;
localparam RESOLUTION = 30;
localparam REF_CLK_CYCLES_PER_SEC = (64'd1_000_000_000*REF_CLK_PERIOD_NS_DENOM)/REF_CLK_PERIOD_NS_NUM;
localparam REF_CNT_WIDTH = $clog2(REF_CLK_CYCLES_PER_SEC >> SHIFT);
localparam CH_PRESCALE_WIDTH = 3;
localparam CNT_WIDTH = RESOLUTION-SHIFT;
localparam CH_CNT_WIDTH = CNT_WIDTH-CH_PRESCALE_WIDTH;
localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
// check configuration
initial begin
if (REG_DATA_WIDTH != 32) begin
$error("Error: Register interface width must be 32 (instance %m)");
$finish;
end
if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
$error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (REG_ADDR_WIDTH < 5) begin
$error("Error: Register address width too narrow (instance %m)");
$finish;
end
if (REG_ADDR_WIDTH < $clog2(32 + CH_CNT*4)) begin
$error("Error: Register address width too narrow (instance %m)");
$finish;
end
if (RB_NEXT_PTR && RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 32 + CH_CNT*4) begin
$error("Error: RB_NEXT_PTR overlaps block (instance %m)");
$finish;
end
end
// generate periodic strobe from ref clock for measurement period
reg [REF_CNT_WIDTH-1:0] ref_cnt_reg = 0;
reg ref_strb_reg = 0;
always @(posedge ref_clk) begin
if (ref_cnt_reg) begin
ref_cnt_reg <= ref_cnt_reg - 1;
end else begin
ref_cnt_reg <= (REF_CLK_CYCLES_PER_SEC >> SHIFT) - 1;
ref_strb_reg <= !ref_strb_reg;
end
if (ref_rst) begin
ref_cnt_reg <= 0;
ref_strb_reg <= 0;
end
end
reg ref_strb_sync_1_reg = 0;
reg ref_strb_sync_2_reg = 0;
reg ref_strb_sync_3_reg = 0;
always @(posedge clk) begin
ref_strb_sync_1_reg <= ref_strb_reg;
ref_strb_sync_2_reg <= ref_strb_sync_1_reg;
ref_strb_sync_3_reg <= ref_strb_sync_2_reg;
end
// divide and sync each input clock
wire [CH_CNT-1:0] ch_flag;
generate
genvar ch;
for (ch = 0; ch < CH_CNT; ch = ch + 1) begin : channel
reg [CH_PRESCALE_WIDTH+1-1:0] ch_prescale_reg = 0;
always @(posedge ch_clk[ch]) begin
ch_prescale_reg <= ch_prescale_reg + 1;
end
reg ch_flag_sync_1_reg = 0;
reg ch_flag_sync_2_reg = 0;
reg ch_flag_sync_3_reg = 0;
always @(posedge clk) begin
ch_flag_sync_1_reg <= ch_prescale_reg[CH_PRESCALE_WIDTH];
ch_flag_sync_2_reg <= ch_flag_sync_1_reg;
ch_flag_sync_3_reg <= ch_flag_sync_2_reg;
end
assign ch_flag[ch] = ch_flag_sync_3_reg ^ ch_flag_sync_2_reg;
end
endgenerate
// control registers
reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0;
reg reg_rd_ack_reg = 1'b0;
reg [CNT_WIDTH-1:0] clk_acc_reg = 0;
reg [CNT_WIDTH-1:0] clk_cnt_reg = 0;
reg [CH_CNT_WIDTH-1:0] ch_acc_reg[0:CH_CNT-1];
reg [CH_CNT_WIDTH-1:0] ch_cnt_reg[0:CH_CNT-1];
wire [CH_CNT_WIDTH-1:0] ch_acc_reg_0 = ch_acc_reg[0];
wire [CH_CNT_WIDTH-1:0] ch_cnt_reg_0 = ch_cnt_reg[0];
assign reg_wr_wait = 1'b0;
assign reg_wr_ack = 1'b0;
assign reg_rd_data = reg_rd_data_reg;
assign reg_rd_wait = 1'b0;
assign reg_rd_ack = reg_rd_ack_reg;
integer k;
initial begin
for (k = 0; k < CH_CNT; k = k + 1) begin
ch_acc_reg[k] = 0;
ch_cnt_reg[k] = 0;
end
end
always @(posedge clk) begin
reg_rd_data_reg <= 0;
reg_rd_ack_reg <= 1'b0;
if (ref_strb_sync_3_reg ^ ref_strb_sync_2_reg) begin
clk_acc_reg <= 1;
clk_cnt_reg <= clk_acc_reg;
end else begin
clk_acc_reg <= clk_acc_reg + 1;
end
for (k = 0; k < CH_CNT; k = k + 1) begin
if (ref_strb_sync_3_reg ^ ref_strb_sync_2_reg) begin
ch_acc_reg[k] <= ch_flag[k];
ch_cnt_reg[k] <= ch_acc_reg[k];
end else begin
ch_acc_reg[k] <= ch_acc_reg[k] + ch_flag[k];
end
end
if (reg_rd_en && !reg_rd_ack_reg) begin
// read operation
reg_rd_ack_reg <= 1'b1;
case ({reg_rd_addr >> 2, 2'b00})
RBB+5'h00: reg_rd_data_reg <= RB_TYPE; // Type
RBB+5'h04: reg_rd_data_reg <= 32'h00000100; // Version
RBB+5'h08: reg_rd_data_reg <= RB_NEXT_PTR; // Next header
RBB+5'h0C: reg_rd_data_reg <= CH_CNT;
RBB+5'h10: begin
reg_rd_data_reg[31:16] <= REF_CLK_PERIOD_NS_NUM;
reg_rd_data_reg[15:0] <= REF_CLK_PERIOD_NS_DENOM;
end
RBB+5'h18: begin
reg_rd_data_reg[31:16] <= CLK_PERIOD_NS_NUM;
reg_rd_data_reg[15:0] <= CLK_PERIOD_NS_DENOM;
end
RBB+5'h1C: reg_rd_data_reg <= clk_cnt_reg << SHIFT;
default: reg_rd_ack_reg <= 1'b0;
endcase
for (k = 0; k < CH_CNT; k = k + 1) begin
if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h20 + k*4) begin
reg_rd_data_reg <= ch_cnt_reg[k] << (SHIFT+CH_PRESCALE_WIDTH);
reg_rd_ack_reg <= 1'b1;
end
end
end
if (rst) begin
reg_rd_ack_reg <= 1'b0;
clk_acc_reg <= 0;
clk_cnt_reg <= 0;
for (k = 0; k < CH_CNT; k = k + 1) begin
ch_acc_reg[k] <= 0;
ch_cnt_reg[k] <= 0;
end
end
end
endmodule
`resetall

44
fpga/common/syn/vivado/mqnic_rb_clk_info.tcl Normal file
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@ -0,0 +1,44 @@
# Copyright 2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
# PTP clock timing constraints
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_rb_clk_info || REF_NAME == mqnic_rb_clk_info)}] {
puts "Inserting timing constraints for mqnic_rb_clk_info instance $inst"
set clk [get_clocks -of_objects [get_pins "$inst/ref_strb_sync_1_reg_reg/C"]]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/ref_strb_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/ref_strb_reg_reg"] -to [get_cells "$inst/ref_strb_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $clk]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/channel\\\[\\d+\\\]\\.ch_flag_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/channel[*].ch_prescale_reg_reg[*]"] -to [get_cells "$inst/channel[*].ch_flag_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $clk]
}

13
fpga/common/tb/mqnic.py
View File

@ -98,13 +98,24 @@ MQNIC_RB_GECKO_BMC_REG_STATUS = 0x0C
MQNIC_RB_GECKO_BMC_REG_DATA = 0x10
MQNIC_RB_GECKO_BMC_REG_CMD = 0x14
MQNIC_RB_STATS_TYPE = 0x0000C004
MQNIC_RB_STATS_TYPE = 0x0000C006
MQNIC_RB_STATS_VER = 0x00000100
MQNIC_RB_STATS_REG_OFFSET = 0x0C
MQNIC_RB_STATS_REG_COUNT = 0x10
MQNIC_RB_STATS_REG_STRIDE = 0x14
MQNIC_RB_STATS_REG_FLAGS = 0x18
MQNIC_RB_IRQ_TYPE = 0x0000C007
MQNIC_RB_IRQ_VER = 0x00000100
MQNIC_RB_CLK_INFO_TYPE = 0x0000C008
MQNIC_RB_CLK_INFO_VER = 0x00000100
MQNIC_RB_CLK_INFO_COUNT = 0x0C
MQNIC_RB_CLK_INFO_REF_NOM_PER = 0x10
MQNIC_RB_CLK_INFO_CLK_NOM_PER = 0x18
MQNIC_RB_CLK_INFO_CLK_FREQ = 0x1C
MQNIC_RB_CLK_INFO_FREQ_BASE = 0x20
MQNIC_RB_PHC_TYPE = 0x0000C080
MQNIC_RB_PHC_VER = 0x00000100
MQNIC_RB_PHC_REG_CTRL = 0x0C

1
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -54,6 +54,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v

1
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -505,6 +505,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "cpl_write.v"),
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),

1
fpga/common/tb/mqnic_core_pcie_ptile/Makefile
View File

@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v

1
fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
View File

@ -706,6 +706,7 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "cpl_write.v"),
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),

1
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v

1
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -654,6 +654,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "cpl_write.v"),
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),

1
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v

1
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -728,6 +728,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "cpl_write.v"),
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),

1
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v

1
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -781,6 +781,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "cpl_write.v"),
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),

2
fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -112,6 +113,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

1
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -634,6 +634,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -693,6 +693,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -114,6 +115,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -116,6 +117,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -634,6 +634,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -132,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -132,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -133,6 +134,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -693,6 +693,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -119,6 +120,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

1
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -634,6 +634,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/AU200/fpga_25g/fpga/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -137,6 +138,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -137,6 +138,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -693,6 +693,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -119,6 +120,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

1
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -634,6 +634,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/AU250/fpga_25g/fpga/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -137,6 +138,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -137,6 +138,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -693,6 +693,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -117,6 +118,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
#XDC_FILES += hbm.xdc
# IP

1
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -623,6 +623,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/AU280/fpga_25g/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -682,6 +682,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -117,6 +118,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
#XDC_FILES += hbm.xdc
# IP

1
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -583,6 +583,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/AU50/fpga_25g/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -602,6 +602,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

1
fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile
View File

@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile
View File

@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -651,6 +651,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

1
fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile
View File

@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile
View File

@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile
View File

@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile
View File

@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -971,6 +971,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -657,6 +657,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
View File

@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -129,6 +130,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
# IP
IP_TCL_FILES = ip/pcie3_7x_0.tcl

1
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -580,6 +580,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -568,6 +568,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -697,6 +697,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

2
fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

2
fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -597,6 +597,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

1
fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile
View File

@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile
View File

@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

1
fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -764,6 +764,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),

1
fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile
View File

@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile
View File

@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile
View File

@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile
View File

@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v

1
fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile
View File

@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v

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