diff --git a/docs/source/rb/index.rst b/docs/source/rb/index.rst index 9871c2581..3b2103615 100644 --- a/docs/source/rb/index.rst +++ b/docs/source/rb/index.rst @@ -70,6 +70,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea 0x0000C005 0x00000200 application 0x0000C006 0x00000100 stats 0x0000C007 0x00000100 IRQ config + 0x0000C008 0x00000100 Clock info 0x0000C010 0x00000100 :ref:`rb_cqm_event` 0x0000C020 0x00000100 :ref:`rb_qm_tx` 0x0000C021 0x00000100 :ref:`rb_qm_rx` diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index f8173e80c..63c053ef3 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 51a99deae..353d442df 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -875,6 +875,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index 0445cd31c..6d040526a 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index abe750454..bd90c6b72 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -715,6 +715,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 672ce5c4a..57c81321a 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -606,6 +606,7 @@ parameter AXIS_IF_RX_USER_WIDTH = AXIS_RX_USER_WIDTH; localparam CLK_CYCLES_PER_US = (1000*CLK_PERIOD_NS_DENOM)/CLK_PERIOD_NS_NUM; localparam PHC_RB_BASE_ADDR = 32'h100; +localparam CLK_RB_BASE_ADDR = PHC_RB_BASE_ADDR + 32'h100; // check configuration initial begin @@ -743,17 +744,23 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ptp_ctrl_reg_rd_data; wire ptp_ctrl_reg_rd_wait; wire ptp_ctrl_reg_rd_ack; +wire clk_ctrl_reg_wr_wait; +wire clk_ctrl_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] clk_ctrl_reg_rd_data; +wire clk_ctrl_reg_rd_wait; +wire clk_ctrl_reg_rd_ack; + reg ctrl_reg_wr_ack_reg = 1'b0; reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; reg ctrl_reg_rd_ack_reg = 1'b0; reg [15:0] irq_rate_limit_min_interval_reg = 10; -assign ctrl_reg_wr_wait_int = ctrl_reg_wr_wait | ptp_ctrl_reg_wr_wait; -assign ctrl_reg_wr_ack_int = ctrl_reg_wr_ack | ctrl_reg_wr_ack_reg | ptp_ctrl_reg_wr_ack; -assign ctrl_reg_rd_data_int = ctrl_reg_rd_data | ctrl_reg_rd_data_reg | ptp_ctrl_reg_rd_data; -assign ctrl_reg_rd_wait_int = ctrl_reg_rd_wait | ptp_ctrl_reg_rd_wait; -assign ctrl_reg_rd_ack_int = ctrl_reg_rd_ack | ctrl_reg_rd_ack_reg | ptp_ctrl_reg_rd_ack; +assign ctrl_reg_wr_wait_int = ctrl_reg_wr_wait | ptp_ctrl_reg_wr_wait | clk_ctrl_reg_wr_wait; +assign ctrl_reg_wr_ack_int = ctrl_reg_wr_ack | ctrl_reg_wr_ack_reg | ptp_ctrl_reg_wr_ack | clk_ctrl_reg_wr_ack; +assign ctrl_reg_rd_data_int = ctrl_reg_rd_data | ctrl_reg_rd_data_reg | ptp_ctrl_reg_rd_data | clk_ctrl_reg_rd_data; +assign ctrl_reg_rd_wait_int = ctrl_reg_rd_wait | ptp_ctrl_reg_rd_wait | clk_ctrl_reg_rd_wait; +assign ctrl_reg_rd_ack_int = ctrl_reg_rd_ack | ctrl_reg_rd_ack_reg | ptp_ctrl_reg_rd_ack | clk_ctrl_reg_rd_ack; always @(posedge clk) begin ctrl_reg_wr_ack_reg <= 1'b0; @@ -836,7 +843,7 @@ mqnic_ptp #( .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .RB_BASE_ADDR(PHC_RB_BASE_ADDR), - .RB_NEXT_PTR(RB_NEXT_PTR) + .RB_NEXT_PTR(CLK_RB_BASE_ADDR) ) mqnic_ptp_inst ( .clk(clk), @@ -875,6 +882,50 @@ mqnic_ptp_inst ( .ptp_perout_pulse(ptp_perout_pulse) ); +localparam CLK_CNT = PORT_COUNT*2; + +wire [CLK_CNT-1:0] all_clocks; + +mqnic_rb_clk_info #( + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + .REF_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .REF_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .CH_CNT(PORT_COUNT*2), + .REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(CLK_RB_BASE_ADDR), + .RB_NEXT_PTR(RB_NEXT_PTR) +) +mqnic_rb_clk_info_inst ( + .clk(clk), + .rst(rst), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(clk_ctrl_reg_wr_wait), + .reg_wr_ack(clk_ctrl_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(clk_ctrl_reg_rd_data), + .reg_rd_wait(clk_ctrl_reg_rd_wait), + .reg_rd_ack(clk_ctrl_reg_rd_ack), + + /* + * Clock inputs + */ + .ref_clk(ptp_clk), + .ref_rst(ptp_rst), + + .ch_clk(all_clocks) +); + localparam CTRL_XBAR_MAIN_OFFSET = 0; localparam CTRL_XBAR_APP_OFFSET = CTRL_XBAR_MAIN_OFFSET + 1; localparam CTRL_XBAR_S_COUNT = CTRL_XBAR_APP_OFFSET + (APP_ENABLE && APP_CTRL_ENABLE ? 1 : 0); @@ -2996,6 +3047,9 @@ generate assign app_direct_rx_clk[n*PORTS_PER_IF+m] = port_rx_clk; assign app_direct_rx_rst[n*PORTS_PER_IF+m] = port_rx_rst; + assign all_clocks[(n*PORTS_PER_IF+m)*2+0] = port_tx_clk; + assign all_clocks[(n*PORTS_PER_IF+m)*2+1] = port_rx_clk; + wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_96; wire port_rx_ptp_ts_step; diff --git a/fpga/common/rtl/mqnic_rb_clk_info.v b/fpga/common/rtl/mqnic_rb_clk_info.v new file mode 100644 index 000000000..3a42609d7 --- /dev/null +++ b/fpga/common/rtl/mqnic_rb_clk_info.v @@ -0,0 +1,273 @@ +/* + +Copyright 2022, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Clock info register block + */ +module mqnic_rb_clk_info # +( + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + parameter REF_CLK_PERIOD_NS_NUM = 32, + parameter REF_CLK_PERIOD_NS_DENOM = 5, + parameter CH_CNT = 2, + parameter REG_ADDR_WIDTH = 16, + parameter REG_DATA_WIDTH = 32, + parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8), + parameter RB_TYPE = 32'h0000C008, + parameter RB_BASE_ADDR = 0, + parameter RB_NEXT_PTR = 0 +) +( + input wire clk, + input wire rst, + + /* + * Register interface + */ + input wire [REG_ADDR_WIDTH-1:0] reg_wr_addr, + input wire [REG_DATA_WIDTH-1:0] reg_wr_data, + input wire [REG_STRB_WIDTH-1:0] reg_wr_strb, + input wire reg_wr_en, + output wire reg_wr_wait, + output wire reg_wr_ack, + input wire [REG_ADDR_WIDTH-1:0] reg_rd_addr, + input wire reg_rd_en, + output wire [REG_DATA_WIDTH-1:0] reg_rd_data, + output wire reg_rd_wait, + output wire reg_rd_ack, + + /* + * Clock inputs + */ + input wire ref_clk, + input wire ref_rst, + + input wire [CH_CNT-1:0] ch_clk +); + +localparam SHIFT = 8; +localparam RESOLUTION = 30; + +localparam REF_CLK_CYCLES_PER_SEC = (64'd1_000_000_000*REF_CLK_PERIOD_NS_DENOM)/REF_CLK_PERIOD_NS_NUM; +localparam REF_CNT_WIDTH = $clog2(REF_CLK_CYCLES_PER_SEC >> SHIFT); + +localparam CH_PRESCALE_WIDTH = 3; +localparam CNT_WIDTH = RESOLUTION-SHIFT; +localparam CH_CNT_WIDTH = CNT_WIDTH-CH_PRESCALE_WIDTH; + +localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}}; + +// check configuration +initial begin + if (REG_DATA_WIDTH != 32) begin + $error("Error: Register interface width must be 32 (instance %m)"); + $finish; + end + + if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin + $error("Error: Register interface requires byte (8-bit) granularity (instance %m)"); + $finish; + end + + if (REG_ADDR_WIDTH < 5) begin + $error("Error: Register address width too narrow (instance %m)"); + $finish; + end + + if (REG_ADDR_WIDTH < $clog2(32 + CH_CNT*4)) begin + $error("Error: Register address width too narrow (instance %m)"); + $finish; + end + + if (RB_NEXT_PTR && RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 32 + CH_CNT*4) begin + $error("Error: RB_NEXT_PTR overlaps block (instance %m)"); + $finish; + end +end + +// generate periodic strobe from ref clock for measurement period +reg [REF_CNT_WIDTH-1:0] ref_cnt_reg = 0; +reg ref_strb_reg = 0; + +always @(posedge ref_clk) begin + if (ref_cnt_reg) begin + ref_cnt_reg <= ref_cnt_reg - 1; + end else begin + ref_cnt_reg <= (REF_CLK_CYCLES_PER_SEC >> SHIFT) - 1; + ref_strb_reg <= !ref_strb_reg; + end + + if (ref_rst) begin + ref_cnt_reg <= 0; + ref_strb_reg <= 0; + end +end + +reg ref_strb_sync_1_reg = 0; +reg ref_strb_sync_2_reg = 0; +reg ref_strb_sync_3_reg = 0; + +always @(posedge clk) begin + ref_strb_sync_1_reg <= ref_strb_reg; + ref_strb_sync_2_reg <= ref_strb_sync_1_reg; + ref_strb_sync_3_reg <= ref_strb_sync_2_reg; +end + +// divide and sync each input clock +wire [CH_CNT-1:0] ch_flag; + +generate + +genvar ch; + +for (ch = 0; ch < CH_CNT; ch = ch + 1) begin : channel + + reg [CH_PRESCALE_WIDTH+1-1:0] ch_prescale_reg = 0; + + always @(posedge ch_clk[ch]) begin + ch_prescale_reg <= ch_prescale_reg + 1; + end + + reg ch_flag_sync_1_reg = 0; + reg ch_flag_sync_2_reg = 0; + reg ch_flag_sync_3_reg = 0; + + always @(posedge clk) begin + ch_flag_sync_1_reg <= ch_prescale_reg[CH_PRESCALE_WIDTH]; + ch_flag_sync_2_reg <= ch_flag_sync_1_reg; + ch_flag_sync_3_reg <= ch_flag_sync_2_reg; + end + + assign ch_flag[ch] = ch_flag_sync_3_reg ^ ch_flag_sync_2_reg; +end + +endgenerate + +// control registers +reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0; +reg reg_rd_ack_reg = 1'b0; + +reg [CNT_WIDTH-1:0] clk_acc_reg = 0; +reg [CNT_WIDTH-1:0] clk_cnt_reg = 0; + +reg [CH_CNT_WIDTH-1:0] ch_acc_reg[0:CH_CNT-1]; +reg [CH_CNT_WIDTH-1:0] ch_cnt_reg[0:CH_CNT-1]; + +wire [CH_CNT_WIDTH-1:0] ch_acc_reg_0 = ch_acc_reg[0]; +wire [CH_CNT_WIDTH-1:0] ch_cnt_reg_0 = ch_cnt_reg[0]; + +assign reg_wr_wait = 1'b0; +assign reg_wr_ack = 1'b0; +assign reg_rd_data = reg_rd_data_reg; +assign reg_rd_wait = 1'b0; +assign reg_rd_ack = reg_rd_ack_reg; + +integer k; + +initial begin + for (k = 0; k < CH_CNT; k = k + 1) begin + ch_acc_reg[k] = 0; + ch_cnt_reg[k] = 0; + end +end + +always @(posedge clk) begin + reg_rd_data_reg <= 0; + reg_rd_ack_reg <= 1'b0; + + if (ref_strb_sync_3_reg ^ ref_strb_sync_2_reg) begin + clk_acc_reg <= 1; + clk_cnt_reg <= clk_acc_reg; + end else begin + clk_acc_reg <= clk_acc_reg + 1; + end + + for (k = 0; k < CH_CNT; k = k + 1) begin + if (ref_strb_sync_3_reg ^ ref_strb_sync_2_reg) begin + ch_acc_reg[k] <= ch_flag[k]; + ch_cnt_reg[k] <= ch_acc_reg[k]; + end else begin + ch_acc_reg[k] <= ch_acc_reg[k] + ch_flag[k]; + end + end + + if (reg_rd_en && !reg_rd_ack_reg) begin + // read operation + reg_rd_ack_reg <= 1'b1; + case ({reg_rd_addr >> 2, 2'b00}) + RBB+5'h00: reg_rd_data_reg <= RB_TYPE; // Type + RBB+5'h04: reg_rd_data_reg <= 32'h00000100; // Version + RBB+5'h08: reg_rd_data_reg <= RB_NEXT_PTR; // Next header + RBB+5'h0C: reg_rd_data_reg <= CH_CNT; + RBB+5'h10: begin + reg_rd_data_reg[31:16] <= REF_CLK_PERIOD_NS_NUM; + reg_rd_data_reg[15:0] <= REF_CLK_PERIOD_NS_DENOM; + end + RBB+5'h18: begin + reg_rd_data_reg[31:16] <= CLK_PERIOD_NS_NUM; + reg_rd_data_reg[15:0] <= CLK_PERIOD_NS_DENOM; + end + RBB+5'h1C: reg_rd_data_reg <= clk_cnt_reg << SHIFT; + default: reg_rd_ack_reg <= 1'b0; + endcase + for (k = 0; k < CH_CNT; k = k + 1) begin + if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h20 + k*4) begin + reg_rd_data_reg <= ch_cnt_reg[k] << (SHIFT+CH_PRESCALE_WIDTH); + reg_rd_ack_reg <= 1'b1; + end + end + end + + if (rst) begin + reg_rd_ack_reg <= 1'b0; + + clk_acc_reg <= 0; + clk_cnt_reg <= 0; + + for (k = 0; k < CH_CNT; k = k + 1) begin + ch_acc_reg[k] <= 0; + ch_cnt_reg[k] <= 0; + end + end +end + +endmodule + +`resetall diff --git a/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl b/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl new file mode 100644 index 000000000..860166973 --- /dev/null +++ b/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl @@ -0,0 +1,44 @@ +# Copyright 2022, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +# PTP clock timing constraints + +foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_rb_clk_info || REF_NAME == mqnic_rb_clk_info)}] { + puts "Inserting timing constraints for mqnic_rb_clk_info instance $inst" + + set clk [get_clocks -of_objects [get_pins "$inst/ref_strb_sync_1_reg_reg/C"]] + + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/ref_strb_sync_\[123\]_reg_reg" -filter "PARENT == $inst"] + + set_max_delay -from [get_cells "$inst/ref_strb_reg_reg"] -to [get_cells "$inst/ref_strb_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $clk] + + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/channel\\\[\\d+\\\]\\.ch_flag_sync_\[123\]_reg_reg" -filter "PARENT == $inst"] + + set_max_delay -from [get_cells "$inst/channel[*].ch_prescale_reg_reg[*]"] -to [get_cells "$inst/channel[*].ch_flag_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $clk] +} diff --git a/fpga/common/tb/mqnic.py b/fpga/common/tb/mqnic.py index 20906a4ee..06e129a82 100644 --- a/fpga/common/tb/mqnic.py +++ b/fpga/common/tb/mqnic.py @@ -98,13 +98,24 @@ MQNIC_RB_GECKO_BMC_REG_STATUS = 0x0C MQNIC_RB_GECKO_BMC_REG_DATA = 0x10 MQNIC_RB_GECKO_BMC_REG_CMD = 0x14 -MQNIC_RB_STATS_TYPE = 0x0000C004 +MQNIC_RB_STATS_TYPE = 0x0000C006 MQNIC_RB_STATS_VER = 0x00000100 MQNIC_RB_STATS_REG_OFFSET = 0x0C MQNIC_RB_STATS_REG_COUNT = 0x10 MQNIC_RB_STATS_REG_STRIDE = 0x14 MQNIC_RB_STATS_REG_FLAGS = 0x18 +MQNIC_RB_IRQ_TYPE = 0x0000C007 +MQNIC_RB_IRQ_VER = 0x00000100 + +MQNIC_RB_CLK_INFO_TYPE = 0x0000C008 +MQNIC_RB_CLK_INFO_VER = 0x00000100 +MQNIC_RB_CLK_INFO_COUNT = 0x0C +MQNIC_RB_CLK_INFO_REF_NOM_PER = 0x10 +MQNIC_RB_CLK_INFO_CLK_NOM_PER = 0x18 +MQNIC_RB_CLK_INFO_CLK_FREQ = 0x1C +MQNIC_RB_CLK_INFO_FREQ_BASE = 0x20 + MQNIC_RB_PHC_TYPE = 0x0000C080 MQNIC_RB_PHC_VER = 0x00000100 MQNIC_RB_PHC_REG_CTRL = 0x0C diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index 9b69f09b3..d2339b66f 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -54,6 +54,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index 07aa9a25b..ef28c9c5e 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -505,6 +505,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "cpl_write.v"), os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index 3b8998301..d26d489c9 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index 61536b73e..8f5531c7f 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -706,6 +706,7 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "cpl_write.v"), os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index 1fc748a49..39d464502 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 7a470199b..0016641bf 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -654,6 +654,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "cpl_write.v"), os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index 27ea6bc26..c65b5ab9a 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 65775fe6f..bef075160 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -728,6 +728,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "cpl_write.v"), os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 04b6c3242..3804c5925 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index 3f7b731d9..a89b7686a 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -781,6 +781,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "cpl_write.v"), os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile index a76cb3203..d291214c8 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -112,6 +113,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index a8dfe24f5..254aaedbd 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index 037b4f576..4853dde6b 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -634,6 +634,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile index 1ee054be4..f3394d995 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile index 1ee054be4..f3394d995 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index a0ffd1336..cfc21ded4 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index ad2b493d3..d88538154 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -693,6 +693,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index c3539c713..9cad98094 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -114,6 +115,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index 8e0f098f0..d6cc7cd50 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -116,6 +117,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index f96fe70a7..34f5579a5 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 6725a712a..37ee05351 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -634,6 +634,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 693de57bd..cc62e1d3d 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -132,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index 693de57bd..cc62e1d3d 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -132,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index 71688a663..d3d9872dc 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -133,6 +134,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index e0b07f00e..5bfd7a553 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index e71f94c17..5675ff8d0 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -693,6 +693,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile index 01013779a..9fab10a0e 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -119,6 +120,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index f1c6022b6..4ceaac3b2 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index 074e659f5..252565267 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -634,6 +634,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile index 6b4f2d6bc..c0b0018c6 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -137,6 +138,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile index 6b4f2d6bc..c0b0018c6 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -137,6 +138,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index 37f6900d3..4734121a5 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index ef4c2e213..437095302 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -693,6 +693,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile index a41aa1e8c..9ede9db30 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -119,6 +120,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index f1c6022b6..4ceaac3b2 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index 074e659f5..252565267 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -634,6 +634,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile index c1d2add7c..75b2b1d2f 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -137,6 +138,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile index c1d2add7c..75b2b1d2f 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -137,6 +138,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile index 37f6900d3..4734121a5 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py index ef4c2e213..437095302 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -693,6 +693,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index 6b880159a..dcdde2218 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -117,6 +118,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl #XDC_FILES += hbm.xdc # IP diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index 8066b891c..66aa216fa 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 2a89b165d..f852c23a7 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -623,6 +623,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile index 305f927e7..ce306c385 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile index 305f927e7..ce306c385 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index 78631f7d6..3ba121f26 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index 29a583be4..00d25ce0c 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -682,6 +682,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index 24a9adeb9..9d584bb24 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -117,6 +118,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl #XDC_FILES += hbm.xdc # IP diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index 90a1f3610..bce526dc8 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 27fff88a1..b3babcd8d 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -583,6 +583,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile index 662f2c21b..3c5855964 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile index 662f2c21b..3c5855964 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index b41d0ca2c..67907d460 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index 7be96b239..c7829345c 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -602,6 +602,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile index ba8289561..7d54b8fb1 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile @@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile index 9b313537f..997065290 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile @@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile index 88215e5d7..1f7e7bdea 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index fd7af1468..7c4f6db1c 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -651,6 +651,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile index a0edcc3e5..c24e68949 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile @@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile index 28599dca5..3bc7ecfa4 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile @@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile index 21eb694c2..be92658bd 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile @@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile index fd0a2cd69..90d245e2d 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile @@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile index 9a03877da..c2a2c1557 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py index 68f020a91..c5b3ce6c7 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -971,6 +971,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile index aecd5d989..1d2914bc9 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile index 6a21a643e..1980895cc 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index d9129336c..e0ba045f4 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index a1f1e03c5..baa53f2bb 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -657,6 +657,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile index 066014375..781252c90 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile @@ -28,6 +28,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -129,6 +130,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie3_7x_0.tcl diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 4569f31e6..061516500 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index 6dc4e5503..f9777f6e5 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -580,6 +580,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile index 9b99b7915..49bc49698 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile index ddb85a2ba..cecb76fb7 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py index e530d069f..880810710 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py @@ -568,6 +568,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile index 36e3a5f33..e0afd9fb9 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile index 36e3a5f33..e0afd9fb9 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index 5f0553eb0..c0d6b2155 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index 2ca99b725..73ec53ddd 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -697,6 +697,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile index b9fefc250..dbd6a9b8d 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile index b9fefc250..dbd6a9b8d 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index 5f0553eb0..c0d6b2155 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index 0abf22bfa..ce16b992e 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -597,6 +597,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile index 837b14b37..36b77fb95 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile index f08135788..b78c11ee9 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile index 0ebe5abe4..81716d400 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index c5b002b5c..0b0b46480 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -764,6 +764,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile index ef889575e..3f8adf3c1 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile index 1f136390a..c848d5ba4 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile index 07f8877fe..ab06d1f4a 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile index 1f592b89a..265716c6a 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile index c163e829c..8b8a91dd0 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index 4c3742c5c..c8ed9ee56 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -603,6 +603,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile index 808d84187..dc4a597de 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -132,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile index 808d84187..dc4a597de 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -132,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index eb5536546..0f2629fef 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index eb00c5e94..e13433147 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -589,6 +589,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index a3cd7bcba..0a1ccb16e 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -114,6 +115,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index 198bc81ff..6ee5fe7e1 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index 7f518110a..0159a7f90 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -638,6 +638,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile index e500c5b9b..980d43781 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -132,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile index e500c5b9b..980d43781 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -132,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index c42c2988c..12d0a2cc6 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index d38424f48..bf19f1ac6 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -697,6 +697,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile index 61af50895..0fa3b8e90 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -115,6 +116,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index f1c6022b6..4ceaac3b2 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index 45ed8e263..1bbe6902e 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -632,6 +632,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile index 672d62335..8e4c7a88d 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -133,6 +134,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile index 672d62335..8e4c7a88d 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -133,6 +134,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile index 37f6900d3..4734121a5 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py index 17e001c9a..00546abf0 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -691,6 +691,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile index 4a93efe05..5a4b28bf7 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -113,6 +114,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index 3307fdebc..513c29170 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index 8deec841e..142e1f077 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -702,6 +702,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile index a7880a465..0a12528b3 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -131,6 +132,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile index a7880a465..0a12528b3 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile @@ -25,6 +25,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -131,6 +132,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index aa6509b11..10997ff9f 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index 1ee685c63..a6109698f 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -841,6 +841,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile index f9a8b5317..b78410ace 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile @@ -24,6 +24,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -112,6 +113,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index b9d70d285..bbd5f083d 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 83b4b888c..8ce9e128f 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -397,6 +397,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index 6fa3066dc..365221d55 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -130,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index d11eebec4..3cd71ebd4 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -56,6 +56,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index eb0bb237b..c559ff6bd 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -591,6 +591,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile index cac5116dc..312d205b3 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile @@ -24,6 +24,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -112,6 +113,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index b9d70d285..bbd5f083d 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -55,6 +55,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index a35731c33..9c3c61c61 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -367,6 +367,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index 9dc690a4b..cf2beafed 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -116,6 +117,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile index c8f5154c0..f57122835 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -117,6 +118,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile index f39bba904..924f335d0 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -120,6 +121,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index b767dfc0d..a42823209 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -118,6 +119,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index ee9268101..b296591ff 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -57,6 +57,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index 0ef756d02..5b5eace46 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -639,6 +639,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index 6b51347d1..a2e7f63ac 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -134,6 +135,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile index 6b51347d1..a2e7f63ac 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -134,6 +135,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index f950737d2..b03cfd59d 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -27,6 +27,7 @@ SYN_FILES += rtl/common/mqnic_rx_queue_map.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v @@ -135,6 +136,7 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index b58f2cd6b..2d136464a 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -57,6 +57,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 6ea1636fd..eebfe6dc9 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -696,6 +696,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), os.path.join(rtl_dir, "common", "cpl_write.v"), os.path.join(rtl_dir, "common", "cpl_op_mux.v"), diff --git a/lib/mqnic/mqnic.c b/lib/mqnic/mqnic.c index da75575d9..ccedf5956 100644 --- a/lib/mqnic/mqnic.c +++ b/lib/mqnic/mqnic.c @@ -421,6 +421,23 @@ open: } dev->phc_rb = mqnic_find_reg_block(dev->rb_list, MQNIC_RB_PHC_TYPE, MQNIC_RB_PHC_VER, 0); + dev->clk_info_rb = mqnic_find_reg_block(dev->rb_list, MQNIC_RB_CLK_INFO_TYPE, MQNIC_RB_CLK_INFO_VER, 0); + + if (dev->clk_info_rb) { + uint32_t val = mqnic_reg_read32(dev->clk_info_rb->regs, MQNIC_RB_CLK_INFO_REF_NOM_PER); + + dev->ref_clk_nom_per_ns_num = val >> 16; + dev->ref_clk_nom_per_ns_denom = val & 0xffff; + dev->ref_clk_nom_freq_hz = (dev->ref_clk_nom_per_ns_denom * 1000000000ull) / dev->ref_clk_nom_per_ns_num; + + val = mqnic_reg_read32(dev->clk_info_rb->regs, MQNIC_RB_CLK_INFO_CLK_NOM_PER); + + dev->core_clk_nom_per_ns_num = val >> 16; + dev->core_clk_nom_per_ns_denom = val & 0xffff; + dev->core_clk_nom_freq_hz = (dev->core_clk_nom_per_ns_denom * 1000000000ull) / dev->core_clk_nom_per_ns_num; + + dev->clk_info_channels = mqnic_reg_read32(dev->clk_info_rb->regs, MQNIC_RB_CLK_INFO_COUNT); + } // Enumerate interfaces dev->if_rb = mqnic_find_reg_block(dev->rb_list, MQNIC_RB_IF_TYPE, MQNIC_RB_IF_VER, 0); @@ -513,3 +530,27 @@ void mqnic_print_fw_id(struct mqnic *dev) if (dev->app_id) printf("Application ID: 0x%08x\n", dev->app_id); } + +uint32_t mqnic_get_core_clk_nom_freq_hz(struct mqnic *dev) +{ + return dev->core_clk_nom_freq_hz; +} + +uint32_t mqnic_get_ref_clk_nom_freq_hz(struct mqnic *dev) +{ + return dev->ref_clk_nom_freq_hz; +} + +uint32_t mqnic_get_core_clk_freq_hz(struct mqnic *dev) +{ + if (!dev->clk_info_rb) + return 0; + return mqnic_reg_read32(dev->clk_info_rb->regs, MQNIC_RB_CLK_INFO_CLK_FREQ); +} + +uint32_t mqnic_get_clk_freq_hz(struct mqnic *dev, int ch) +{ + if (!dev->clk_info_rb || ch < 0 || ch >= dev->clk_info_channels) + return 0; + return mqnic_reg_read32(dev->clk_info_rb->regs, MQNIC_RB_CLK_INFO_FREQ_BASE + ch*4); +} diff --git a/lib/mqnic/mqnic.h b/lib/mqnic/mqnic.h index f61768740..27a3aee11 100644 --- a/lib/mqnic/mqnic.h +++ b/lib/mqnic/mqnic.h @@ -152,6 +152,7 @@ struct mqnic { struct mqnic_reg_block *fw_id_rb; struct mqnic_reg_block *if_rb; struct mqnic_reg_block *phc_rb; + struct mqnic_reg_block *clk_info_rb; uint32_t fpga_id; const char *fpga_part; @@ -165,6 +166,14 @@ struct mqnic { uint32_t app_id; + uint16_t core_clk_nom_per_ns_num; + uint16_t core_clk_nom_per_ns_denom; + uint32_t core_clk_nom_freq_hz; + uint16_t ref_clk_nom_per_ns_num; + uint16_t ref_clk_nom_per_ns_denom; + uint32_t ref_clk_nom_freq_hz; + uint32_t clk_info_channels; + uint32_t if_offset; uint32_t if_count; uint32_t if_stride; @@ -182,6 +191,10 @@ struct mqnic { struct mqnic *mqnic_open(const char *dev_name); void mqnic_close(struct mqnic *dev); void mqnic_print_fw_id(struct mqnic *dev); +uint32_t mqnic_get_core_clk_nom_freq_hz(struct mqnic *dev); +uint32_t mqnic_get_ref_clk_nom_freq_hz(struct mqnic *dev); +uint32_t mqnic_get_core_clk_freq_hz(struct mqnic *dev); +uint32_t mqnic_get_clk_freq_hz(struct mqnic *dev, int ch); // mqnic_if.c struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *regs); diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h index 82130829b..84e573af4 100644 --- a/modules/mqnic/mqnic_hw.h +++ b/modules/mqnic/mqnic_hw.h @@ -127,13 +127,24 @@ #define MQNIC_RB_GECKO_BMC_REG_DATA 0x10 #define MQNIC_RB_GECKO_BMC_REG_CMD 0x14 -#define MQNIC_RB_STATS_TYPE 0x0000C004 +#define MQNIC_RB_STATS_TYPE 0x0000C006 #define MQNIC_RB_STATS_VER 0x00000100 #define MQNIC_RB_STATS_REG_OFFSET 0x0C #define MQNIC_RB_STATS_REG_COUNT 0x10 #define MQNIC_RB_STATS_REG_STRIDE 0x14 #define MQNIC_RB_STATS_REG_FLAGS 0x18 +#define MQNIC_RB_IRQ_TYPE 0x0000C007 +#define MQNIC_RB_IRQ_VER 0x00000100 + +#define MQNIC_RB_CLK_INFO_TYPE 0x0000C008 +#define MQNIC_RB_CLK_INFO_VER 0x00000100 +#define MQNIC_RB_CLK_INFO_COUNT 0x0C +#define MQNIC_RB_CLK_INFO_REF_NOM_PER 0x10 +#define MQNIC_RB_CLK_INFO_CLK_NOM_PER 0x18 +#define MQNIC_RB_CLK_INFO_CLK_FREQ 0x1C +#define MQNIC_RB_CLK_INFO_FREQ_BASE 0x20 + #define MQNIC_RB_PHC_TYPE 0x0000C080 #define MQNIC_RB_PHC_VER 0x00000100 #define MQNIC_RB_PHC_REG_CTRL 0x0C diff --git a/utils/mqnic-dump.c b/utils/mqnic-dump.c index 91500fd5d..d19d56a77 100644 --- a/utils/mqnic-dump.c +++ b/utils/mqnic-dump.c @@ -163,6 +163,63 @@ int main(int argc, char *argv[]) } } + if (dev->clk_info_rb) + { + uint32_t num; + uint32_t denom; + uint32_t ns; + uint32_t fns; + uint32_t mhz; + uint32_t hz; + + num = dev->ref_clk_nom_per_ns_num; + denom = dev->ref_clk_nom_per_ns_denom; + + ns = num/denom; + fns = ((num-ns*denom)*1000000000ull)/denom; + + printf("Ref clock nominal period: %d.%09d ns (raw %d/%d ns)\n", ns, fns, num, denom); + + hz = mqnic_get_ref_clk_nom_freq_hz(dev); + + mhz = hz / 1000000; + hz = hz - (mhz * 1000000); + + printf("Ref clock nominal freq: %d.%06d MHz\n", mhz, hz); + + num = dev->core_clk_nom_per_ns_num; + denom = dev->core_clk_nom_per_ns_denom; + + ns = num/denom; + fns = ((num-ns*denom)*1000000000ull)/denom; + + printf("Core clock nominal period: %d.%09d ns (raw %d/%d ns)\n", ns, fns, num, denom); + + hz = mqnic_get_core_clk_nom_freq_hz(dev); + + mhz = hz / 1000000; + hz = hz - (mhz * 1000000); + + printf("Core clock nominal freq: %d.%06d MHz\n", mhz, hz); + + hz = mqnic_get_core_clk_freq_hz(dev); + + mhz = hz / 1000000; + hz = hz - (mhz * 1000000); + + printf("Core clock freq: %d.%06d MHz\n", mhz, hz); + + for (int ch = 0; ch < dev->clk_info_channels; ch++) + { + hz = mqnic_get_clk_freq_hz(dev, ch); + + mhz = hz / 1000000; + hz = hz - (mhz * 1000000); + + printf("CH%d: clock freq: %d.%06d MHz\n", ch, mhz, hz); + } + } + if (interface < 0 || interface >= dev->if_count) { fprintf(stderr, "Interface out of range\n");