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Add statistics collection for AXI DMA IF

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-04-23 13:12:50 -07:00
parent 2bd8350276
commit d5c2566dff
10 changed files with 553 additions and 11 deletions
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213
fpga/common/rtl/mqnic_core_axi.v
View File

@ -442,6 +442,35 @@ wire dma_write_desc_status_valid;
wire dma_enable = 1;
wire [$clog2(AXI_DMA_READ_OP_TABLE_SIZE)-1:0] stat_rd_op_start_tag;
wire [DMA_LEN_WIDTH-1:0] stat_rd_op_start_len;
wire stat_rd_op_start_valid;
wire [$clog2(AXI_DMA_READ_OP_TABLE_SIZE)-1:0] stat_rd_op_finish_tag;
wire [3:0] stat_rd_op_finish_status;
wire stat_rd_op_finish_valid;
wire [$clog2(AXI_DMA_READ_OP_TABLE_SIZE)-1:0] stat_rd_req_start_tag;
wire [12:0] stat_rd_req_start_len;
wire stat_rd_req_start_valid;
wire [$clog2(AXI_DMA_READ_OP_TABLE_SIZE)-1:0] stat_rd_req_finish_tag;
wire [3:0] stat_rd_req_finish_status;
wire stat_rd_req_finish_valid;
wire stat_rd_op_table_full;
wire stat_rd_tx_stall;
wire [$clog2(AXI_DMA_WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_start_tag;
wire [DMA_LEN_WIDTH-1:0] stat_wr_op_start_len;
wire stat_wr_op_start_valid;
wire [$clog2(AXI_DMA_WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_finish_tag;
wire [3:0] stat_wr_op_finish_status;
wire stat_wr_op_finish_valid;
wire [$clog2(AXI_DMA_WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_start_tag;
wire [12:0] stat_wr_req_start_len;
wire stat_wr_req_start_valid;
wire [$clog2(AXI_DMA_WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_finish_tag;
wire [3:0] stat_wr_req_finish_status;
wire stat_wr_req_finish_valid;
wire stat_wr_op_table_full;
wire stat_wr_tx_stall;
dma_if_axi #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
@ -566,9 +595,183 @@ dma_if_axi_inst (
* Configuration
*/
.read_enable(dma_enable),
.write_enable(dma_enable)
.write_enable(dma_enable),
/*
* Statistics
*/
.stat_rd_op_start_tag(stat_rd_op_start_tag),
.stat_rd_op_start_len(stat_rd_op_start_len),
.stat_rd_op_start_valid(stat_rd_op_start_valid),
.stat_rd_op_finish_tag(stat_rd_op_finish_tag),
.stat_rd_op_finish_status(stat_rd_op_finish_status),
.stat_rd_op_finish_valid(stat_rd_op_finish_valid),
.stat_rd_req_start_tag(stat_rd_req_start_tag),
.stat_rd_req_start_len(stat_rd_req_start_len),
.stat_rd_req_start_valid(stat_rd_req_start_valid),
.stat_rd_req_finish_tag(stat_rd_req_finish_tag),
.stat_rd_req_finish_status(stat_rd_req_finish_status),
.stat_rd_req_finish_valid(stat_rd_req_finish_valid),
.stat_rd_op_table_full(stat_rd_op_table_full),
.stat_rd_tx_stall(stat_rd_tx_stall),
.stat_wr_op_start_tag(stat_wr_op_start_tag),
.stat_wr_op_start_len(stat_wr_op_start_len),
.stat_wr_op_start_valid(stat_wr_op_start_valid),
.stat_wr_op_finish_tag(stat_wr_op_finish_tag),
.stat_wr_op_finish_status(stat_wr_op_finish_status),
.stat_wr_op_finish_valid(stat_wr_op_finish_valid),
.stat_wr_req_start_tag(stat_wr_req_start_tag),
.stat_wr_req_start_len(stat_wr_req_start_len),
.stat_wr_req_start_valid(stat_wr_req_start_valid),
.stat_wr_req_finish_tag(stat_wr_req_finish_tag),
.stat_wr_req_finish_status(stat_wr_req_finish_status),
.stat_wr_req_finish_valid(stat_wr_req_finish_valid),
.stat_wr_op_table_full(stat_wr_op_table_full),
.stat_wr_tx_stall(stat_wr_tx_stall)
);
wire [STAT_INC_WIDTH-1:0] axis_stat_tdata;
wire [STAT_ID_WIDTH-1:0] axis_stat_tid;
wire axis_stat_tvalid;
wire axis_stat_tready;
wire [STAT_INC_WIDTH-1:0] axis_stat_axi_tdata = 0;
wire [STAT_ID_WIDTH-1:0] axis_stat_axi_tid = 0;
wire axis_stat_axi_tvalid = 0;
wire axis_stat_axi_tready;
wire [STAT_INC_WIDTH-1:0] axis_stat_dma_tdata;
wire [STAT_ID_WIDTH-1:0] axis_stat_dma_tid;
wire axis_stat_dma_tvalid;
wire axis_stat_dma_tready;
generate
if (STAT_ENABLE && STAT_DMA_ENABLE) begin : stats_dma_if_axi
stats_dma_if_axi #(
.LEN_WIDTH(DMA_LEN_WIDTH),
.READ_OP_TABLE_SIZE(AXI_DMA_READ_OP_TABLE_SIZE),
.WRITE_OP_TABLE_SIZE(AXI_DMA_WRITE_OP_TABLE_SIZE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(5),
.UPDATE_PERIOD(1024)
)
stats_dma_if_axi_inst (
.clk(clk),
.rst(rst),
/*
* Statistics from dma_if_axi
*/
.stat_rd_op_start_tag(stat_rd_op_start_tag),
.stat_rd_op_start_len(stat_rd_op_start_len),
.stat_rd_op_start_valid(stat_rd_op_start_valid),
.stat_rd_op_finish_tag(stat_rd_op_finish_tag),
.stat_rd_op_finish_status(stat_rd_op_finish_status),
.stat_rd_op_finish_valid(stat_rd_op_finish_valid),
.stat_rd_req_start_tag(stat_rd_req_start_tag),
.stat_rd_req_start_len(stat_rd_req_start_len),
.stat_rd_req_start_valid(stat_rd_req_start_valid),
.stat_rd_req_finish_tag(stat_rd_req_finish_tag),
.stat_rd_req_finish_status(stat_rd_req_finish_status),
.stat_rd_req_finish_valid(stat_rd_req_finish_valid),
.stat_rd_op_table_full(stat_rd_op_table_full),
.stat_rd_tx_stall(stat_rd_tx_stall),
.stat_wr_op_start_tag(stat_wr_op_start_tag),
.stat_wr_op_start_len(stat_wr_op_start_len),
.stat_wr_op_start_valid(stat_wr_op_start_valid),
.stat_wr_op_finish_tag(stat_wr_op_finish_tag),
.stat_wr_op_finish_status(stat_wr_op_finish_status),
.stat_wr_op_finish_valid(stat_wr_op_finish_valid),
.stat_wr_req_start_tag(stat_wr_req_start_tag),
.stat_wr_req_start_len(stat_wr_req_start_len),
.stat_wr_req_start_valid(stat_wr_req_start_valid),
.stat_wr_req_finish_tag(stat_wr_req_finish_tag),
.stat_wr_req_finish_status(stat_wr_req_finish_status),
.stat_wr_req_finish_valid(stat_wr_req_finish_valid),
.stat_wr_op_table_full(stat_wr_op_table_full),
.stat_wr_tx_stall(stat_wr_tx_stall),
/*
* Statistics output
*/
.m_axis_stat_tdata(axis_stat_dma_tdata),
.m_axis_stat_tid(axis_stat_dma_tid[4:0]),
.m_axis_stat_tvalid(axis_stat_dma_tvalid),
.m_axis_stat_tready(axis_stat_dma_tready),
/*
* Control inputs
*/
.update(1'b0)
);
assign axis_stat_dma_tid[STAT_ID_WIDTH-1:5] = 1;
end else begin
assign axis_stat_dma_tdata = 0;
assign axis_stat_dma_tid = 0;
assign axis_stat_dma_tvalid = 0;
end
if (STAT_ENABLE && (STAT_DMA_ENABLE || STAT_AXI_ENABLE)) begin : stats_mux
axis_arb_mux #(
.S_COUNT(3),
.DATA_WIDTH(STAT_INC_WIDTH),
.KEEP_ENABLE(0),
.ID_ENABLE(1),
.S_ID_WIDTH(STAT_ID_WIDTH),
.M_ID_WIDTH(STAT_ID_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.LAST_ENABLE(0),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_LSB_HIGH_PRIORITY(1)
)
axis_stat_mux_inst (
.clk(clk),
.rst(rst),
/*
* AXI Stream inputs
*/
.s_axis_tdata({axis_stat_dma_tdata, axis_stat_axi_tdata, s_axis_stat_tdata}),
.s_axis_tkeep(0),
.s_axis_tvalid({axis_stat_dma_tvalid, axis_stat_axi_tvalid, s_axis_stat_tvalid}),
.s_axis_tready({axis_stat_dma_tready, axis_stat_axi_tready, s_axis_stat_tready}),
.s_axis_tlast(0),
.s_axis_tid({axis_stat_dma_tid, axis_stat_axi_tid, s_axis_stat_tid}),
.s_axis_tdest(0),
.s_axis_tuser(0),
/*
* AXI Stream output
*/
.m_axis_tdata(axis_stat_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(axis_stat_tvalid),
.m_axis_tready(axis_stat_tready),
.m_axis_tlast(),
.m_axis_tid(axis_stat_tid),
.m_axis_tdest(),
.m_axis_tuser()
);
end else begin
assign axis_stat_tdata = s_axis_stat_tdata;
assign axis_stat_tid = s_axis_stat_tid;
assign axis_stat_tvalid = s_axis_stat_tvalid;
assign s_axis_stat_tready = axis_stat_tready;
end
endgenerate
mqnic_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
@ -904,10 +1107,10 @@ core_inst (
/*
* Statistics input
*/
.s_axis_stat_tdata(s_axis_stat_tdata),
.s_axis_stat_tid(s_axis_stat_tid),
.s_axis_stat_tvalid(s_axis_stat_tvalid),
.s_axis_stat_tready(s_axis_stat_tready),
.s_axis_stat_tdata(axis_stat_tdata),
.s_axis_stat_tid(axis_stat_tid),
.s_axis_stat_tvalid(axis_stat_tvalid),
.s_axis_stat_tready(axis_stat_tready),
/*
* GPIO

324
fpga/common/rtl/stats_dma_if_axi.v Normal file
View File

@ -0,0 +1,324 @@
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Statistics for AXI DMA interface
*/
module stats_dma_if_axi #
(
// Length field width
parameter LEN_WIDTH = 16,
// Operation table size (read)
parameter READ_OP_TABLE_SIZE = 64,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 64,
// Statistics counter increment width (bits)
parameter STAT_INC_WIDTH = 24,
// Statistics counter ID width (bits)
parameter STAT_ID_WIDTH = 5,
// Statistics counter update period (cycles)
parameter UPDATE_PERIOD = 1024
)
(
input wire clk,
input wire rst,
/*
* Statistics from dma_if_axi
*/
input wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_start_tag,
input wire [LEN_WIDTH-1:0] stat_rd_op_start_len,
input wire stat_rd_op_start_valid,
input wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_finish_tag,
input wire [3:0] stat_rd_op_finish_status,
input wire stat_rd_op_finish_valid,
input wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_req_start_tag,
input wire [12:0] stat_rd_req_start_len,
input wire stat_rd_req_start_valid,
input wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_req_finish_tag,
input wire [3:0] stat_rd_req_finish_status,
input wire stat_rd_req_finish_valid,
input wire stat_rd_op_table_full,
input wire stat_rd_tx_stall,
input wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_start_tag,
input wire [LEN_WIDTH-1:0] stat_wr_op_start_len,
input wire stat_wr_op_start_valid,
input wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_finish_tag,
input wire [3:0] stat_wr_op_finish_status,
input wire stat_wr_op_finish_valid,
input wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_start_tag,
input wire [12:0] stat_wr_req_start_len,
input wire stat_wr_req_start_valid,
input wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_finish_tag,
input wire [3:0] stat_wr_req_finish_status,
input wire stat_wr_req_finish_valid,
input wire stat_wr_op_table_full,
input wire stat_wr_tx_stall,
/*
* Statistics output
*/
output wire [STAT_INC_WIDTH-1:0] m_axis_stat_tdata,
output wire [STAT_ID_WIDTH-1:0] m_axis_stat_tid,
output wire m_axis_stat_tvalid,
input wire m_axis_stat_tready,
/*
* Control inputs
*/
input wire update
);
wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_tag;
wire [LEN_WIDTH-1:0] stat_rd_op_len;
wire [3:0] stat_rd_op_status;
wire [15:0] stat_rd_op_latency;
wire stat_rd_op_valid;
wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_req_tag;
wire [12:0] stat_rd_req_len;
wire [3:0] stat_rd_req_status;
wire [15:0] stat_rd_req_latency;
wire stat_rd_req_valid;
wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_tag;
wire [LEN_WIDTH-1:0] stat_wr_op_len;
wire [3:0] stat_wr_op_status;
wire [15:0] stat_wr_op_latency;
wire stat_wr_op_valid;
wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_tag;
wire [12:0] stat_wr_req_len;
wire [3:0] stat_wr_req_status;
wire [15:0] stat_wr_req_latency;
wire stat_wr_req_valid;
stats_dma_latency #(
.COUNT_WIDTH(16),
.TAG_WIDTH($clog2(READ_OP_TABLE_SIZE)),
.LEN_WIDTH(LEN_WIDTH),
.STATUS_WIDTH(4)
)
stats_dma_latency_rd_op_inst (
.clk(clk),
.rst(rst),
/*
* Tag inputs
*/
.in_start_tag(stat_rd_op_start_tag),
.in_start_len(stat_rd_op_start_len),
.in_start_valid(stat_rd_op_start_valid),
.in_finish_tag(stat_rd_op_finish_tag),
.in_finish_status(stat_rd_op_finish_status),
.in_finish_valid(stat_rd_op_finish_valid),
/*
* Statistics increment output
*/
.out_tag(stat_rd_op_tag),
.out_len(stat_rd_op_len),
.out_status(stat_rd_op_status),
.out_latency(stat_rd_op_latency),
.out_valid(stat_rd_op_valid)
);
stats_dma_latency #(
.COUNT_WIDTH(16),
.TAG_WIDTH($clog2(READ_OP_TABLE_SIZE)),
.LEN_WIDTH(13),
.STATUS_WIDTH(4)
)
stats_dma_latency_rd_req_inst (
.clk(clk),
.rst(rst),
/*
* Tag inputs
*/
.in_start_tag(stat_rd_req_start_tag),
.in_start_len(stat_rd_req_start_len),
.in_start_valid(stat_rd_req_start_valid),
.in_finish_tag(stat_rd_req_finish_tag),
.in_finish_status(stat_rd_req_finish_status),
.in_finish_valid(stat_rd_req_finish_valid),
/*
* Statistics increment output
*/
.out_tag(stat_rd_req_tag),
.out_len(stat_rd_req_len),
.out_status(stat_rd_req_status),
.out_latency(stat_rd_req_latency),
.out_valid(stat_rd_req_valid)
);
stats_dma_latency #(
.COUNT_WIDTH(16),
.TAG_WIDTH($clog2(WRITE_OP_TABLE_SIZE)),
.LEN_WIDTH(LEN_WIDTH),
.STATUS_WIDTH(4)
)
stats_dma_latency_wr_op_inst (
.clk(clk),
.rst(rst),
/*
* Tag inputs
*/
.in_start_tag(stat_wr_op_start_tag),
.in_start_len(stat_wr_op_start_len),
.in_start_valid(stat_wr_op_start_valid),
.in_finish_tag(stat_wr_op_finish_tag),
.in_finish_status(stat_wr_op_finish_status),
.in_finish_valid(stat_wr_op_finish_valid),
/*
* Statistics increment output
*/
.out_tag(stat_wr_op_tag),
.out_len(stat_wr_op_len),
.out_status(stat_wr_op_status),
.out_latency(stat_wr_op_latency),
.out_valid(stat_wr_op_valid)
);
stats_dma_latency #(
.COUNT_WIDTH(16),
.TAG_WIDTH($clog2(WRITE_OP_TABLE_SIZE)),
.LEN_WIDTH(13),
.STATUS_WIDTH(4)
)
stats_dma_latency_wr_req_inst (
.clk(clk),
.rst(rst),
/*
* Tag inputs
*/
.in_start_tag(stat_wr_req_start_tag),
.in_start_len(stat_wr_req_start_len),
.in_start_valid(stat_wr_req_start_valid),
.in_finish_tag(stat_wr_req_finish_tag),
.in_finish_status(stat_wr_req_finish_status),
.in_finish_valid(stat_wr_req_finish_valid),
/*
* Statistics increment output
*/
.out_tag(stat_wr_req_tag),
.out_len(stat_wr_req_len),
.out_status(stat_wr_req_status),
.out_latency(stat_wr_req_latency),
.out_valid(stat_wr_req_valid)
);
wire [15:0] stat_rd_op_count_inc = stat_rd_op_valid;
wire [15:0] stat_rd_op_bytes_inc = stat_rd_op_len;
wire [15:0] stat_rd_op_latency_inc = stat_rd_op_latency;
wire [15:0] stat_rd_op_error_inc = stat_rd_op_valid && (stat_rd_op_status != 0);
wire [15:0] stat_rd_req_count_inc = stat_rd_req_valid;
wire [15:0] stat_rd_req_latency_inc = stat_rd_req_latency;
wire [15:0] stat_rd_op_table_full_inc = stat_rd_op_table_full;
wire [15:0] stat_rd_tx_stall_inc = stat_rd_tx_stall;
wire [15:0] stat_wr_op_count_inc = stat_wr_op_valid;
wire [15:0] stat_wr_op_bytes_inc = stat_wr_op_len;
wire [15:0] stat_wr_op_latency_inc = stat_wr_op_latency;
wire [15:0] stat_wr_op_error_inc = stat_wr_op_valid && (stat_wr_op_status != 0);
wire [15:0] stat_wr_req_count_inc = stat_wr_req_valid;
wire [15:0] stat_wr_req_latency_inc = stat_wr_req_latency;
wire [15:0] stat_wr_op_table_full_inc = stat_wr_op_table_full;
wire [15:0] stat_wr_tx_stall_inc = stat_wr_tx_stall;
stats_collect #(
.COUNT(32),
.INC_WIDTH(16),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(5),
.UPDATE_PERIOD(UPDATE_PERIOD)
)
stats_collect_tx_inst (
.clk(clk),
.rst(rst),
/*
* Increment inputs
*/
.stat_inc({
16'd0, // index 31
16'd0, // index 30
16'd0, // index 29
16'd0, // index 28
stat_wr_tx_stall_inc, // index 27
16'd0, // index 26
16'd0, // index 25
16'd0, // index 24
stat_wr_op_table_full_inc, // index 23
16'd0, // index 22
stat_wr_req_latency_inc, // index 21
stat_wr_req_count_inc, // index 20
stat_wr_op_error_inc, // index 19
stat_wr_op_latency_inc, // index 18
stat_wr_op_bytes_inc, // index 17
stat_wr_op_count_inc, // index 16
16'd0, // index 15
16'd0, // index 14
16'd0, // index 13
16'd0, // index 12
stat_rd_tx_stall_inc, // index 11
16'd0, // index 10
16'd0, // index 9
16'd0, // index 8
stat_rd_op_table_full_inc, // index 7
16'd0, // index 6
stat_rd_req_latency_inc, // index 5
stat_rd_req_count_inc, // index 4
stat_rd_op_error_inc, // index 3
stat_rd_op_latency_inc, // index 2
stat_rd_op_bytes_inc, // index 1
stat_rd_op_count_inc // index 0
}),
.stat_valid({32{1'b1}}),
/*
* Statistics increment output
*/
.m_axis_stat_tdata(m_axis_stat_tdata),
.m_axis_stat_tid(m_axis_stat_tid),
.m_axis_stat_tvalid(m_axis_stat_tvalid),
.m_axis_stat_tready(m_axis_stat_tready),
/*
* Control inputs
*/
.update(update)
);
endmodule
`resetall

8
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -70,7 +70,7 @@ VERILOG_SOURCES += ../../rtl/stats_counter.v
VERILOG_SOURCES += ../../rtl/stats_collect.v
VERILOG_SOURCES += ../../rtl/stats_pcie_if.v
VERILOG_SOURCES += ../../rtl/stats_pcie_tlp.v
VERILOG_SOURCES += ../../rtl/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/stats_dma_if_axi.v
VERILOG_SOURCES += ../../rtl/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v
@ -222,7 +222,7 @@ export PARAM_AXIS_RX_FIFO_PIPELINE ?= 2
# Statistics counter subsystem
export PARAM_STAT_ENABLE ?= 1
export PARAM_STAT_DMA_ENABLE ?= 1
export PARAM_STAT_PCIE_ENABLE ?= 1
export PARAM_STAT_AXI_ENABLE ?= 1
export PARAM_STAT_INC_WIDTH ?= 24
export PARAM_STAT_ID_WIDTH ?= 12
@ -309,7 +309,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_RX_FIFO_PIPELINE=$(PARAM_AXIS_RX_FIFO_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_AXI_ENABLE=$(PARAM_STAT_AXI_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
@ -400,7 +400,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GAXIS_RX_FIFO_PIPELINE=$(PARAM_AXIS_RX_FIFO_PIPELINE)
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
COMPILE_ARGS += -GSTAT_AXI_ENABLE=$(PARAM_STAT_AXI_ENABLE)
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)

4
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -490,7 +490,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, "stats_collect.v"),
os.path.join(rtl_dir, "stats_pcie_if.v"),
os.path.join(rtl_dir, "stats_pcie_tlp.v"),
os.path.join(rtl_dir, "stats_dma_if_pcie.v"),
os.path.join(rtl_dir, "stats_dma_if_axi.v"),
os.path.join(rtl_dir, "stats_dma_latency.v"),
os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "tx_scheduler_rr.v"),
@ -643,7 +643,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
# Statistics counter subsystem
parameters['STAT_ENABLE'] = 1
parameters['STAT_DMA_ENABLE'] = 1
parameters['STAT_PCIE_ENABLE'] = 1
parameters['STAT_AXI_ENABLE'] = 1
parameters['STAT_INC_WIDTH'] = 24
parameters['STAT_ID_WIDTH'] = 12

3
fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile
View File

@ -41,6 +41,9 @@ SYN_FILES += rtl/common/rb_drp.v
SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v
SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v
SYN_FILES += rtl/common/stats_counter.v
SYN_FILES += rtl/common/stats_collect.v
SYN_FILES += rtl/common/stats_dma_if_axi.v
SYN_FILES += rtl/common/stats_dma_latency.v
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v

2
fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
View File

@ -183,6 +183,8 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_AXI_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"

2
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
View File

@ -156,6 +156,7 @@ module fpga #
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_AXI_ENABLE = 1,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
)
@ -807,6 +808,7 @@ fpga_core #(
// Statistics counter subsystem
.STAT_ENABLE(STAT_ENABLE),
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
.STAT_AXI_ENABLE(STAT_AXI_ENABLE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)

2
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
View File

@ -175,6 +175,7 @@ module fpga_core #
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_AXI_ENABLE = 1,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
)
@ -844,6 +845,7 @@ mqnic_core_axi #(
// Statistics counter subsystem
.STAT_ENABLE(STAT_ENABLE),
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
.STAT_AXI_ENABLE(STAT_AXI_ENABLE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)

4
fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
View File

@ -71,6 +71,7 @@ VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
VERILOG_SOURCES += ../../rtl/common/rb_drp.v
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_axi.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
@ -219,6 +220,7 @@ export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 2
# Statistics counter subsystem
export PARAM_STAT_ENABLE ?= 1
export PARAM_STAT_DMA_ENABLE ?= 1
export PARAM_STAT_AXI_ENABLE ?= 1
export PARAM_STAT_INC_WIDTH ?= 24
export PARAM_STAT_ID_WIDTH ?= 12
@ -296,6 +298,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_AXI_ENABLE=$(PARAM_STAT_AXI_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
@ -377,6 +380,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
COMPILE_ARGS += -GSTAT_AXI_ENABLE=$(PARAM_STAT_AXI_ENABLE)
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)

2
fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
View File

@ -373,6 +373,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "rb_drp.v"),
os.path.join(rtl_dir, "common", "stats_counter.v"),
os.path.join(rtl_dir, "common", "stats_collect.v"),
os.path.join(rtl_dir, "common", "stats_dma_if_axi.v"),
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
@ -522,6 +523,7 @@ def test_fpga_core(request):
# Statistics counter subsystem
parameters['STAT_ENABLE'] = 1
parameters['STAT_DMA_ENABLE'] = 1
parameters['STAT_AXI_ENABLE'] = 1
parameters['STAT_INC_WIDTH'] = 24
parameters['STAT_ID_WIDTH'] = 12