From d621f79d36adf608dd040e7410d6b0cbb3a5a18e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 22 Sep 2020 01:02:43 -0700 Subject: [PATCH] Update readme --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 218dc9b08..e389731cc 100644 --- a/README.md +++ b/README.md @@ -34,6 +34,8 @@ devices. Designs are included for the following FPGA boards: * Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P) * NetFPGA SUME (Xilinx Virtex 7 XC7V690T) * Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50) +* Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200) +* Xilinx Alveo U250 (Xilinx Virtex UltraScale+ XCU250) * Xilinx Alveo U280 (Xilinx Virtex UltraScale+ XCU280) * Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095) * Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)