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merged changes in axis

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This commit is contained in:
Alex Forencich 2019-03-26 18:49:15 -07:00
commit d651cb72de
10 changed files with 304 additions and 2 deletions
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63
lib/axis/rtl/axis_async_fifo.v
View File

@ -124,6 +124,7 @@ localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_sync_gray_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
@ -135,6 +136,14 @@ reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg wr_ptr_update_valid_reg = 1'b0, wr_ptr_update_valid_next;
reg wr_ptr_update_reg = 1'b0, wr_ptr_update_next;
reg wr_ptr_update_sync1_reg = 1'b0;
reg wr_ptr_update_sync2_reg = 1'b0;
reg wr_ptr_update_sync3_reg = 1'b0;
reg wr_ptr_update_ack_sync1_reg = 1'b0;
reg wr_ptr_update_ack_sync2_reg = 1'b0;
reg s_rst_sync1_reg = 1'b1;
reg s_rst_sync2_reg = 1'b1;
reg s_rst_sync3_reg = 1'b1;
@ -160,7 +169,7 @@ wire full_cur = ((wr_ptr_cur_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_
(wr_ptr_cur_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
(wr_ptr_cur_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg);
// overflow within packet
wire full_wr = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) &&
(wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0]));
@ -253,8 +262,22 @@ always @* begin
wr_ptr_next = wr_ptr_reg;
wr_ptr_cur_next = wr_ptr_cur_reg;
wr_ptr_gray_next = wr_ptr_gray_reg;
wr_ptr_sync_gray_next = wr_ptr_sync_gray_reg;
wr_ptr_cur_gray_next = wr_ptr_cur_gray_reg;
wr_ptr_update_valid_next = wr_ptr_update_valid_reg;
wr_ptr_update_next = wr_ptr_update_reg;
if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
// have updated pointer to sync
if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_next = 1'b0;
wr_ptr_sync_gray_next = wr_ptr_gray_reg;
wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg;
end
end
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if (!FRAME_FIFO) begin
@ -288,6 +311,17 @@ always @* begin
// good packet, update write pointer
wr_ptr_next = wr_ptr_cur_reg + 1;
wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_next = 1'b0;
wr_ptr_sync_gray_next = wr_ptr_gray_next;
wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg;
end else begin
// sync in progress; flag it for later
wr_ptr_update_valid_next = 1'b1;
end
good_frame_next = 1'b1;
end
end
@ -300,8 +334,12 @@ always @(posedge s_clk) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_update_reg <= 1'b0;
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
@ -310,8 +348,12 @@ always @(posedge s_clk) begin
wr_ptr_reg <= wr_ptr_next;
wr_ptr_cur_reg <= wr_ptr_cur_next;
wr_ptr_gray_reg <= wr_ptr_gray_next;
wr_ptr_sync_gray_reg <= wr_ptr_sync_gray_next;
wr_ptr_cur_gray_reg <= wr_ptr_cur_gray_next;
wr_ptr_update_valid_reg <= wr_ptr_update_valid_next;
wr_ptr_update_reg <= wr_ptr_update_next;
drop_frame_reg <= drop_frame_next;
overflow_reg <= overflow_next;
bad_frame_reg <= bad_frame_next;
@ -334,9 +376,13 @@ always @(posedge s_clk) begin
if (s_rst_sync3_reg) begin
rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_ack_sync1_reg <= 1'b0;
wr_ptr_update_ack_sync2_reg <= 1'b0;
end else begin
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
end
end
@ -344,9 +390,19 @@ always @(posedge m_clk) begin
if (m_rst_sync3_reg) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_sync1_reg <= 1'b0;
wr_ptr_update_sync2_reg <= 1'b0;
wr_ptr_update_sync3_reg <= 1'b0;
end else begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
if (!FRAME_FIFO) begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
wr_ptr_gray_sync1_reg <= wr_ptr_sync_gray_reg;
end
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
end
end
@ -367,10 +423,13 @@ always @(posedge m_clk) begin
if (m_rst_sync3_reg) begin
overflow_sync2_reg <= 1'b0;
overflow_sync3_reg <= 1'b0;
overflow_sync4_reg <= 1'b0;
bad_frame_sync2_reg <= 1'b0;
bad_frame_sync3_reg <= 1'b0;
bad_frame_sync4_reg <= 1'b0;
good_frame_sync2_reg <= 1'b0;
good_frame_sync3_reg <= 1'b0;
good_frame_sync4_reg <= 1'b0;
end else begin
overflow_sync2_reg <= overflow_sync1_reg;
overflow_sync3_reg <= overflow_sync2_reg;

75
lib/axis/syn/axis_async_fifo.tcl Normal file
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@ -0,0 +1,75 @@
# Copyright (c) 2019 Alex Forencich
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.
# AXI stream asynchronous FIFO timing constraints
foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo || REF_NAME == axis_async_fifo)}] {
puts "Inserting timing constraints for axis_async_fifo instance $fifo_inst"
# get clock periods
set read_clk [get_clocks -of_objects [get_pins $fifo_inst/rd_ptr_reg_reg[0]/C]]
set write_clk [get_clocks -of_objects [get_pins $fifo_inst/wr_ptr_reg_reg[0]/C]]
set read_clk_period [get_property -min PERIOD $read_clk]
set write_clk_period [get_property -min PERIOD $write_clk]
set min_clk_period [expr $read_clk_period < $write_clk_period ? $read_clk_period : $write_clk_period]
# reset synchronization
set reset_ffs [get_cells -hier -regexp ".*/(s|m)_rst_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
set_property ASYNC_REG TRUE $reset_ffs
set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
set_false_path -to [get_pins $fifo_inst/s_rst_sync2_reg_reg/D]
set_max_delay -from [get_cells $fifo_inst/s_rst_sync2_reg_reg] -to [get_cells $fifo_inst/s_rst_sync3_reg_reg] $min_clk_period
set_false_path -to [get_pins $fifo_inst/m_rst_sync2_reg_reg/D]
set_max_delay -from [get_cells $fifo_inst/m_rst_sync2_reg_reg] -to [get_cells $fifo_inst/m_rst_sync3_reg_reg] $min_clk_period
# pointer synchronization
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/(wr|rd)_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"]
set_max_delay -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $fifo_inst/rd_ptr_gray_sync1_reg_reg[*]] -datapath_only $read_clk_period
set_bus_skew -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $fifo_inst/rd_ptr_gray_sync1_reg_reg[*]] $write_clk_period
set_max_delay -from [get_cells "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_sync_gray_reg_reg[*]"] -to [get_cells $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]] -datapath_only $write_clk_period
set_bus_skew -from [get_cells "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_sync_gray_reg_reg[*]"] -to [get_cells $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]] $read_clk_period
# frame FIFO pointer update synchronization
set update_ffs [get_cells -hier -regexp ".*/wr_ptr_update(_ack)?_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
if {[llength $update_ffs]} {
set_property ASYNC_REG TRUE $update_ffs
set_max_delay -from [get_cells $fifo_inst/wr_ptr_update_reg_reg] -to [get_cells $fifo_inst/wr_ptr_update_sync1_reg_reg] -datapath_only $write_clk_period
set_max_delay -from [get_cells $fifo_inst/wr_ptr_update_sync3_reg_reg] -to [get_cells $fifo_inst/wr_ptr_update_ack_sync1_reg_reg] -datapath_only $read_clk_period
}
# status synchronization
foreach i {overflow bad_frame good_frame} {
set status_sync_regs [get_cells -quiet -hier -regexp ".*/${i}_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
if {[llength $status_sync_regs]} {
set_property ASYNC_REG TRUE $status_sync_regs
set_max_delay -from [get_cells $fifo_inst/${i}_sync1_reg_reg] -to [get_cells $fifo_inst/${i}_sync2_reg_reg] -datapath_only $read_clk_period
}
}
}

21
lib/axis/tb/test_axis_async_fifo.py
View File

@ -500,6 +500,27 @@ def bench():
yield delay(100)
yield s_clk.posedge
print("test 11: many small packets")
current_test.next = 11
test_frame = axis_ep.AXIStreamFrame(
b'\xAA',
id=11,
dest=1
)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()

21
lib/axis/tb/test_axis_async_fifo_64.py
View File

@ -500,6 +500,27 @@ def bench():
yield delay(100)
yield s_clk.posedge
print("test 11: many small packets")
current_test.next = 11
test_frame = axis_ep.AXIStreamFrame(
b'\xAA',
id=11,
dest=1
)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()

21
lib/axis/tb/test_axis_async_frame_fifo.py
View File

@ -668,6 +668,27 @@ def bench():
yield delay(100)
yield s_clk.posedge
print("test 12: many small packets")
current_test.next = 12
test_frame = axis_ep.AXIStreamFrame(
b'\xAA',
id=12,
dest=1
)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()

21
lib/axis/tb/test_axis_async_frame_fifo_64.py
View File

@ -668,6 +668,27 @@ def bench():
yield delay(100)
yield s_clk.posedge
print("test 12: many small packets")
current_test.next = 12
test_frame = axis_ep.AXIStreamFrame(
b'\xAA',
id=12,
dest=1
)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()

21
lib/axis/tb/test_axis_fifo.py
View File

@ -489,6 +489,27 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 11: many small packets")
current_test.next = 11
test_frame = axis_ep.AXIStreamFrame(
b'\xAA',
id=11,
dest=1
)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()

21
lib/axis/tb/test_axis_fifo_64.py
View File

@ -489,6 +489,27 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 11: many small packets")
current_test.next = 11
test_frame = axis_ep.AXIStreamFrame(
b'\xAA',
id=11,
dest=1
)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()

21
lib/axis/tb/test_axis_frame_fifo.py
View File

@ -594,6 +594,27 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 12: many small packets")
current_test.next = 12
test_frame = axis_ep.AXIStreamFrame(
b'\xAA',
id=12,
dest=1
)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()

21
lib/axis/tb/test_axis_frame_fifo_64.py
View File

@ -594,6 +594,27 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 12: many small packets")
current_test.next = 12
test_frame = axis_ep.AXIStreamFrame(
b'\xAA',
id=12,
dest=1
)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()