From d67c9ff70e525e5212691c468ece35187bfd1d37 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 23 Aug 2019 07:44:33 -0700 Subject: [PATCH] Pull out scheduler op table size parameter --- fpga/common/rtl/interface.v | 3 +++ fpga/common/rtl/port.v | 4 +++- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 2 ++ fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v | 2 ++ fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v | 2 ++ fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v | 2 ++ fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 2 ++ fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v | 2 ++ fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v | 2 ++ fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v | 2 ++ 10 files changed, 22 insertions(+), 1 deletion(-) diff --git a/fpga/common/rtl/interface.v b/fpga/common/rtl/interface.v index bee402d26..771bc28b3 100644 --- a/fpga/common/rtl/interface.v +++ b/fpga/common/rtl/interface.v @@ -84,6 +84,8 @@ module interface # parameter RX_PKT_TABLE_SIZE = 8, // Transmit scheduler type parameter TX_SCHEDULER = "RR", + // Scheduler operation table size + parameter TX_SCHEDULER_OP_TABLE_SIZE = 32, // Scheduler TDMA index width parameter TDMA_INDEX_WIDTH = 8, // Interrupt number width @@ -2366,6 +2368,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .PTP_TS_ENABLE(PTP_TS_ENABLE), diff --git a/fpga/common/rtl/port.v b/fpga/common/rtl/port.v index 66aeb1718..89c34e681 100644 --- a/fpga/common/rtl/port.v +++ b/fpga/common/rtl/port.v @@ -70,6 +70,8 @@ module port # parameter RX_PKT_TABLE_SIZE = 8, // Transmit scheduler type parameter TX_SCHEDULER = "RR", + // Scheduler operation table size + parameter TX_SCHEDULER_OP_TABLE_SIZE = 32, // Scheduler TDMA index width parameter TDMA_INDEX_WIDTH = 8, // Queue element pointer width @@ -980,7 +982,7 @@ if (TX_SCHEDULER == "RR") begin .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), .AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH), .REQ_TAG_WIDTH(REQ_TAG_WIDTH), - .OP_TABLE_SIZE(16), + .OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .PIPELINE(3) ) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 09cc5bafc..1a4257d00 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -305,6 +305,7 @@ parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = 32; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) @@ -2106,6 +2107,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16), diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v index 357d23337..5cc27454b 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -243,6 +243,7 @@ parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = 32; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) @@ -1930,6 +1931,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16), diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v index 6c3469531..fa107496e 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v @@ -269,6 +269,7 @@ parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = 32; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) @@ -2077,6 +2078,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16), diff --git a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v index d017bdbe4..4cfa67490 100644 --- a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v @@ -306,6 +306,7 @@ parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = 32; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) @@ -2042,6 +2043,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16), diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 955bd1f7f..435980019 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -305,6 +305,7 @@ parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "TDMA_RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = 32; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) @@ -2106,6 +2107,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16), diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v index 6c54bee97..b80034acb 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -243,6 +243,7 @@ parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "TDMA_RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = 32; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) @@ -1930,6 +1931,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16), diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v index be01e2b6b..aea1ebca6 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v @@ -269,6 +269,7 @@ parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "TDMA_RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = 32; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) @@ -2077,6 +2078,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16), diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v index 267154f42..3c230f573 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v @@ -306,6 +306,7 @@ parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "TDMA_RR"; +parameter TX_SCHEDULER_OP_TABLE_SIZE = 32; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) @@ -2042,6 +2043,7 @@ generate .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16),