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Pull out scheduler op table size parameter

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This commit is contained in:
Alex Forencich 2019-08-23 07:44:33 -07:00
parent 744ac22c75
commit d67c9ff70e
10 changed files with 22 additions and 1 deletions
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3
fpga/common/rtl/interface.v
View File

@ -84,6 +84,8 @@ module interface #
parameter RX_PKT_TABLE_SIZE = 8,
// Transmit scheduler type
parameter TX_SCHEDULER = "RR",
// Scheduler operation table size
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32,
// Scheduler TDMA index width
parameter TDMA_INDEX_WIDTH = 8,
// Interrupt number width
@ -2366,6 +2368,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),

4
fpga/common/rtl/port.v
View File

@ -70,6 +70,8 @@ module port #
parameter RX_PKT_TABLE_SIZE = 8,
// Transmit scheduler type
parameter TX_SCHEDULER = "RR",
// Scheduler operation table size
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32,
// Scheduler TDMA index width
parameter TDMA_INDEX_WIDTH = 8,
// Queue element pointer width
@ -980,7 +982,7 @@ if (TX_SCHEDULER == "RR") begin
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.OP_TABLE_SIZE(16),
.OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.PIPELINE(3)
)

2
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -305,6 +305,7 @@ parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)
parameter TX_SCHEDULER = "RR";
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
@ -2106,6 +2107,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),

2
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -243,6 +243,7 @@ parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)
parameter TX_SCHEDULER = "RR";
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
@ -1930,6 +1931,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),

2
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -269,6 +269,7 @@ parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)
parameter TX_SCHEDULER = "RR";
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
@ -2077,6 +2078,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),

2
fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -306,6 +306,7 @@ parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)
parameter TX_SCHEDULER = "RR";
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
@ -2042,6 +2043,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),

2
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -305,6 +305,7 @@ parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)
parameter TX_SCHEDULER = "TDMA_RR";
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
@ -2106,6 +2107,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),

2
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -243,6 +243,7 @@ parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)
parameter TX_SCHEDULER = "TDMA_RR";
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
@ -1930,6 +1931,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),

2
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -269,6 +269,7 @@ parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)
parameter TX_SCHEDULER = "TDMA_RR";
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
@ -2077,6 +2078,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),

2
fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -306,6 +306,7 @@ parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)
parameter TX_SCHEDULER = "TDMA_RR";
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
@ -2042,6 +2043,7 @@ generate
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.INT_WIDTH(8),
.QUEUE_PTR_WIDTH(16),