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Add extra output register for flash interface to improve routability and timing

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This commit is contained in:
Alex Forencich 2020-10-08 19:22:28 -07:00
parent b140d73660
commit d6810db7f5
25 changed files with 546 additions and 154 deletions
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36
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -294,11 +294,29 @@ wire [3:0] qspi_1_dq_o_int;
wire [3:0] qspi_1_dq_oe_int;
wire qspi_1_cs_int;
assign qspi_1_dq[0] = qspi_1_dq_oe_int[0] ? qspi_1_dq_o_int[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_int[1] ? qspi_1_dq_o_int[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_int[2] ? qspi_1_dq_o_int[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_int[3] ? qspi_1_dq_o_int[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_0_dq_o_reg;
reg [3:0] qspi_0_dq_oe_reg;
reg qspi_0_cs_reg;
reg [3:0] qspi_1_dq_o_reg;
reg [3:0] qspi_1_dq_oe_reg;
reg qspi_1_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_0_dq_o_reg <= qspi_0_dq_o_int;
qspi_0_dq_oe_reg <= qspi_0_dq_oe_int;
qspi_0_cs_reg <= qspi_0_cs_int;
qspi_1_dq_o_reg <= qspi_1_dq_o_int;
qspi_1_dq_oe_reg <= qspi_1_dq_oe_int;
qspi_1_cs_reg <= qspi_1_cs_int;
end
assign qspi_1_dq[0] = qspi_1_dq_oe_reg[0] ? qspi_1_dq_o_reg[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_reg[1] ? qspi_1_dq_o_reg[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_reg[2] ? qspi_1_dq_o_reg[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_reg[3] ? qspi_1_dq_o_reg[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_reg;
sync_signal #(
.WIDTH(8),
@ -315,17 +333,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_0_dq_int),
.DO(qspi_0_dq_o_int),
.DTS(~qspi_0_dq_oe_int),
.DO(qspi_0_dq_o_reg),
.DTS(~qspi_0_dq_oe_reg),
.EOS(),
.FCSBO(qspi_0_cs_int),
.FCSBO(qspi_0_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

36
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
View File

@ -295,11 +295,29 @@ wire [3:0] qspi_1_dq_o_int;
wire [3:0] qspi_1_dq_oe_int;
wire qspi_1_cs_int;
assign qspi_1_dq[0] = qspi_1_dq_oe_int[0] ? qspi_1_dq_o_int[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_int[1] ? qspi_1_dq_o_int[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_int[2] ? qspi_1_dq_o_int[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_int[3] ? qspi_1_dq_o_int[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_0_dq_o_reg;
reg [3:0] qspi_0_dq_oe_reg;
reg qspi_0_cs_reg;
reg [3:0] qspi_1_dq_o_reg;
reg [3:0] qspi_1_dq_oe_reg;
reg qspi_1_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_0_dq_o_reg <= qspi_0_dq_o_int;
qspi_0_dq_oe_reg <= qspi_0_dq_oe_int;
qspi_0_cs_reg <= qspi_0_cs_int;
qspi_1_dq_o_reg <= qspi_1_dq_o_int;
qspi_1_dq_oe_reg <= qspi_1_dq_oe_int;
qspi_1_cs_reg <= qspi_1_cs_int;
end
assign qspi_1_dq[0] = qspi_1_dq_oe_reg[0] ? qspi_1_dq_o_reg[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_reg[1] ? qspi_1_dq_o_reg[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_reg[2] ? qspi_1_dq_o_reg[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_reg[3] ? qspi_1_dq_o_reg[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_reg;
sync_signal #(
.WIDTH(8),
@ -316,17 +334,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_0_dq_int),
.DO(qspi_0_dq_o_int),
.DTS(~qspi_0_dq_oe_int),
.DO(qspi_0_dq_o_reg),
.DTS(~qspi_0_dq_oe_reg),
.EOS(),
.FCSBO(qspi_0_cs_int),
.FCSBO(qspi_0_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

36
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -295,11 +295,29 @@ wire [3:0] qspi_1_dq_o_int;
wire [3:0] qspi_1_dq_oe_int;
wire qspi_1_cs_int;
assign qspi_1_dq[0] = qspi_1_dq_oe_int[0] ? qspi_1_dq_o_int[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_int[1] ? qspi_1_dq_o_int[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_int[2] ? qspi_1_dq_o_int[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_int[3] ? qspi_1_dq_o_int[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_0_dq_o_reg;
reg [3:0] qspi_0_dq_oe_reg;
reg qspi_0_cs_reg;
reg [3:0] qspi_1_dq_o_reg;
reg [3:0] qspi_1_dq_oe_reg;
reg qspi_1_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_0_dq_o_reg <= qspi_0_dq_o_int;
qspi_0_dq_oe_reg <= qspi_0_dq_oe_int;
qspi_0_cs_reg <= qspi_0_cs_int;
qspi_1_dq_o_reg <= qspi_1_dq_o_int;
qspi_1_dq_oe_reg <= qspi_1_dq_oe_int;
qspi_1_cs_reg <= qspi_1_cs_int;
end
assign qspi_1_dq[0] = qspi_1_dq_oe_reg[0] ? qspi_1_dq_o_reg[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_reg[1] ? qspi_1_dq_o_reg[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_reg[2] ? qspi_1_dq_o_reg[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_reg[3] ? qspi_1_dq_o_reg[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_reg;
sync_signal #(
.WIDTH(8),
@ -316,17 +334,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_0_dq_int),
.DO(qspi_0_dq_o_int),
.DTS(~qspi_0_dq_oe_int),
.DO(qspi_0_dq_o_reg),
.DTS(~qspi_0_dq_oe_reg),
.EOS(),
.FCSBO(qspi_0_cs_int),
.FCSBO(qspi_0_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -282,6 +282,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -300,17 +312,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/AU200/fpga_10g/rtl/fpga.v
View File

@ -279,6 +279,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -297,17 +309,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -282,6 +282,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -300,17 +312,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/AU250/fpga_10g/rtl/fpga.v
View File

@ -279,6 +279,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -297,17 +309,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -217,6 +217,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -232,17 +244,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/AU280/fpga_10g/rtl/fpga.v
View File

@ -218,6 +218,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -233,17 +245,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -195,6 +195,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -210,17 +222,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/AU50/fpga_10g/rtl/fpga.v
View File

@ -196,6 +196,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -211,17 +223,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

36
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -274,13 +274,35 @@ wire flash_oe_n_int;
wire flash_we_n_int;
wire flash_adv_n_int;
assign flash_dq = flash_dq_oe_int ? flash_dq_o_int : 16'hzzzz;
assign flash_addr = flash_addr_int;
assign flash_region = flash_region_oe_int ? flash_region_int : 1'bz;
assign flash_ce_n = flash_ce_n_int;
assign flash_oe_n = flash_oe_n_int;
assign flash_we_n = flash_we_n_int;
assign flash_adv_n = flash_adv_n_int;
reg [15:0] flash_dq_o_reg;
reg flash_dq_oe_reg;
reg [22:0] flash_addr_reg;
reg flash_region_reg;
reg flash_region_oe_reg;
reg flash_ce_n_reg;
reg flash_oe_n_reg;
reg flash_we_n_reg;
reg flash_adv_n_reg;
always @(posedge pcie_user_clk) begin
flash_dq_o_reg <= flash_dq_o_int;
flash_dq_oe_reg <= flash_dq_oe_int;
flash_addr_reg <= flash_addr_int;
flash_region_reg <= flash_region_int;
flash_region_oe_reg <= flash_region_oe_int;
flash_ce_n_reg <= flash_ce_n_int;
flash_oe_n_reg <= flash_oe_n_int;
flash_we_n_reg <= flash_we_n_int;
flash_adv_n_reg <= flash_adv_n_int;
end
assign flash_dq = flash_dq_oe_reg ? flash_dq_o_reg : 16'hzzzz;
assign flash_addr = flash_addr_reg;
assign flash_region = flash_region_oe_reg ? flash_region_reg : 1'bz;
assign flash_ce_n = flash_ce_n_reg;
assign flash_oe_n = flash_oe_n_reg;
assign flash_we_n = flash_we_n_reg;
assign flash_adv_n = flash_adv_n_reg;
sync_signal #(
.WIDTH(16),

36
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v
View File

@ -258,13 +258,35 @@ wire flash_oe_n_int;
wire flash_we_n_int;
wire flash_adv_n_int;
assign flash_dq = flash_dq_oe_int ? flash_dq_o_int : 16'hzzzz;
assign flash_addr = flash_addr_int;
assign flash_region = flash_region_oe_int ? flash_region_int : 1'bz;
assign flash_ce_n = flash_ce_n_int;
assign flash_oe_n = flash_oe_n_int;
assign flash_we_n = flash_we_n_int;
assign flash_adv_n = flash_adv_n_int;
reg [15:0] flash_dq_o_reg;
reg flash_dq_oe_reg;
reg [22:0] flash_addr_reg;
reg flash_region_reg;
reg flash_region_oe_reg;
reg flash_ce_n_reg;
reg flash_oe_n_reg;
reg flash_we_n_reg;
reg flash_adv_n_reg;
always @(posedge pcie_user_clk) begin
flash_dq_o_reg <= flash_dq_o_int;
flash_dq_oe_reg <= flash_dq_oe_int;
flash_addr_reg <= flash_addr_int;
flash_region_reg <= flash_region_int;
flash_region_oe_reg <= flash_region_oe_int;
flash_ce_n_reg <= flash_ce_n_int;
flash_oe_n_reg <= flash_oe_n_int;
flash_we_n_reg <= flash_we_n_int;
flash_adv_n_reg <= flash_adv_n_int;
end
assign flash_dq = flash_dq_oe_reg ? flash_dq_o_reg : 16'hzzzz;
assign flash_addr = flash_addr_reg;
assign flash_region = flash_region_oe_reg ? flash_region_reg : 1'bz;
assign flash_ce_n = flash_ce_n_reg;
assign flash_oe_n = flash_oe_n_reg;
assign flash_we_n = flash_we_n_reg;
assign flash_adv_n = flash_adv_n_reg;
sync_signal #(
.WIDTH(16),

40
fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
View File

@ -295,12 +295,34 @@ wire flash_oe_n_int;
wire flash_we_n_int;
wire flash_adv_n_int;
assign flash_dq[15:4] = flash_dq_oe_int ? flash_dq_o_int[15:4] : 12'hzzz;
assign flash_addr = flash_addr_int;
assign flash_region = flash_region_oe_int ? flash_region_int : 2'bz;
assign flash_oe_n = flash_oe_n_int;
assign flash_we_n = flash_we_n_int;
assign flash_adv_n = flash_adv_n_int;
reg [15:0] flash_dq_o_reg;
reg flash_dq_oe_reg;
reg [23:0] flash_addr_reg;
reg [1:0] flash_region_reg;
reg flash_region_oe_reg;
reg flash_ce_n_reg;
reg flash_oe_n_reg;
reg flash_we_n_reg;
reg flash_adv_n_reg;
always @(posedge pcie_user_clk) begin
flash_dq_o_reg <= flash_dq_o_int;
flash_dq_oe_reg <= flash_dq_oe_int;
flash_addr_reg <= flash_addr_int;
flash_region_reg <= flash_region_int;
flash_region_oe_reg <= flash_region_oe_int;
flash_ce_n_reg <= flash_ce_n_int;
flash_oe_n_reg <= flash_oe_n_int;
flash_we_n_reg <= flash_we_n_int;
flash_adv_n_reg <= flash_adv_n_int;
end
assign flash_dq[15:4] = flash_dq_oe_reg ? flash_dq_o_reg[15:4] : 12'hzzz;
assign flash_addr = flash_addr_reg;
assign flash_region = flash_region_oe_reg ? flash_region_reg : 2'bz;
assign flash_oe_n = flash_oe_n_reg;
assign flash_we_n = flash_we_n_reg;
assign flash_adv_n = flash_adv_n_reg;
sync_signal #(
.WIDTH(16),
@ -317,10 +339,10 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(flash_dq_int),
.DO(flash_dq_o_int[3:0]),
.DTS({4{~flash_dq_oe_int}}),
.DO(flash_dq_o_reg[3:0]),
.DTS({4{~flash_dq_oe_reg}}),
.EOS(),
.FCSBO(flash_ce_n_int),
.FCSBO(flash_ce_n_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),

36
fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
View File

@ -321,11 +321,29 @@ wire [3:0] qspi_1_dq_o_int;
wire [3:0] qspi_1_dq_oe_int;
wire qspi_1_cs_int;
assign qspi_1_dq[0] = qspi_1_dq_oe_int[0] ? qspi_1_dq_o_int[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_int[1] ? qspi_1_dq_o_int[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_int[2] ? qspi_1_dq_o_int[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_int[3] ? qspi_1_dq_o_int[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_0_dq_o_reg;
reg [3:0] qspi_0_dq_oe_reg;
reg qspi_0_cs_reg;
reg [3:0] qspi_1_dq_o_reg;
reg [3:0] qspi_1_dq_oe_reg;
reg qspi_1_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_0_dq_o_reg <= qspi_0_dq_o_int;
qspi_0_dq_oe_reg <= qspi_0_dq_oe_int;
qspi_0_cs_reg <= qspi_0_cs_int;
qspi_1_dq_o_reg <= qspi_1_dq_o_int;
qspi_1_dq_oe_reg <= qspi_1_dq_oe_int;
qspi_1_cs_reg <= qspi_1_cs_int;
end
assign qspi_1_dq[0] = qspi_1_dq_oe_reg[0] ? qspi_1_dq_o_reg[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_reg[1] ? qspi_1_dq_o_reg[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_reg[2] ? qspi_1_dq_o_reg[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_reg[3] ? qspi_1_dq_o_reg[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_reg;
sync_signal #(
.WIDTH(8),
@ -342,17 +360,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_0_dq_int),
.DO(qspi_0_dq_o_int),
.DTS(~qspi_0_dq_oe_int),
.DO(qspi_0_dq_o_reg),
.DTS(~qspi_0_dq_oe_reg),
.EOS(),
.FCSBO(qspi_0_cs_int),
.FCSBO(qspi_0_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

36
fpga/mqnic/VCU118/fpga_10g/rtl/fpga.v
View File

@ -318,11 +318,29 @@ wire [3:0] qspi_1_dq_o_int;
wire [3:0] qspi_1_dq_oe_int;
wire qspi_1_cs_int;
assign qspi_1_dq[0] = qspi_1_dq_oe_int[0] ? qspi_1_dq_o_int[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_int[1] ? qspi_1_dq_o_int[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_int[2] ? qspi_1_dq_o_int[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_int[3] ? qspi_1_dq_o_int[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_0_dq_o_reg;
reg [3:0] qspi_0_dq_oe_reg;
reg qspi_0_cs_reg;
reg [3:0] qspi_1_dq_o_reg;
reg [3:0] qspi_1_dq_oe_reg;
reg qspi_1_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_0_dq_o_reg <= qspi_0_dq_o_int;
qspi_0_dq_oe_reg <= qspi_0_dq_oe_int;
qspi_0_cs_reg <= qspi_0_cs_int;
qspi_1_dq_o_reg <= qspi_1_dq_o_int;
qspi_1_dq_oe_reg <= qspi_1_dq_oe_int;
qspi_1_cs_reg <= qspi_1_cs_int;
end
assign qspi_1_dq[0] = qspi_1_dq_oe_reg[0] ? qspi_1_dq_o_reg[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_reg[1] ? qspi_1_dq_o_reg[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_reg[2] ? qspi_1_dq_o_reg[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_reg[3] ? qspi_1_dq_o_reg[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_reg;
sync_signal #(
.WIDTH(8),
@ -339,17 +357,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_0_dq_int),
.DO(qspi_0_dq_o_int),
.DTS(~qspi_0_dq_oe_int),
.DO(qspi_0_dq_o_reg),
.DTS(~qspi_0_dq_oe_reg),
.EOS(),
.FCSBO(qspi_0_cs_int),
.FCSBO(qspi_0_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
View File

@ -282,6 +282,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -300,17 +312,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/VCU1525/fpga_10g/rtl/fpga.v
View File

@ -279,6 +279,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -297,17 +309,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
View File

@ -318,6 +318,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -333,17 +345,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v
View File

@ -315,6 +315,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -330,17 +342,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

20
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
View File

@ -315,6 +315,18 @@ wire [3:0] qspi_dq_o_int;
wire [3:0] qspi_dq_oe_int;
wire qspi_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_dq_o_reg;
reg [3:0] qspi_dq_oe_reg;
reg qspi_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_dq_o_reg <= qspi_dq_o_int;
qspi_dq_oe_reg <= qspi_dq_oe_int;
qspi_cs_reg <= qspi_cs_int;
end
sync_signal #(
.WIDTH(4),
.N(2)
@ -330,17 +342,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_dq_int),
.DO(qspi_dq_o_int),
.DTS(~qspi_dq_oe_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
.EOS(),
.FCSBO(qspi_cs_int),
.FCSBO(qspi_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

36
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
View File

@ -295,11 +295,29 @@ wire [3:0] qspi_1_dq_o_int;
wire [3:0] qspi_1_dq_oe_int;
wire qspi_1_cs_int;
assign qspi_1_dq[0] = qspi_1_dq_oe_int[0] ? qspi_1_dq_o_int[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_int[1] ? qspi_1_dq_o_int[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_int[2] ? qspi_1_dq_o_int[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_int[3] ? qspi_1_dq_o_int[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_0_dq_o_reg;
reg [3:0] qspi_0_dq_oe_reg;
reg qspi_0_cs_reg;
reg [3:0] qspi_1_dq_o_reg;
reg [3:0] qspi_1_dq_oe_reg;
reg qspi_1_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_0_dq_o_reg <= qspi_0_dq_o_int;
qspi_0_dq_oe_reg <= qspi_0_dq_oe_int;
qspi_0_cs_reg <= qspi_0_cs_int;
qspi_1_dq_o_reg <= qspi_1_dq_o_int;
qspi_1_dq_oe_reg <= qspi_1_dq_oe_int;
qspi_1_cs_reg <= qspi_1_cs_int;
end
assign qspi_1_dq[0] = qspi_1_dq_oe_reg[0] ? qspi_1_dq_o_reg[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_reg[1] ? qspi_1_dq_o_reg[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_reg[2] ? qspi_1_dq_o_reg[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_reg[3] ? qspi_1_dq_o_reg[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_reg;
sync_signal #(
.WIDTH(8),
@ -316,17 +334,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_0_dq_int),
.DO(qspi_0_dq_o_int),
.DTS(~qspi_0_dq_oe_int),
.DO(qspi_0_dq_o_reg),
.DTS(~qspi_0_dq_oe_reg),
.EOS(),
.FCSBO(qspi_0_cs_int),
.FCSBO(qspi_0_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)

36
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -274,13 +274,35 @@ wire flash_oe_n_int;
wire flash_we_n_int;
wire flash_adv_n_int;
assign flash_dq = flash_dq_oe_int ? flash_dq_o_int : 16'hzzzz;
assign flash_addr = flash_addr_int;
assign flash_region = flash_region_oe_int ? flash_region_int : 1'bz;
assign flash_ce_n = flash_ce_n_int;
assign flash_oe_n = flash_oe_n_int;
assign flash_we_n = flash_we_n_int;
assign flash_adv_n = flash_adv_n_int;
reg [15:0] flash_dq_o_reg;
reg flash_dq_oe_reg;
reg [22:0] flash_addr_reg;
reg flash_region_reg;
reg flash_region_oe_reg;
reg flash_ce_n_reg;
reg flash_oe_n_reg;
reg flash_we_n_reg;
reg flash_adv_n_reg;
always @(posedge pcie_user_clk) begin
flash_dq_o_reg <= flash_dq_o_int;
flash_dq_oe_reg <= flash_dq_oe_int;
flash_addr_reg <= flash_addr_int;
flash_region_reg <= flash_region_int;
flash_region_oe_reg <= flash_region_oe_int;
flash_ce_n_reg <= flash_ce_n_int;
flash_oe_n_reg <= flash_oe_n_int;
flash_we_n_reg <= flash_we_n_int;
flash_adv_n_reg <= flash_adv_n_int;
end
assign flash_dq = flash_dq_oe_reg ? flash_dq_o_reg : 16'hzzzz;
assign flash_addr = flash_addr_reg;
assign flash_region = flash_region_oe_reg ? flash_region_reg : 1'bz;
assign flash_ce_n = flash_ce_n_reg;
assign flash_oe_n = flash_oe_n_reg;
assign flash_we_n = flash_we_n_reg;
assign flash_adv_n = flash_adv_n_reg;
sync_signal #(
.WIDTH(16),

40
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v
View File

@ -295,12 +295,34 @@ wire flash_oe_n_int;
wire flash_we_n_int;
wire flash_adv_n_int;
assign flash_dq[15:4] = flash_dq_oe_int ? flash_dq_o_int[15:4] : 12'hzzz;
assign flash_addr = flash_addr_int;
assign flash_region = flash_region_oe_int ? flash_region_int : 2'bz;
assign flash_oe_n = flash_oe_n_int;
assign flash_we_n = flash_we_n_int;
assign flash_adv_n = flash_adv_n_int;
reg [15:0] flash_dq_o_reg;
reg flash_dq_oe_reg;
reg [23:0] flash_addr_reg;
reg [1:0] flash_region_reg;
reg flash_region_oe_reg;
reg flash_ce_n_reg;
reg flash_oe_n_reg;
reg flash_we_n_reg;
reg flash_adv_n_reg;
always @(posedge pcie_user_clk) begin
flash_dq_o_reg <= flash_dq_o_int;
flash_dq_oe_reg <= flash_dq_oe_int;
flash_addr_reg <= flash_addr_int;
flash_region_reg <= flash_region_int;
flash_region_oe_reg <= flash_region_oe_int;
flash_ce_n_reg <= flash_ce_n_int;
flash_oe_n_reg <= flash_oe_n_int;
flash_we_n_reg <= flash_we_n_int;
flash_adv_n_reg <= flash_adv_n_int;
end
assign flash_dq[15:4] = flash_dq_oe_reg ? flash_dq_o_reg[15:4] : 12'hzzz;
assign flash_addr = flash_addr_reg;
assign flash_region = flash_region_oe_reg ? flash_region_reg : 2'bz;
assign flash_oe_n = flash_oe_n_reg;
assign flash_we_n = flash_we_n_reg;
assign flash_adv_n = flash_adv_n_reg;
sync_signal #(
.WIDTH(16),
@ -317,10 +339,10 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(flash_dq_int),
.DO(flash_dq_o_int[3:0]),
.DTS({4{~flash_dq_oe_int}}),
.DO(flash_dq_o_reg[3:0]),
.DTS({4{~flash_dq_oe_reg}}),
.EOS(),
.FCSBO(flash_ce_n_int),
.FCSBO(flash_ce_n_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),

36
fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga.v
View File

@ -318,11 +318,29 @@ wire [3:0] qspi_1_dq_o_int;
wire [3:0] qspi_1_dq_oe_int;
wire qspi_1_cs_int;
assign qspi_1_dq[0] = qspi_1_dq_oe_int[0] ? qspi_1_dq_o_int[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_int[1] ? qspi_1_dq_o_int[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_int[2] ? qspi_1_dq_o_int[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_int[3] ? qspi_1_dq_o_int[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_int;
reg qspi_clk_reg;
reg [3:0] qspi_0_dq_o_reg;
reg [3:0] qspi_0_dq_oe_reg;
reg qspi_0_cs_reg;
reg [3:0] qspi_1_dq_o_reg;
reg [3:0] qspi_1_dq_oe_reg;
reg qspi_1_cs_reg;
always @(posedge pcie_user_clk) begin
qspi_clk_reg <= qspi_clk_int;
qspi_0_dq_o_reg <= qspi_0_dq_o_int;
qspi_0_dq_oe_reg <= qspi_0_dq_oe_int;
qspi_0_cs_reg <= qspi_0_cs_int;
qspi_1_dq_o_reg <= qspi_1_dq_o_int;
qspi_1_dq_oe_reg <= qspi_1_dq_oe_int;
qspi_1_cs_reg <= qspi_1_cs_int;
end
assign qspi_1_dq[0] = qspi_1_dq_oe_reg[0] ? qspi_1_dq_o_reg[0] : 1'bz;
assign qspi_1_dq[1] = qspi_1_dq_oe_reg[1] ? qspi_1_dq_o_reg[1] : 1'bz;
assign qspi_1_dq[2] = qspi_1_dq_oe_reg[2] ? qspi_1_dq_o_reg[2] : 1'bz;
assign qspi_1_dq[3] = qspi_1_dq_oe_reg[3] ? qspi_1_dq_o_reg[3] : 1'bz;
assign qspi_1_cs = qspi_1_cs_reg;
sync_signal #(
.WIDTH(8),
@ -339,17 +357,17 @@ startupe3_inst (
.CFGCLK(),
.CFGMCLK(),
.DI(qspi_0_dq_int),
.DO(qspi_0_dq_o_int),
.DTS(~qspi_0_dq_oe_int),
.DO(qspi_0_dq_o_reg),
.DTS(~qspi_0_dq_oe_reg),
.EOS(),
.FCSBO(qspi_0_cs_int),
.FCSBO(qspi_0_cs_reg),
.FCSBTS(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(qspi_clk_int),
.USRCCLKO(qspi_clk_reg),
.USRCCLKTS(1'b0),
.USRDONEO(1'b0),
.USRDONETS(1'b1)