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Use correct offsets in testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-06-23 02:39:22 -07:00
parent 2f881e154a
commit d730369671
3 changed files with 6 additions and 6 deletions
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4
example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py
View File

@ -590,14 +590,14 @@ async def run_test(dut):
size = 8+64 size = 8+64
stride = 0 stride = 0
for count in range(8, 256+1, 8): for count in range(8, 256+1, 8):
await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000) await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
tb.log.info("Test RX completion buffer (CPLH, 8+128+8)") tb.log.info("Test RX completion buffer (CPLH, 8+128+8)")
size = 8+128+8 size = 8+128+8
stride = 0 stride = 0
for count in range(8, 256+1, 8): for count in range(8, 256+1, 8):
await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000) await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
tb.log.info("Test RX completion buffer (CPLD)") tb.log.info("Test RX completion buffer (CPLD)")

4
example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
View File

@ -538,14 +538,14 @@ async def run_test(dut):
size = 8+64 size = 8+64
stride = 0 stride = 0
for count in range(8, 256+1, 8): for count in range(8, 256+1, 8):
await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000) await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
tb.log.info("Test RX completion buffer (CPLH, 8+128+8)") tb.log.info("Test RX completion buffer (CPLH, 8+128+8)")
size = 8+128+8 size = 8+128+8
stride = 0 stride = 0
for count in range(8, 256+1, 8): for count in range(8, 256+1, 8):
await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000) await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
tb.log.info("Test RX completion buffer (CPLD)") tb.log.info("Test RX completion buffer (CPLD)")

4
example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
View File

@ -631,14 +631,14 @@ async def run_test(dut):
size = 8+64 size = 8+64
stride = 0 stride = 0
for count in range(8, 256+1, 8): for count in range(8, 256+1, 8):
await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000) await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
tb.log.info("Test RX completion buffer (CPLH, 8+128+8)") tb.log.info("Test RX completion buffer (CPLH, 8+128+8)")
size = 8+128+8 size = 8+128+8
stride = 0 stride = 0
for count in range(8, 256+1, 8): for count in range(8, 256+1, 8):
await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000) await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
tb.log.info("Test RX completion buffer (CPLD)") tb.log.info("Test RX completion buffer (CPLD)")