Properly handle short packets

rtl/axis_eth_fcs_check.v

@@ -149,7 +149,20 @@ always @* begin
                     frame_ptr_next = 1;
                     reset_crc = 0;
                     update_crc = 1;
-                    state_next = STATE_PAYLOAD;
+                    if (input_axis_tlast) begin
+                        shift_reset = 1;
+                        reset_crc = 1;
+                        output_axis_tlast_int = 1;
+                        output_axis_tuser_int = input_axis_tuser;
+                        if ({input_axis_tdata, input_axis_tdata_d0, input_axis_tdata_d1, input_axis_tdata_d2} != ~crc_next) begin
+                            output_axis_tuser_int = 1;
+                            error_bad_fcs_next = 1;
+                        end
+                        input_axis_tready_next = output_axis_tready_int_early;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        state_next = STATE_PAYLOAD;
+                    end
                 end else begin
                     state_next = STATE_IDLE;
                 end

tb/test_axis_eth_fcs_check.py

@@ -26,6 +26,8 @@ THE SOFTWARE.
 from myhdl import *
 import os
 from Queue import Queue
+import struct
+import zlib
 
 import axis_ep
 import eth_ep
@@ -414,6 +416,36 @@ def bench():
 
                 yield delay(100)
 
+        for payload_len in list(range(1,18)):
+            yield clk.posedge
+            print("test 5: test short packet, length %d" % payload_len)
+            current_test.next = 5
+
+            test_frame = bytearray(range(payload_len))
+            fcs = zlib.crc32(bytes(test_frame)) & 0xffffffff
+            test_frame_fcs = test_frame + struct.pack('<L', fcs)
+
+            for wait in wait_normal, wait_pause_source, wait_pause_sink:
+                source_queue.put(test_frame_fcs)
+                yield clk.posedge
+                yield clk.posedge
+
+                yield wait()
+
+                yield clk.posedge
+                yield clk.posedge
+                yield clk.posedge
+
+                rx_frame = None
+                if not sink_queue.empty():
+                    rx_frame = sink_queue.get()
+
+                assert test_frame == bytearray(rx_frame)
+
+                assert sink_queue.empty()
+
+                yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, clkgen, check