diff --git a/fpga/common/rtl/cmac_gty_wrapper.v b/fpga/common/rtl/cmac_gty_wrapper.v index dbb339ec4..f6c14cb01 100644 --- a/fpga/common/rtl/cmac_gty_wrapper.v +++ b/fpga/common/rtl/cmac_gty_wrapper.v @@ -145,8 +145,6 @@ module cmac_gty_wrapper # output wire rx_axis_tlast, output wire [80+1-1:0] rx_axis_tuser, - output wire rx_ptp_clk, - output wire rx_ptp_rst, input wire [79:0] rx_ptp_time, input wire rx_enable, @@ -903,17 +901,6 @@ end assign rx_rst = rx_rst_reg_2; -assign rx_ptp_clk = gt_rxusrclk2[0]; - -sync_reset #( - .N(4) -) -sync_reset_rx_ptp_rst_inst ( - .clk(rx_ptp_clk), - .rst(gt_rx_reset_out[0] || rx_rst), - .out(rx_ptp_rst) -); - // serdes data // 80 bit mode - 64 bits in data, 8 bits each in ctrl0 and ctrl1 (per serdes) // widths match concatenated GTY ports (not all bits used) diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v index aec63f850..0b6b0e7ac 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v @@ -221,7 +221,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 512; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -708,8 +707,6 @@ wire qsfp0_rx_axis_tvalid_int; wire qsfp0_rx_axis_tlast_int; wire [80+1-1:0] qsfp0_rx_axis_tuser_int; -wire qsfp0_rx_ptp_clk_int; -wire qsfp0_rx_ptp_rst_int; wire [79:0] qsfp0_rx_ptp_time_int; wire qsfp0_drp_clk = clk_125mhz_int; @@ -842,8 +839,6 @@ qsfp0_cmac_inst ( .rx_axis_tlast(qsfp0_rx_axis_tlast_int), .rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp0_rx_ptp_rst_int), .rx_ptp_time(qsfp0_rx_ptp_time_int), .rx_enable(qsfp0_rx_enable), @@ -881,8 +876,6 @@ wire qsfp1_rx_axis_tvalid_int; wire qsfp1_rx_axis_tlast_int; wire [80+1-1:0] qsfp1_rx_axis_tuser_int; -wire qsfp1_rx_ptp_clk_int; -wire qsfp1_rx_ptp_rst_int; wire [79:0] qsfp1_rx_ptp_time_int; wire qsfp1_drp_clk = clk_125mhz_int; @@ -1015,8 +1008,6 @@ qsfp1_cmac_inst ( .rx_axis_tlast(qsfp1_rx_axis_tlast_int), .rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp1_rx_ptp_rst_int), .rx_ptp_time(qsfp1_rx_ptp_time_int), .rx_enable(qsfp1_rx_enable), @@ -1257,7 +1248,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -1525,8 +1515,6 @@ core_inst ( .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int), .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), .qsfp0_rx_enable(qsfp0_rx_enable), @@ -1578,8 +1566,6 @@ core_inst ( .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_enable(qsfp1_rx_enable), diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index a6d25c160..ed252a5c3 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -312,8 +311,6 @@ module fpga_core # input wire qsfp0_rx_axis_tlast, input wire [80+1-1:0] qsfp0_rx_axis_tuser, - input wire qsfp0_rx_ptp_clk, - input wire qsfp0_rx_ptp_rst, output wire [79:0] qsfp0_rx_ptp_time, output wire qsfp0_rx_enable, @@ -369,8 +366,6 @@ module fpga_core # input wire qsfp1_rx_axis_tlast, input wire [80+1-1:0] qsfp1_rx_axis_tuser, - input wire qsfp1_rx_ptp_clk, - input wire qsfp1_rx_ptp_rst, output wire [79:0] qsfp1_rx_ptp_time, output wire qsfp1_rx_enable, @@ -877,8 +872,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), - .mac_rx_ptp_clk({qsfp1_rx_ptp_clk, qsfp0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp1_rx_ptp_rst, qsfp0_rx_ptp_rst}), + .mac_rx_ptp_clk(2'b00), + .mac_rx_ptp_rst(2'b00), .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -980,7 +975,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index 72ca73a2b..b57188305 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index 2b4207b84..093c0c686 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,7 +689,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v index 77bb9f851..f4f6e6eba 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v @@ -248,7 +248,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -943,8 +942,6 @@ wire qsfp_0_rx_axis_tvalid_int; wire qsfp_0_rx_axis_tlast_int; wire [80+1-1:0] qsfp_0_rx_axis_tuser_int; -wire qsfp_0_rx_ptp_clk_int; -wire qsfp_0_rx_ptp_rst_int; wire [79:0] qsfp_0_rx_ptp_time_int; wire qsfp_0_drp_clk = clk_125mhz_int; @@ -1077,8 +1074,6 @@ qsfp_0_cmac_inst ( .rx_axis_tlast(qsfp_0_rx_axis_tlast_int), .rx_axis_tuser(qsfp_0_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_0_rx_ptp_rst_int), .rx_ptp_time(qsfp_0_rx_ptp_time_int), .rx_enable(qsfp_0_rx_enable), @@ -1116,8 +1111,6 @@ wire qsfp_1_rx_axis_tvalid_int; wire qsfp_1_rx_axis_tlast_int; wire [80+1-1:0] qsfp_1_rx_axis_tuser_int; -wire qsfp_1_rx_ptp_clk_int; -wire qsfp_1_rx_ptp_rst_int; wire [79:0] qsfp_1_rx_ptp_time_int; wire qsfp_1_drp_clk = clk_125mhz_int; @@ -1250,8 +1243,6 @@ qsfp_1_cmac_inst ( .rx_axis_tlast(qsfp_1_rx_axis_tlast_int), .rx_axis_tuser(qsfp_1_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_1_rx_ptp_rst_int), .rx_ptp_time(qsfp_1_rx_ptp_time_int), .rx_enable(qsfp_1_rx_enable), @@ -1617,7 +1608,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -1864,8 +1854,6 @@ core_inst ( .qsfp_0_rx_axis_tvalid(qsfp_0_rx_axis_tvalid_int), .qsfp_0_rx_axis_tlast(qsfp_0_rx_axis_tlast_int), .qsfp_0_rx_axis_tuser(qsfp_0_rx_axis_tuser_int), - .qsfp_0_rx_ptp_clk(qsfp_0_rx_ptp_clk_int), - .qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int), .qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int), .qsfp_0_rx_enable(qsfp_0_rx_enable), @@ -1915,8 +1903,6 @@ core_inst ( .qsfp_1_rx_axis_tvalid(qsfp_1_rx_axis_tvalid_int), .qsfp_1_rx_axis_tlast(qsfp_1_rx_axis_tlast_int), .qsfp_1_rx_axis_tuser(qsfp_1_rx_axis_tuser_int), - .qsfp_1_rx_ptp_clk(qsfp_1_rx_ptp_clk_int), - .qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int), .qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int), .qsfp_1_rx_enable(qsfp_1_rx_enable), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index 6916684c3..96b15dce4 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -291,8 +290,6 @@ module fpga_core # input wire qsfp_0_rx_axis_tlast, input wire [80+1-1:0] qsfp_0_rx_axis_tuser, - input wire qsfp_0_rx_ptp_clk, - input wire qsfp_0_rx_ptp_rst, output wire [79:0] qsfp_0_rx_ptp_time, output wire qsfp_0_rx_enable, @@ -346,8 +343,6 @@ module fpga_core # input wire qsfp_1_rx_axis_tlast, input wire [80+1-1:0] qsfp_1_rx_axis_tuser, - input wire qsfp_1_rx_ptp_clk, - input wire qsfp_1_rx_ptp_rst, output wire [79:0] qsfp_1_rx_ptp_time, output wire qsfp_1_rx_enable, @@ -967,8 +962,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp_1_rx_clk, qsfp_0_rx_clk}), .mac_rx_rst({qsfp_1_rx_rst, qsfp_0_rx_rst}), - .mac_rx_ptp_clk({qsfp_1_rx_ptp_clk, qsfp_0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp_1_rx_ptp_rst, qsfp_0_rx_ptp_rst}), + .mac_rx_ptp_clk(2'b00), + .mac_rx_ptp_rst(2'b00), .mac_rx_ptp_ts_96({qsfp_1_rx_ptp_time_int, qsfp_0_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -1070,7 +1065,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index 67b6abbfd..da4c9bb32 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 7a9f13d00..38dc2d30a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -692,7 +692,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index 0d2f8dbb6..5411ce059 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -282,7 +282,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -1123,8 +1122,6 @@ wire qsfp0_rx_axis_tvalid_int; wire qsfp0_rx_axis_tlast_int; wire [80+1-1:0] qsfp0_rx_axis_tuser_int; -wire qsfp0_rx_ptp_clk_int; -wire qsfp0_rx_ptp_rst_int; wire [79:0] qsfp0_rx_ptp_time_int; wire qsfp0_drp_clk = clk_125mhz_int; @@ -1259,8 +1256,6 @@ qsfp0_cmac_inst ( .rx_axis_tlast(qsfp0_rx_axis_tlast_int), .rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp0_rx_ptp_rst_int), .rx_ptp_time(qsfp0_rx_ptp_time_int), .rx_enable(qsfp0_rx_enable), @@ -1301,8 +1296,6 @@ wire qsfp1_rx_axis_tvalid_int; wire qsfp1_rx_axis_tlast_int; wire [80+1-1:0] qsfp1_rx_axis_tuser_int; -wire qsfp1_rx_ptp_clk_int; -wire qsfp1_rx_ptp_rst_int; wire [79:0] qsfp1_rx_ptp_time_int; wire qsfp1_drp_clk = clk_125mhz_int; @@ -1435,8 +1428,6 @@ qsfp1_cmac_inst ( .rx_axis_tlast(qsfp1_rx_axis_tlast_int), .rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp1_rx_ptp_rst_int), .rx_ptp_time(qsfp1_rx_ptp_time_int), .rx_enable(qsfp1_rx_enable), @@ -2046,7 +2037,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -2301,8 +2291,6 @@ core_inst ( .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int), .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), .qsfp0_rx_enable(qsfp0_rx_enable), @@ -2355,8 +2343,6 @@ core_inst ( .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_enable(qsfp1_rx_enable), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index facbcbf67..a06377c97 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -302,8 +301,6 @@ module fpga_core # input wire qsfp0_rx_axis_tlast, input wire [80+1-1:0] qsfp0_rx_axis_tuser, - input wire qsfp0_rx_ptp_clk, - input wire qsfp0_rx_ptp_rst, output wire [79:0] qsfp0_rx_ptp_time, output wire qsfp0_rx_enable, @@ -360,8 +357,6 @@ module fpga_core # input wire qsfp1_rx_axis_tlast, input wire [80+1-1:0] qsfp1_rx_axis_tuser, - input wire qsfp1_rx_ptp_clk, - input wire qsfp1_rx_ptp_rst, output wire [79:0] qsfp1_rx_ptp_time, output wire qsfp1_rx_enable, @@ -957,8 +952,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), - .mac_rx_ptp_clk({qsfp1_rx_ptp_clk, qsfp0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp1_rx_ptp_rst, qsfp0_rx_ptp_rst}), + .mac_rx_ptp_clk(2'b00), + .mac_rx_ptp_rst(2'b00), .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -1060,7 +1055,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index 6b3457a52..972993f64 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index 87569e0dc..613555323 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,7 +689,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v index 541fa618f..77b0d7047 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -235,7 +235,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -982,8 +981,6 @@ wire qsfp0_rx_axis_tvalid_int; wire qsfp0_rx_axis_tlast_int; wire [80+1-1:0] qsfp0_rx_axis_tuser_int; -wire qsfp0_rx_ptp_clk_int; -wire qsfp0_rx_ptp_rst_int; wire [79:0] qsfp0_rx_ptp_time_int; wire qsfp0_drp_clk = clk_125mhz_int; @@ -1118,8 +1115,6 @@ qsfp0_cmac_inst ( .rx_axis_tlast(qsfp0_rx_axis_tlast_int), .rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp0_rx_ptp_rst_int), .rx_ptp_time(qsfp0_rx_ptp_time_int), .rx_enable(qsfp0_rx_enable), @@ -1160,8 +1155,6 @@ wire qsfp1_rx_axis_tvalid_int; wire qsfp1_rx_axis_tlast_int; wire [80+1-1:0] qsfp1_rx_axis_tuser_int; -wire qsfp1_rx_ptp_clk_int; -wire qsfp1_rx_ptp_rst_int; wire [79:0] qsfp1_rx_ptp_time_int; wire qsfp1_drp_clk = clk_125mhz_int; @@ -1294,8 +1287,6 @@ qsfp1_cmac_inst ( .rx_axis_tlast(qsfp1_rx_axis_tlast_int), .rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp1_rx_ptp_rst_int), .rx_ptp_time(qsfp1_rx_ptp_time_int), .rx_enable(qsfp1_rx_enable), @@ -3144,7 +3135,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -3391,8 +3381,6 @@ core_inst ( .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int), .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), .qsfp0_rx_enable(qsfp0_rx_enable), @@ -3439,8 +3427,6 @@ core_inst ( .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_enable(qsfp1_rx_enable), diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index 2ac4f896e..e8aca3492 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 1, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -291,8 +290,6 @@ module fpga_core # input wire qsfp0_rx_axis_tlast, input wire [80+1-1:0] qsfp0_rx_axis_tuser, - input wire qsfp0_rx_ptp_clk, - input wire qsfp0_rx_ptp_rst, output wire [79:0] qsfp0_rx_ptp_time, output wire qsfp0_rx_enable, @@ -343,8 +340,6 @@ module fpga_core # input wire qsfp1_rx_axis_tlast, input wire [80+1-1:0] qsfp1_rx_axis_tuser, - input wire qsfp1_rx_ptp_clk, - input wire qsfp1_rx_ptp_rst, output wire [79:0] qsfp1_rx_ptp_time, output wire qsfp1_rx_enable, @@ -897,8 +892,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), - .mac_rx_ptp_clk({qsfp1_rx_ptp_clk, qsfp0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp1_rx_ptp_rst, qsfp0_rx_ptp_rst}), + .mac_rx_ptp_clk(2'b00), + .mac_rx_ptp_rst(2'b00), .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -1000,7 +995,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index 0bde67d54..f60a01ceb 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 1 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 1 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index c5dd0e429..7a50609ad 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -681,7 +681,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 1 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 1 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v index 07c951deb..43e206093 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v @@ -183,7 +183,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -926,8 +925,6 @@ wire qsfp_rx_axis_tvalid_int; wire qsfp_rx_axis_tlast_int; wire [80+1-1:0] qsfp_rx_axis_tuser_int; -wire qsfp_rx_ptp_clk_int; -wire qsfp_rx_ptp_rst_int; wire [79:0] qsfp_rx_ptp_time_int; wire qsfp_drp_clk = clk_125mhz_int; @@ -1062,8 +1059,6 @@ qsfp_cmac_inst ( .rx_axis_tlast(qsfp_rx_axis_tlast_int), .rx_axis_tuser(qsfp_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_rx_ptp_rst_int), .rx_ptp_time(qsfp_rx_ptp_time_int), .rx_enable(qsfp_rx_enable), @@ -2595,7 +2590,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -2841,8 +2835,6 @@ core_inst ( .qsfp_rx_axis_tvalid(qsfp_rx_axis_tvalid_int), .qsfp_rx_axis_tlast(qsfp_rx_axis_tlast_int), .qsfp_rx_axis_tuser(qsfp_rx_axis_tuser_int), - .qsfp_rx_ptp_clk(qsfp_rx_ptp_clk_int), - .qsfp_rx_ptp_rst(qsfp_rx_ptp_rst_int), .qsfp_rx_ptp_time(qsfp_rx_ptp_time_int), .qsfp_rx_enable(qsfp_rx_enable), diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index 183caed4d..59a75879a 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 1, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -290,8 +289,6 @@ module fpga_core # input wire qsfp_rx_axis_tlast, input wire [80+1-1:0] qsfp_rx_axis_tuser, - input wire qsfp_rx_ptp_clk, - input wire qsfp_rx_ptp_rst, output wire [79:0] qsfp_rx_ptp_time, output wire qsfp_rx_enable, @@ -749,8 +746,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp_rx_clk}), .mac_rx_rst({qsfp_rx_rst}), - .mac_rx_ptp_clk({qsfp_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp_rx_ptp_rst}), + .mac_rx_ptp_clk(1'b0), + .mac_rx_ptp_rst(1'b0), .mac_rx_ptp_ts_96({qsfp_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -852,7 +849,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index b55ebb732..ecc319484 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 1 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 1 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 7c3e426b7..8b7301e34 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -659,7 +659,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 1 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 1 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v index 6d4a15460..4603dab8b 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v @@ -265,7 +265,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -930,8 +929,6 @@ wire qsfp1_rx_axis_tvalid_int; wire qsfp1_rx_axis_tlast_int; wire [80+1-1:0] qsfp1_rx_axis_tuser_int; -wire qsfp1_rx_ptp_clk_int; -wire qsfp1_rx_ptp_rst_int; wire [79:0] qsfp1_rx_ptp_time_int; wire qsfp1_drp_clk = clk_125mhz_int; @@ -1064,8 +1061,6 @@ qsfp1_cmac_inst ( .rx_axis_tlast(qsfp1_rx_axis_tlast_int), .rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp1_rx_ptp_rst_int), .rx_ptp_time(qsfp1_rx_ptp_time_int), .rx_enable(qsfp1_rx_enable), @@ -1103,8 +1098,6 @@ wire qsfp2_rx_axis_tvalid_int; wire qsfp2_rx_axis_tlast_int; wire [80+1-1:0] qsfp2_rx_axis_tuser_int; -wire qsfp2_rx_ptp_clk_int; -wire qsfp2_rx_ptp_rst_int; wire [79:0] qsfp2_rx_ptp_time_int; wire qsfp2_drp_clk = clk_125mhz_int; @@ -1202,8 +1195,6 @@ qsfp2_cmac_inst ( .rx_axis_tlast(qsfp2_rx_axis_tlast_int), .rx_axis_tuser(qsfp2_rx_axis_tuser_int), - .rx_ptp_clk(qsfp2_rx_ptp_clk_int), - .rx_ptp_rst(qsfp2_rx_ptp_rst_int), .rx_ptp_time(qsfp2_rx_ptp_time_int), .rx_enable(qsfp2_rx_enable), @@ -1572,7 +1563,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -1834,8 +1824,6 @@ core_inst ( .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_enable(qsfp1_rx_enable), @@ -1888,8 +1876,6 @@ core_inst ( .qsfp2_rx_axis_tvalid(qsfp2_rx_axis_tvalid_int), .qsfp2_rx_axis_tlast(qsfp2_rx_axis_tlast_int), .qsfp2_rx_axis_tuser(qsfp2_rx_axis_tuser_int), - .qsfp2_rx_ptp_clk(qsfp2_rx_ptp_clk_int), - .qsfp2_rx_ptp_rst(qsfp2_rx_ptp_rst_int), .qsfp2_rx_ptp_time(qsfp2_rx_ptp_time_int), .qsfp2_rx_enable(qsfp2_rx_enable), diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index a86122bd4..8f17b1971 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -306,8 +305,6 @@ module fpga_core # input wire qsfp1_rx_axis_tlast, input wire [80+1-1:0] qsfp1_rx_axis_tuser, - input wire qsfp1_rx_ptp_clk, - input wire qsfp1_rx_ptp_rst, output wire [79:0] qsfp1_rx_ptp_time, output wire qsfp1_rx_enable, @@ -364,8 +361,6 @@ module fpga_core # input wire qsfp2_rx_axis_tlast, input wire [80+1-1:0] qsfp2_rx_axis_tuser, - input wire qsfp2_rx_ptp_clk, - input wire qsfp2_rx_ptp_rst, output wire [79:0] qsfp2_rx_ptp_time, input wire qsfp2_drp_clk, @@ -922,8 +917,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp2_rx_clk, qsfp1_rx_clk}), .mac_rx_rst({qsfp2_rx_rst, qsfp1_rx_rst}), - .mac_rx_ptp_clk({qsfp2_rx_ptp_clk, qsfp1_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp2_rx_ptp_rst, qsfp1_rx_ptp_rst}), + .mac_rx_ptp_clk(2'b00), + .mac_rx_ptp_rst(2'b00), .mac_rx_ptp_ts_96({qsfp2_rx_ptp_time_int, qsfp1_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -1025,7 +1020,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index c3d9b0680..da31ede71 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index c53099325..af5581be8 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -693,7 +693,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index ff66f43e8..40bd3d3fe 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -328,7 +328,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 512; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -1034,8 +1033,6 @@ wire qsfp0_rx_axis_tvalid_int; wire qsfp0_rx_axis_tlast_int; wire [80+1-1:0] qsfp0_rx_axis_tuser_int; -wire qsfp0_rx_ptp_clk_int; -wire qsfp0_rx_ptp_rst_int; wire [79:0] qsfp0_rx_ptp_time_int; wire qsfp0_drp_clk = clk_125mhz_int; @@ -1168,8 +1165,6 @@ qsfp0_cmac_inst ( .rx_axis_tlast(qsfp0_rx_axis_tlast_int), .rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp0_rx_ptp_rst_int), .rx_ptp_time(qsfp0_rx_ptp_time_int), .rx_enable(qsfp0_rx_enable), @@ -1207,8 +1202,6 @@ wire qsfp1_rx_axis_tvalid_int; wire qsfp1_rx_axis_tlast_int; wire [80+1-1:0] qsfp1_rx_axis_tuser_int; -wire qsfp1_rx_ptp_clk_int; -wire qsfp1_rx_ptp_rst_int; wire [79:0] qsfp1_rx_ptp_time_int; wire qsfp1_drp_clk = clk_125mhz_int; @@ -1341,8 +1334,6 @@ qsfp1_cmac_inst ( .rx_axis_tlast(qsfp1_rx_axis_tlast_int), .rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp1_rx_ptp_rst_int), .rx_ptp_time(qsfp1_rx_ptp_time_int), .rx_enable(qsfp1_rx_enable), @@ -1380,8 +1371,6 @@ wire qsfp2_rx_axis_tvalid_int; wire qsfp2_rx_axis_tlast_int; wire [80+1-1:0] qsfp2_rx_axis_tuser_int; -wire qsfp2_rx_ptp_clk_int; -wire qsfp2_rx_ptp_rst_int; wire [79:0] qsfp2_rx_ptp_time_int; wire qsfp2_drp_clk = clk_125mhz_int; @@ -1514,8 +1503,6 @@ qsfp2_cmac_inst ( .rx_axis_tlast(qsfp2_rx_axis_tlast_int), .rx_axis_tuser(qsfp2_rx_axis_tuser_int), - .rx_ptp_clk(qsfp2_rx_ptp_clk_int), - .rx_ptp_rst(qsfp2_rx_ptp_rst_int), .rx_ptp_time(qsfp2_rx_ptp_time_int), .rx_enable(qsfp2_rx_enable), @@ -1553,8 +1540,6 @@ wire qsfp3_rx_axis_tvalid_int; wire qsfp3_rx_axis_tlast_int; wire [80+1-1:0] qsfp3_rx_axis_tuser_int; -wire qsfp3_rx_ptp_clk_int; -wire qsfp3_rx_ptp_rst_int; wire [79:0] qsfp3_rx_ptp_time_int; wire qsfp3_drp_clk = clk_125mhz_int; @@ -1687,8 +1672,6 @@ qsfp3_cmac_inst ( .rx_axis_tlast(qsfp3_rx_axis_tlast_int), .rx_axis_tuser(qsfp3_rx_axis_tuser_int), - .rx_ptp_clk(qsfp3_rx_ptp_clk_int), - .rx_ptp_rst(qsfp3_rx_ptp_rst_int), .rx_ptp_time(qsfp3_rx_ptp_time_int), .rx_enable(qsfp3_rx_enable), @@ -2296,7 +2279,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -2552,8 +2534,6 @@ core_inst ( .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int), .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), .qsfp0_rx_enable(qsfp0_rx_enable), @@ -2612,8 +2592,6 @@ core_inst ( .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_enable(qsfp1_rx_enable), @@ -2672,8 +2650,6 @@ core_inst ( .qsfp2_rx_axis_tvalid(qsfp2_rx_axis_tvalid_int), .qsfp2_rx_axis_tlast(qsfp2_rx_axis_tlast_int), .qsfp2_rx_axis_tuser(qsfp2_rx_axis_tuser_int), - .qsfp2_rx_ptp_clk(qsfp2_rx_ptp_clk_int), - .qsfp2_rx_ptp_rst(qsfp2_rx_ptp_rst_int), .qsfp2_rx_ptp_time(qsfp2_rx_ptp_time_int), .qsfp2_rx_enable(qsfp2_rx_enable), @@ -2732,8 +2708,6 @@ core_inst ( .qsfp3_rx_axis_tvalid(qsfp3_rx_axis_tvalid_int), .qsfp3_rx_axis_tlast(qsfp3_rx_axis_tlast_int), .qsfp3_rx_axis_tuser(qsfp3_rx_axis_tuser_int), - .qsfp3_rx_ptp_clk(qsfp3_rx_ptp_clk_int), - .qsfp3_rx_ptp_rst(qsfp3_rx_ptp_rst_int), .qsfp3_rx_ptp_time(qsfp3_rx_ptp_time_int), .qsfp3_rx_enable(qsfp3_rx_enable), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index 77edb706e..164187e9c 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -300,8 +299,6 @@ module fpga_core # input wire qsfp0_rx_axis_tlast, input wire [80+1-1:0] qsfp0_rx_axis_tuser, - input wire qsfp0_rx_ptp_clk, - input wire qsfp0_rx_ptp_rst, output wire [79:0] qsfp0_rx_ptp_time, output wire qsfp0_rx_enable, @@ -364,8 +361,6 @@ module fpga_core # input wire qsfp1_rx_axis_tlast, input wire [80+1-1:0] qsfp1_rx_axis_tuser, - input wire qsfp1_rx_ptp_clk, - input wire qsfp1_rx_ptp_rst, output wire [79:0] qsfp1_rx_ptp_time, output wire qsfp1_rx_enable, @@ -428,8 +423,6 @@ module fpga_core # input wire qsfp2_rx_axis_tlast, input wire [80+1-1:0] qsfp2_rx_axis_tuser, - input wire qsfp2_rx_ptp_clk, - input wire qsfp2_rx_ptp_rst, output wire [79:0] qsfp2_rx_ptp_time, output wire qsfp2_rx_enable, @@ -492,8 +485,6 @@ module fpga_core # input wire qsfp3_rx_axis_tlast, input wire [80+1-1:0] qsfp3_rx_axis_tuser, - input wire qsfp3_rx_ptp_clk, - input wire qsfp3_rx_ptp_rst, output wire [79:0] qsfp3_rx_ptp_time, output wire qsfp3_rx_enable, @@ -1277,8 +1268,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp3_rx_clk, qsfp2_rx_clk, qsfp1_rx_clk, qsfp0_rx_clk}), .mac_rx_rst({qsfp3_rx_rst, qsfp2_rx_rst, qsfp1_rx_rst, qsfp0_rx_rst}), - .mac_rx_ptp_clk({qsfp3_rx_ptp_clk, qsfp2_rx_ptp_clk, qsfp1_rx_ptp_clk, qsfp0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp3_rx_ptp_rst, qsfp2_rx_ptp_rst, qsfp1_rx_ptp_rst, qsfp0_rx_ptp_rst}), + .mac_rx_ptp_clk(4'b0000), + .mac_rx_ptp_rst(4'b0000), .mac_rx_ptp_ts_96({qsfp3_rx_ptp_time_int, qsfp2_rx_ptp_time_int, qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -1380,7 +1371,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index 334ffb4de..c37a5c157 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index 67b3e98db..2e8bd1140 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,7 +689,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index 97c26cbe6..fa08d12f8 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -294,7 +294,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -977,8 +976,6 @@ wire qsfp_0_rx_axis_tvalid_int; wire qsfp_0_rx_axis_tlast_int; wire [80+1-1:0] qsfp_0_rx_axis_tuser_int; -wire qsfp_0_rx_ptp_clk_int; -wire qsfp_0_rx_ptp_rst_int; wire [79:0] qsfp_0_rx_ptp_time_int; wire qsfp_0_drp_clk = clk_125mhz_int; @@ -1111,8 +1108,6 @@ qsfp_0_cmac_inst ( .rx_axis_tlast(qsfp_0_rx_axis_tlast_int), .rx_axis_tuser(qsfp_0_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_0_rx_ptp_rst_int), .rx_ptp_time(qsfp_0_rx_ptp_time_int), .rx_enable(qsfp_0_rx_enable), @@ -1150,8 +1145,6 @@ wire qsfp_1_rx_axis_tvalid_int; wire qsfp_1_rx_axis_tlast_int; wire [80+1-1:0] qsfp_1_rx_axis_tuser_int; -wire qsfp_1_rx_ptp_clk_int; -wire qsfp_1_rx_ptp_rst_int; wire [79:0] qsfp_1_rx_ptp_time_int; wire qsfp_1_drp_clk = clk_125mhz_int; @@ -1284,8 +1277,6 @@ qsfp_1_cmac_inst ( .rx_axis_tlast(qsfp_1_rx_axis_tlast_int), .rx_axis_tuser(qsfp_1_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_1_rx_ptp_rst_int), .rx_ptp_time(qsfp_1_rx_ptp_time_int), .rx_enable(qsfp_1_rx_enable), @@ -1937,7 +1928,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -2197,8 +2187,6 @@ core_inst ( .qsfp_0_rx_axis_tvalid(qsfp_0_rx_axis_tvalid_int), .qsfp_0_rx_axis_tlast(qsfp_0_rx_axis_tlast_int), .qsfp_0_rx_axis_tuser(qsfp_0_rx_axis_tuser_int), - .qsfp_0_rx_ptp_clk(qsfp_0_rx_ptp_clk_int), - .qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int), .qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int), .qsfp_0_rx_enable(qsfp_0_rx_enable), @@ -2257,8 +2245,6 @@ core_inst ( .qsfp_1_rx_axis_tvalid(qsfp_1_rx_axis_tvalid_int), .qsfp_1_rx_axis_tlast(qsfp_1_rx_axis_tlast_int), .qsfp_1_rx_axis_tuser(qsfp_1_rx_axis_tuser_int), - .qsfp_1_rx_ptp_clk(qsfp_1_rx_ptp_clk_int), - .qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int), .qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int), .qsfp_1_rx_enable(qsfp_1_rx_enable), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 61212b113..647c268d2 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -304,8 +303,6 @@ module fpga_core # input wire qsfp_0_rx_axis_tlast, input wire [80+1-1:0] qsfp_0_rx_axis_tuser, - input wire qsfp_0_rx_ptp_clk, - input wire qsfp_0_rx_ptp_rst, output wire [79:0] qsfp_0_rx_ptp_time, output wire qsfp_0_rx_enable, @@ -367,8 +364,6 @@ module fpga_core # input wire qsfp_1_rx_axis_tlast, input wire [80+1-1:0] qsfp_1_rx_axis_tuser, - input wire qsfp_1_rx_ptp_clk, - input wire qsfp_1_rx_ptp_rst, output wire [79:0] qsfp_1_rx_ptp_time, output wire qsfp_1_rx_enable, @@ -979,8 +974,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp_1_rx_clk, qsfp_0_rx_clk}), .mac_rx_rst({qsfp_1_rx_rst, qsfp_0_rx_rst}), - .mac_rx_ptp_clk({qsfp_1_rx_ptp_clk, qsfp_0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp_1_rx_ptp_rst, qsfp_0_rx_ptp_rst}), + .mac_rx_ptp_clk(2'b00), + .mac_rx_ptp_rst(2'b00), .mac_rx_ptp_ts_96({qsfp_1_rx_ptp_time_int, qsfp_0_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -1082,7 +1077,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index 848083937..389f05eec 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index b051cafb0..7ac2e051e 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -690,7 +690,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v index 3be5e9b8a..a80ec0bd6 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v @@ -311,7 +311,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; @@ -955,8 +954,6 @@ wire qsfp_0_rx_axis_tvalid_int; wire qsfp_0_rx_axis_tlast_int; wire [80+1-1:0] qsfp_0_rx_axis_tuser_int; -wire qsfp_0_rx_ptp_clk_int; -wire qsfp_0_rx_ptp_rst_int; wire [79:0] qsfp_0_rx_ptp_time_int; wire qsfp_0_drp_clk = clk_125mhz_int; @@ -1097,8 +1094,6 @@ qsfp_0_cmac_inst ( .rx_axis_tlast(qsfp_0_rx_axis_tlast_int), .rx_axis_tuser(qsfp_0_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_0_rx_ptp_rst_int), .rx_ptp_time(qsfp_0_rx_ptp_time_int), .rx_enable(qsfp_0_rx_enable), @@ -1136,8 +1131,6 @@ wire qsfp_1_rx_axis_tvalid_int; wire qsfp_1_rx_axis_tlast_int; wire [80+1-1:0] qsfp_1_rx_axis_tuser_int; -wire qsfp_1_rx_ptp_clk_int; -wire qsfp_1_rx_ptp_rst_int; wire [79:0] qsfp_1_rx_ptp_time_int; wire qsfp_1_drp_clk = clk_125mhz_int; @@ -1278,8 +1271,6 @@ qsfp_1_cmac_inst ( .rx_axis_tlast(qsfp_1_rx_axis_tlast_int), .rx_axis_tuser(qsfp_1_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_1_rx_ptp_rst_int), .rx_ptp_time(qsfp_1_rx_ptp_time_int), .rx_enable(qsfp_1_rx_enable), @@ -1317,8 +1308,6 @@ wire qsfp_2_rx_axis_tvalid_int; wire qsfp_2_rx_axis_tlast_int; wire [80+1-1:0] qsfp_2_rx_axis_tuser_int; -wire qsfp_2_rx_ptp_clk_int; -wire qsfp_2_rx_ptp_rst_int; wire [79:0] qsfp_2_rx_ptp_time_int; wire qsfp_2_drp_clk = clk_125mhz_int; @@ -1459,8 +1448,6 @@ qsfp_2_cmac_inst ( .rx_axis_tlast(qsfp_2_rx_axis_tlast_int), .rx_axis_tuser(qsfp_2_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_2_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_2_rx_ptp_rst_int), .rx_ptp_time(qsfp_2_rx_ptp_time_int), .rx_enable(qsfp_2_rx_enable), @@ -1498,8 +1485,6 @@ wire qsfp_3_rx_axis_tvalid_int; wire qsfp_3_rx_axis_tlast_int; wire [80+1-1:0] qsfp_3_rx_axis_tuser_int; -wire qsfp_3_rx_ptp_clk_int; -wire qsfp_3_rx_ptp_rst_int; wire [79:0] qsfp_3_rx_ptp_time_int; wire qsfp_3_drp_clk = clk_125mhz_int; @@ -1640,8 +1625,6 @@ qsfp_3_cmac_inst ( .rx_axis_tlast(qsfp_3_rx_axis_tlast_int), .rx_axis_tuser(qsfp_3_rx_axis_tuser_int), - .rx_ptp_clk(qsfp_3_rx_ptp_clk_int), - .rx_ptp_rst(qsfp_3_rx_ptp_rst_int), .rx_ptp_time(qsfp_3_rx_ptp_time_int), .rx_enable(qsfp_3_rx_enable), @@ -2183,7 +2166,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -2441,8 +2423,6 @@ core_inst ( .qsfp_0_rx_axis_tvalid(qsfp_0_rx_axis_tvalid_int), .qsfp_0_rx_axis_tlast(qsfp_0_rx_axis_tlast_int), .qsfp_0_rx_axis_tuser(qsfp_0_rx_axis_tuser_int), - .qsfp_0_rx_ptp_clk(qsfp_0_rx_ptp_clk_int), - .qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int), .qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int), .qsfp_0_rx_enable(qsfp_0_rx_enable), @@ -2501,8 +2481,6 @@ core_inst ( .qsfp_1_rx_axis_tvalid(qsfp_1_rx_axis_tvalid_int), .qsfp_1_rx_axis_tlast(qsfp_1_rx_axis_tlast_int), .qsfp_1_rx_axis_tuser(qsfp_1_rx_axis_tuser_int), - .qsfp_1_rx_ptp_clk(qsfp_1_rx_ptp_clk_int), - .qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int), .qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int), .qsfp_1_rx_enable(qsfp_1_rx_enable), @@ -2561,8 +2539,6 @@ core_inst ( .qsfp_2_rx_axis_tvalid(qsfp_2_rx_axis_tvalid_int), .qsfp_2_rx_axis_tlast(qsfp_2_rx_axis_tlast_int), .qsfp_2_rx_axis_tuser(qsfp_2_rx_axis_tuser_int), - .qsfp_2_rx_ptp_clk(qsfp_2_rx_ptp_clk_int), - .qsfp_2_rx_ptp_rst(qsfp_2_rx_ptp_rst_int), .qsfp_2_rx_ptp_time(qsfp_2_rx_ptp_time_int), .qsfp_2_rx_enable(qsfp_2_rx_enable), @@ -2621,8 +2597,6 @@ core_inst ( .qsfp_3_rx_axis_tvalid(qsfp_3_rx_axis_tvalid_int), .qsfp_3_rx_axis_tlast(qsfp_3_rx_axis_tlast_int), .qsfp_3_rx_axis_tuser(qsfp_3_rx_axis_tuser_int), - .qsfp_3_rx_ptp_clk(qsfp_3_rx_ptp_clk_int), - .qsfp_3_rx_ptp_rst(qsfp_3_rx_ptp_rst_int), .qsfp_3_rx_ptp_time(qsfp_3_rx_ptp_time_int), .qsfp_3_rx_enable(qsfp_3_rx_enable), diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v index e1c8e949a..3170cf53a 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -302,8 +301,6 @@ module fpga_core # input wire qsfp_0_rx_axis_tlast, input wire [80+1-1:0] qsfp_0_rx_axis_tuser, - input wire qsfp_0_rx_ptp_clk, - input wire qsfp_0_rx_ptp_rst, output wire [79:0] qsfp_0_rx_ptp_time, output wire qsfp_0_rx_enable, @@ -365,8 +362,6 @@ module fpga_core # input wire qsfp_1_rx_axis_tlast, input wire [80+1-1:0] qsfp_1_rx_axis_tuser, - input wire qsfp_1_rx_ptp_clk, - input wire qsfp_1_rx_ptp_rst, output wire [79:0] qsfp_1_rx_ptp_time, output wire qsfp_1_rx_enable, @@ -428,8 +423,6 @@ module fpga_core # input wire qsfp_2_rx_axis_tlast, input wire [80+1-1:0] qsfp_2_rx_axis_tuser, - input wire qsfp_2_rx_ptp_clk, - input wire qsfp_2_rx_ptp_rst, output wire [79:0] qsfp_2_rx_ptp_time, output wire qsfp_2_rx_enable, @@ -491,8 +484,6 @@ module fpga_core # input wire qsfp_3_rx_axis_tlast, input wire [80+1-1:0] qsfp_3_rx_axis_tuser, - input wire qsfp_3_rx_ptp_clk, - input wire qsfp_3_rx_ptp_rst, output wire [79:0] qsfp_3_rx_ptp_time, output wire qsfp_3_rx_enable, @@ -1244,8 +1235,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk({qsfp_3_rx_clk, qsfp_2_rx_clk, qsfp_1_rx_clk, qsfp_0_rx_clk}), .mac_rx_rst({qsfp_3_rx_rst, qsfp_2_rx_rst, qsfp_1_rx_rst, qsfp_0_rx_rst}), - .mac_rx_ptp_clk({qsfp_3_rx_ptp_clk, qsfp_2_rx_ptp_clk, qsfp_1_rx_ptp_clk, qsfp_0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp_3_rx_ptp_rst, qsfp_2_rx_ptp_rst, qsfp_1_rx_ptp_rst, qsfp_0_rx_ptp_rst}), + .mac_rx_ptp_clk(4'b0000), + .mac_rx_ptp_rst(4'b0000), .mac_rx_ptp_ts_96({qsfp_3_rx_ptp_time_int, qsfp_2_rx_ptp_time_int, qsfp_1_rx_ptp_time_int, qsfp_0_rx_ptp_time_int}), .mac_rx_ptp_ts_step(), @@ -1347,7 +1338,7 @@ mqnic_core_pcie_us #( .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile index 38c2e9ce0..413c209cb 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile @@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py index d850fa496..c3d0f5999 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -685,7 +685,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1