From d7904b8007256d4020845f21c0e29eb22323795a Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 4 Sep 2022 15:24:40 -0700 Subject: [PATCH] fpga: Add support for IRQ rate limiting Signed-off-by: Alex Forencich --- docs/source/rb/index.rst | 1 + .../dma_bench/tb/mqnic_core_pcie_us/Makefile | 1 + .../test_mqnic_core_pcie_us.py | 1 + .../template/tb/mqnic_core_pcie_us/Makefile | 1 + .../test_mqnic_core_pcie_us.py | 1 + fpga/common/rtl/mqnic_core.v | 85 ++++++++++++++----- fpga/common/tb/mqnic_core_axi/Makefile | 1 + .../tb/mqnic_core_axi/test_mqnic_core_axi.py | 1 + fpga/common/tb/mqnic_core_pcie_ptile/Makefile | 1 + .../test_mqnic_core_pcie_ptile.py | 1 + fpga/common/tb/mqnic_core_pcie_s10/Makefile | 1 + .../test_mqnic_core_pcie_s10.py | 1 + fpga/common/tb/mqnic_core_pcie_us/Makefile | 1 + .../test_mqnic_core_pcie_us.py | 1 + .../tb/mqnic_core_pcie_us_tdma/Makefile | 1 + .../test_mqnic_core_pcie_us.py | 1 + fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile | 1 + .../250_SoC/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile | 1 + .../250_SoC/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + .../ADM_PCIE_9V3/fpga_100g/fpga/Makefile | 1 + .../ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile | 1 + .../fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + .../mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 1 + .../ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile | 1 + .../ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile | 1 + .../fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/AU200/fpga_100g/fpga/Makefile | 1 + .../AU200/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/AU200/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile | 1 + .../AU200/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/AU250/fpga_100g/fpga/Makefile | 1 + .../AU250/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/AU250/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile | 1 + .../AU250/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/AU280/fpga_100g/fpga/Makefile | 1 + .../AU280/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/AU280/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile | 1 + .../AU280/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/AU50/fpga_100g/fpga/Makefile | 1 + .../AU50/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/AU50/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile | 1 + .../mqnic/AU50/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + .../DE10_Agilex/fpga_100g/fpga_24AR0/Makefile | 1 + .../DE10_Agilex/fpga_100g/fpga_24B/Makefile | 1 + .../fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + .../fpga_25g/fpga_10g_24AR0/Makefile | 1 + .../fpga_25g/fpga_10g_24B/Makefile | 1 + .../DE10_Agilex/fpga_25g/fpga_24AR0/Makefile | 1 + .../DE10_Agilex/fpga_25g/fpga_24B/Makefile | 1 + .../fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + .../fpga/fpga_ku040/Makefile | 1 + .../fpga/fpga_ku060/Makefile | 1 + .../fpga/tb/fpga_core/Makefile | 1 + .../fpga/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile | 1 + .../NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 1 + .../fpga/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile | 1 + .../Nexus_K35_S/fpga/tb/fpga_core/Makefile | 1 + .../fpga/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile | 1 + .../Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile | 1 + .../Nexus_K3P_S/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile | 1 + .../mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile | 1 + .../S10DX_DK/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + .../fpga_25g/fpga_10g_1sm21b/Makefile | 1 + .../fpga_25g/fpga_10g_1sm21c/Makefile | 1 + .../S10MX_DK/fpga_25g/fpga_1sm21b/Makefile | 1 + .../S10MX_DK/fpga_25g/fpga_1sm21c/Makefile | 1 + .../S10MX_DK/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/VCU108/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile | 1 + .../VCU108/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/VCU118/fpga_100g/fpga/Makefile | 1 + .../VCU118/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/VCU118/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile | 1 + .../VCU118/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile | 1 + .../VCU1525/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile | 1 + .../VCU1525/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile | 1 + .../XUPP3R/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile | 1 + .../XUPP3R/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/ZCU102/fpga/fpga/Makefile | 1 + fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile | 1 + .../fpga/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile | 1 + .../ZCU106/fpga_pcie/tb/fpga_core/Makefile | 1 + .../fpga_pcie/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile | 1 + .../ZCU106/fpga_zynqmp/tb/fpga_core/Makefile | 1 + .../tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile | 1 + .../fpga_100g/fpga_app_dma_bench/Makefile | 1 + .../fpga_100g/fpga_app_template/Makefile | 1 + fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile | 1 + .../fb2CG/fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile | 1 + fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile | 1 + fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile | 1 + .../fb2CG/fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + 143 files changed, 207 insertions(+), 20 deletions(-) diff --git a/docs/source/rb/index.rst b/docs/source/rb/index.rst index 03d886152..9871c2581 100644 --- a/docs/source/rb/index.rst +++ b/docs/source/rb/index.rst @@ -69,6 +69,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea 0x0000C004 0x00000300 :ref:`rb_sched_block` 0x0000C005 0x00000200 application 0x0000C006 0x00000100 stats + 0x0000C007 0x00000100 IRQ config 0x0000C010 0x00000100 :ref:`rb_cqm_event` 0x0000C020 0x00000100 :ref:`rb_qm_tx` 0x0000C021 0x00000100 :ref:`rb_qm_rx` diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index 41f47cfaa..021d6eb57 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index f22c9e76f..41d3a06d6 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -930,6 +930,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index dcab5f92a..4e76bdc26 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -110,6 +110,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index f4272300f..5e3ad45dd 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -770,6 +770,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index edbc26df9..62d57725d 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -458,6 +458,8 @@ parameter AXIS_IF_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH; parameter AXIS_IF_TX_USER_WIDTH = AXIS_TX_USER_WIDTH; parameter AXIS_IF_RX_USER_WIDTH = AXIS_RX_USER_WIDTH; +localparam CLK_CYCLES_PER_US = (1000*CLK_PERIOD_NS_DENOM)/CLK_PERIOD_NS_NUM; + localparam PHC_RB_BASE_ADDR = 32'h100; // check configuration @@ -600,6 +602,8 @@ reg ctrl_reg_wr_ack_reg = 1'b0; reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; reg ctrl_reg_rd_ack_reg = 1'b0; +reg [15:0] irq_rate_limit_min_interval_reg = 10; + assign ctrl_reg_wr_wait_int = ctrl_reg_wr_wait | ptp_ctrl_reg_wr_wait; assign ctrl_reg_wr_ack_int = ctrl_reg_wr_ack | ctrl_reg_wr_ack_reg | ptp_ctrl_reg_wr_ack; assign ctrl_reg_rd_data_int = ctrl_reg_rd_data | ctrl_reg_rd_data_reg | ptp_ctrl_reg_rd_data; @@ -614,9 +618,11 @@ always @(posedge clk) begin if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin // write operation ctrl_reg_wr_ack_reg <= 1'b0; - // case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // default: ctrl_reg_wr_ack_reg <= 1'b0; - // endcase + case ({ctrl_reg_wr_addr >> 2, 2'b00}) + // IRQ configuration + 8'h4C: irq_rate_limit_min_interval_reg <= ctrl_reg_wr_data; // IRQ config: Min interval + default: ctrl_reg_wr_ack_reg <= 1'b0; + endcase end if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin @@ -635,19 +641,24 @@ always @(posedge clk) begin 8'h20: ctrl_reg_rd_data_reg <= BUILD_DATE; // FW ID: Build date 8'h24: ctrl_reg_rd_data_reg <= GIT_HASH; // FW ID: Git commit hash 8'h28: ctrl_reg_rd_data_reg <= RELEASE_INFO; // FW ID: Release info + // IRQ configuration + 8'h40: ctrl_reg_rd_data_reg <= 32'h0000C007; // IRQ config: Type + 8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // IRQ config: Version + 8'h48: ctrl_reg_rd_data_reg <= 32'h50; // IRQ config: Next header + 8'h4C: ctrl_reg_rd_data_reg <= irq_rate_limit_min_interval_reg; // IRQ config: Min interval // Interface - 8'h40: ctrl_reg_rd_data_reg <= 32'h0000C000; // Interface: Type - 8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // Interface: Version - 8'h48: ctrl_reg_rd_data_reg <= 32'h60; // Interface: Next header - 8'h4C: ctrl_reg_rd_data_reg <= 32'h0; // Interface: Offset - 8'h50: ctrl_reg_rd_data_reg <= IF_COUNT; // Interface: Count - 8'h54: ctrl_reg_rd_data_reg <= 2**AXIL_IF_CTRL_ADDR_WIDTH; // Interface: Stride - 8'h58: ctrl_reg_rd_data_reg <= 2**AXIL_CSR_ADDR_WIDTH; // Interface: CSR offset + 8'h50: ctrl_reg_rd_data_reg <= 32'h0000C000; // Interface: Type + 8'h54: ctrl_reg_rd_data_reg <= 32'h00000100; // Interface: Version + 8'h58: ctrl_reg_rd_data_reg <= 32'h70; // Interface: Next header + 8'h5C: ctrl_reg_rd_data_reg <= 32'h0; // Interface: Offset + 8'h60: ctrl_reg_rd_data_reg <= IF_COUNT; // Interface: Count + 8'h64: ctrl_reg_rd_data_reg <= 2**AXIL_IF_CTRL_ADDR_WIDTH; // Interface: Stride + 8'h68: ctrl_reg_rd_data_reg <= 2**AXIL_CSR_ADDR_WIDTH; // Interface: CSR offset // App info - 8'h60: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h0000C005 : 0; // App info: Type - 8'h64: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h00000200 : 0; // App info: Version - 8'h68: ctrl_reg_rd_data_reg <= 32'h80; // App info: Next header - 8'h6C: ctrl_reg_rd_data_reg <= APP_ENABLE ? APP_ID : 0; // App info: ID + 8'h70: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h0000C005 : 0; // App info: Type + 8'h74: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h00000200 : 0; // App info: Version + 8'h78: ctrl_reg_rd_data_reg <= 32'h80; // App info: Next header + 8'h7C: ctrl_reg_rd_data_reg <= APP_ENABLE ? APP_ID : 0; // App info: ID // Stats 8'h80: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h0000C006 : 0; // Stats: Type 8'h84: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h00000100 : 0; // Stats: Version @@ -663,6 +674,8 @@ always @(posedge clk) begin if (rst) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_ack_reg <= 1'b0; + + irq_rate_limit_min_interval_reg <= 10; end end @@ -2127,6 +2140,38 @@ end endgenerate +wire [IRQ_INDEX_WIDTH-1:0] int_irq_index; +wire int_irq_valid; +wire int_irq_ready; + +irq_rate_limit #( + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH) +) +irq_rate_limit_inst ( + .clk(clk), + .rst(rst), + + /* + * Interrupt request input + */ + .in_irq_index(int_irq_index), + .in_irq_valid(int_irq_valid), + .in_irq_ready(int_irq_ready), + + /* + * Interrupt request output + */ + .out_irq_index(irq_index), + .out_irq_valid(irq_valid), + .out_irq_ready(irq_ready), + + /* + * Configuration + */ + .prescale(CLK_CYCLES_PER_US-1), + .min_interval(irq_rate_limit_min_interval_reg) +); + wire [IF_COUNT*IRQ_INDEX_WIDTH-1:0] if_irq_index; wire [IF_COUNT-1:0] if_irq_valid; wire [IF_COUNT-1:0] if_irq_ready; @@ -2165,10 +2210,10 @@ if (IF_COUNT > 1) begin : irq_mux /* * AXI Stream output */ - .m_axis_tdata(irq_index), + .m_axis_tdata(int_irq_index), .m_axis_tkeep(), - .m_axis_tvalid(irq_valid), - .m_axis_tready(irq_ready), + .m_axis_tvalid(int_irq_valid), + .m_axis_tready(int_irq_ready), .m_axis_tlast(), .m_axis_tid(), .m_axis_tdest(), @@ -2177,9 +2222,9 @@ if (IF_COUNT > 1) begin : irq_mux end else begin - assign irq_index = if_irq_index; - assign irq_valid = if_irq_valid; - assign if_irq_ready = irq_ready; + assign int_irq_index = if_irq_index; + assign int_irq_valid = if_irq_valid; + assign if_irq_ready = int_irq_ready; end diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index 2ab6c0cbb..5e8b3d24e 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -100,6 +100,7 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_wr.v diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index f83e0c110..376db0e3f 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -532,6 +532,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_axi.v"), os.path.join(pcie_rtl_dir, "dma_if_axi_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_axi_wr.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index d67e9cc79..2c24f22ef 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -110,6 +110,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index e65dde19f..aaf8cc504 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -742,6 +742,7 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index 5e0dddf25..d82196046 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -110,6 +110,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 0a3cac2de..aba3aa62d 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -690,6 +690,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index 49ad787ec..90a218ac9 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -108,6 +108,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 38de1e240..9613e1171 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -762,6 +762,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 32e3f7b0f..348964d40 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -110,6 +110,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index edbca35bf..3ec1b5727 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -817,6 +817,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile index 3e94c252b..940aae536 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile @@ -83,6 +83,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index 5fb791757..0af5692fb 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index 74b2bd213..0645297d6 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,6 +689,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile index c24b2e420..b6200a0c0 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile index c24b2e420..b6200a0c0 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index 68072b9ac..2f22618d1 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index cc6b76e83..6cd4aca54 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -756,6 +756,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index 5c7df84ae..c9a01f61b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -84,6 +84,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index d68deaa64..40ede8699 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -86,6 +86,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index e5852da44..ec086db3b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index e736d7771..567b351a7 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,6 +689,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 26a4b0f33..e2be57e70 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index 26a4b0f33..e2be57e70 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index 6c424b71a..0871281c9 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -103,6 +103,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index 30ca622f1..c6be61fca 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index a59cda0f9..d56636995 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -756,6 +756,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile index 0eb4c9b9f..8c627182b 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile @@ -87,6 +87,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index 2a60d9d0d..fc5078e61 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index 8f81405f5..29403148f 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,6 +689,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile index 1d3f870ab..4989842a9 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile @@ -105,6 +105,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile index 1d3f870ab..4989842a9 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile @@ -105,6 +105,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index 2d0efaf0c..240acf838 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index 4bf49efbb..0fffef2e9 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -756,6 +756,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile index 5b044a26f..e24846446 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile @@ -87,6 +87,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index 2a60d9d0d..fc5078e61 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index 8f81405f5..29403148f 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,6 +689,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile index a54dcd880..4365b3707 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile @@ -105,6 +105,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile index a54dcd880..4365b3707 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile @@ -105,6 +105,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile index 2d0efaf0c..240acf838 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py index 4bf49efbb..0fffef2e9 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -756,6 +756,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index f83617485..fedb334f5 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -86,6 +86,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index 1a1a48795..b0d2dce6c 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 1d1068c89..1b10d7b46 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -678,6 +678,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile index 06b9c16c4..bb5bfa142 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile @@ -104,6 +104,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile index 06b9c16c4..bb5bfa142 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile @@ -104,6 +104,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index 51ffb00a9..69f99a36e 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index c525d19fa..8c29ef418 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -745,6 +745,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index 12343f59b..edc4c334a 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -86,6 +86,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index 046ed756b..e45407a3d 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 93a785510..1c31e4d4e 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -638,6 +638,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile index 2a7a5ecb8..f3f113c17 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile @@ -104,6 +104,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile index 2a7a5ecb8..f3f113c17 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile @@ -104,6 +104,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index bbc385195..78adf604a 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index c719202e1..ad33400b5 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -665,6 +665,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile index 882c1eef1..ba8289561 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile @@ -91,6 +91,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile index 0bb1647ca..9b313537f 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/Makefile @@ -91,6 +91,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile index 332749ae3..94eb03b0d 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile @@ -120,6 +120,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index 271c27c76..9a7460bc2 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -715,6 +715,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile index 3cebc6a36..a0edcc3e5 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile @@ -91,6 +91,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile index 611e709f4..28599dca5 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/Makefile @@ -91,6 +91,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile index a52a91249..21eb694c2 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile @@ -91,6 +91,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile index 25e703238..fd0a2cd69 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/Makefile @@ -91,6 +91,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile index 78424a40a..647d6f701 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile @@ -120,6 +120,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py index b69624dce..426c78c87 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -1035,6 +1035,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile index c57f4be34..69fc05d9d 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile index ad7b182a3..3a334eb71 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index e5c462886..dad23a675 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index 96194eae9..a04f048d4 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -720,6 +720,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile index fdf639fd9..066014375 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile @@ -100,6 +100,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 700a984c8..f2ace3706 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -118,6 +118,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index 642ba979f..a5ade26e7 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -642,6 +642,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile index 0cebef3a0..9b99b7915 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile index f63c03e03..bf4338d83 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py index a20d1d169..b3751f1f0 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py @@ -631,6 +631,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile index f7beba9ae..b9fefc250 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile index f7beba9ae..b9fefc250 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index 80316b466..003484aef 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index 85fa84eef..bf9e7ea6e 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -760,6 +760,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile index f7beba9ae..b9fefc250 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile index f7beba9ae..b9fefc250 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index 80316b466..003484aef 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index a1241e8ca..44c17c781 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -660,6 +660,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile index 34357a8ce..837b14b37 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile @@ -90,6 +90,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile index 667d7b1d0..f08135788 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile @@ -90,6 +90,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile index cb50bfecc..6ed4fe546 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile @@ -117,6 +117,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index acc71c78a..1becc1e87 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -825,6 +825,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile index 446f9de5c..ef889575e 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile index 326f541fc..1f136390a 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile index bbb6f9e20..07f8877fe 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile index f306c065e..1f592b89a 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile index 3e55b3910..9994f094d 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile @@ -120,6 +120,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index 347956445..225e4f7cd 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -667,6 +667,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile index ce13bc71e..19d2e9abe 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile index ce13bc71e..19d2e9abe 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index 1d3ce9e28..da400240b 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index a89bf28bc..7779d7ac5 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -652,6 +652,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index 6d357a444..738aade00 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -84,6 +84,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index 2e9101c82..c7dc789cc 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index fffd29fdd..9fbbe9b06 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -693,6 +693,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile index aebfc96be..fc8cef49d 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile index aebfc96be..fc8cef49d 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index fbe3d3237..c53d6f95b 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index 488e1419b..0d2829d91 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -760,6 +760,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile index 95f9d0030..1d46ca2a2 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile @@ -84,6 +84,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index 2a60d9d0d..fc5078e61 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index 5e89dc1fb..e632e4495 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -687,6 +687,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile index e0c8907d2..1ea7629c8 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile index e0c8907d2..1ea7629c8 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile index 2d0efaf0c..240acf838 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py index c907a7fc9..7c9029908 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -754,6 +754,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile index cc9b5fbd6..7a6cb9c32 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile @@ -83,6 +83,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index 92cbcaa50..00356574f 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -111,6 +111,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index 5c7899f4f..66341cdb9 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -757,6 +757,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile index 1bb6b65ba..0779d69a9 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile index 1bb6b65ba..0779d69a9 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile @@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index 403fb4214..82d355d8a 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index e38ff47aa..749669bc4 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -904,6 +904,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile index fc73e734c..b04483282 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile @@ -91,6 +91,7 @@ SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_axi.v SYN_FILES += lib/pcie/rtl/dma_if_axi_rd.v SYN_FILES += lib/pcie/rtl/dma_if_axi_wr.v diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index f3dece5af..0ac594e6a 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -109,6 +109,7 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_wr.v diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 9e6b0d1fa..a49fdfbf2 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -451,6 +451,7 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_axi.v"), os.path.join(pcie_rtl_dir, "dma_if_axi_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_axi_wr.v"), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index 6b0d8a0aa..72002119e 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index e75da58f6..c25724fcd 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -119,6 +119,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index 7f7701dc4..b005dc7aa 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -654,6 +654,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile index 76a5b61ac..bad0a6715 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile @@ -91,6 +91,7 @@ SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_axi.v SYN_FILES += lib/pcie/rtl/dma_if_axi_rd.v SYN_FILES += lib/pcie/rtl/dma_if_axi_wr.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index f3dece5af..0ac594e6a 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -109,6 +109,7 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_wr.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index dd53b5706..115de52db 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -421,6 +421,7 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_axi.v"), os.path.join(pcie_rtl_dir, "dma_if_axi_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_axi_wr.v"), diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index c19972191..46eb1b6d5 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -85,6 +85,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile index 481e1e768..0043f30b3 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile @@ -86,6 +86,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile index 7490fed98..cdf6b5082 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile @@ -89,6 +89,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index 646ba72e1..fd3a2ddba 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -87,6 +87,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index 870042e38..01a8d4265 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -112,6 +112,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index 7e5afeeb5..f1fb98a22 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -694,6 +694,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index 64c384247..65a53e477 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -103,6 +103,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile index 64c384247..65a53e477 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile @@ -103,6 +103,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index 9c45fbbd4..3c1b61280 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -104,6 +104,7 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index 825e5c1f5..4c036a7f0 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -120,6 +120,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 817b0f573..05976d5af 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -759,6 +759,7 @@ def test_fpga_core(request): os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),