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Improve output register filling

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This commit is contained in:
Alex Forencich 2014-10-22 15:11:41 -07:00
parent c86ffa1202
commit d82ebcce17
2 changed files with 19 additions and 6 deletions
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12
rtl/axis_rate_limit.v
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@ -70,7 +70,7 @@ reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early = output_axis_tready;
wire output_axis_tready_int_early;
reg [23:0] acc_reg = 0, acc_next;
reg pause;
@ -138,6 +138,9 @@ assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
@ -151,8 +154,7 @@ always @(posedge clk or posedge rst) begin
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
// also enable ready input next cycle if output is currently not valid and will not become valid next cycle
output_axis_tready_int <= output_axis_tready | (~output_axis_tvalid_reg & ~output_axis_tvalid_int);
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
@ -175,6 +177,10 @@ always @(posedge clk or posedge rst) begin
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end

13
rtl/axis_rate_limit_64.v
View File

@ -73,7 +73,7 @@ reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early = output_axis_tready;
wire output_axis_tready_int_early;
reg [23:0] acc_reg = 0, acc_next;
reg pause;
@ -145,6 +145,9 @@ assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
@ -160,8 +163,7 @@ always @(posedge clk or posedge rst) begin
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
// also enable ready input next cycle if output is currently not valid and will not become valid next cycle
output_axis_tready_int <= output_axis_tready | (~output_axis_tvalid_reg & ~output_axis_tvalid_int);
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
@ -187,6 +189,11 @@ always @(posedge clk or posedge rst) begin
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end