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Update ARP cache testbench
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ce13522085
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@ -43,6 +43,9 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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CACHE_ADDR_WIDTH = 2
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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@ -193,8 +196,6 @@ def bench():
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yield delay(100)
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raise StopSimulation
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yield clk.posedge
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print("test 3: write more")
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current_test.next = 3
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@ -202,7 +203,7 @@ def bench():
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yield clk.posedge
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write_request_source.send([(0xc0a80121, 0x0000c0a80121)])
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write_request_source.send([(0xc0a80122, 0x0000c0a80122)])
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# overwrites 0xc0a80121 due to LRU
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# overwrites 0xc0a80112
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write_request_source.send([(0xc0a80123, 0x0000c0a80123)])
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while not write_request_source.empty():
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@ -222,21 +223,21 @@ def bench():
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assert resp.data[0][0] == 0x0000c0a80111
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assert not resp.user[0]
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# not in cache; was overwritten
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yield clk.posedge
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query_request_source.send([(0xc0a80112, )])
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yield query_response_sink.wait()
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80112
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assert not resp.user[0]
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assert resp.user[0]
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# not in cache; was overwritten
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yield clk.posedge
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query_request_source.send([(0xc0a80121, )])
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yield query_response_sink.wait()
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resp = query_response_sink.recv()
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assert resp.user[0]
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assert resp.data[0][0] == 0x0000c0a80121
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assert not resp.user[0]
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yield clk.posedge
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query_request_source.send([(0xc0a80122, )])
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@ -254,237 +255,65 @@ def bench():
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assert resp.data[0][0] == 0x0000c0a80123
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assert not resp.user[0]
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# LRU reset by previous operation
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yield delay(100)
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raise StopSimulation
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yield clk.posedge
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print("test 5: LRU test")
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print("test 5: Test overwrite")
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current_test.next = 5
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# read to set LRU bit
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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write_request_source.send([(0xc0a80123, 0x0000c0a80164)])
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80111
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80131
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write_request_mac.next = 0x0000c0a80131
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80132
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write_request_mac.next = 0x0000c0a80132
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80133
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write_request_mac.next = 0x0000c0a80133
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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while not write_request_source.empty():
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yield clk.posedge
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# read values
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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query_request_source.send([(0xc0a80111, )])
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80111
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yield query_response_sink.wait()
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80111
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assert not resp.user[0]
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# not in cache; was overwritten
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yield clk.posedge
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query_request_source.send([(0xc0a80112, )])
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yield query_response_sink.wait()
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resp = query_response_sink.recv()
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assert resp.user[0]
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80112
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yield clk.posedge
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query_request_valid.next = False
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query_request_source.send([(0xc0a80121, )])
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield query_response_sink.wait()
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80121
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assert not resp.user[0]
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80121
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yield clk.posedge
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query_request_valid.next = False
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query_request_source.send([(0xc0a80122, )])
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield query_response_sink.wait()
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80122
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assert not resp.user[0]
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80122
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yield clk.posedge
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query_request_valid.next = False
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query_request_source.send([(0xc0a80123, )])
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80123
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80131
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80131
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80132
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80132
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80133
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80133
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# LRU reset by previous operation
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yield query_response_sink.wait()
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resp = query_response_sink.recv()
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assert resp.data[0][0] == 0x0000c0a80164
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assert not resp.user[0]
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yield delay(100)
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yield clk.posedge
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print("test 6: Test overwrite")
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print("test 6: clear cache")
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current_test.next = 6
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80133
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write_request_mac.next = 0x0000c0a80164
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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# read values
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80111
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80112
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80121
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80122
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80123
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80131
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80131
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80132
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80132
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80133
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80164
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# LRU reset by previous operation
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yield delay(100)
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yield clk.posedge
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print("test 7: clear cache")
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current_test.next = 7
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yield clk.posedge
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clear_cache.next = True
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yield clk.posedge
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@ -493,13 +322,11 @@ def bench():
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yield delay(100)
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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query_request_source.send([(0xc0a80111, )])
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield query_response_sink.wait()
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resp = query_response_sink.recv()
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assert resp.user[0]
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yield delay(100)
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@ -31,6 +31,9 @@ THE SOFTWARE.
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*/
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module test_arp_cache;
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// Parameters
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parameter CACHE_ADDR_WIDTH = 2;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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@ -84,7 +87,7 @@ initial begin
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end
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arp_cache #(
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.CACHE_ADDR_WIDTH(2)
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.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH)
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)
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UUT (
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.clk(clk),
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