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Add feature bits

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This commit is contained in:
Alex Forencich 2019-08-19 23:43:52 -07:00
parent 1fc15d234d
commit d977cbdac2
3 changed files with 22 additions and 2 deletions
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7
fpga/common/rtl/interface.v
View File

@ -761,7 +761,12 @@ always @(posedge clk) begin
case ({axil_ctrl_araddr[15:2], 2'b00}) case ({axil_ctrl_araddr[15:2], 2'b00})
16'h0000: axil_ctrl_rdata_reg <= 32'd0; // if_id 16'h0000: axil_ctrl_rdata_reg <= 32'd0; // if_id
16'h0004: axil_ctrl_rdata_reg <= 32'd0; // if_features 16'h0004: begin
// if_features
axil_ctrl_rdata_reg[4] <= PTP_TS_ENABLE;
axil_ctrl_rdata_reg[8] <= TX_CHECKSUM_ENABLE;
axil_ctrl_rdata_reg[9] <= RX_CHECKSUM_ENABLE;
end
16'h0010: axil_ctrl_rdata_reg <= 2**EVENT_QUEUE_INDEX_WIDTH; // event_queue_count 16'h0010: axil_ctrl_rdata_reg <= 2**EVENT_QUEUE_INDEX_WIDTH; // event_queue_count
16'h0014: axil_ctrl_rdata_reg <= 24'h080000; // event_queue_offset 16'h0014: axil_ctrl_rdata_reg <= 24'h080000; // event_queue_offset
16'h0020: axil_ctrl_rdata_reg <= 2**TX_QUEUE_INDEX_WIDTH; // tx_queue_count 16'h0020: axil_ctrl_rdata_reg <= 2**TX_QUEUE_INDEX_WIDTH; // tx_queue_count

7
fpga/common/rtl/port.v
View File

@ -763,7 +763,12 @@ always @(posedge clk) begin
case ({axil_ctrl_araddr[15:2], 2'b00}) case ({axil_ctrl_araddr[15:2], 2'b00})
16'h0000: axil_ctrl_rdata_reg <= 32'd0; // port_id 16'h0000: axil_ctrl_rdata_reg <= 32'd0; // port_id
16'h0004: axil_ctrl_rdata_reg <= 32'd0; // port_features 16'h0004: begin
// port_features
axil_ctrl_rdata_reg[4] <= PTP_TS_ENABLE;
axil_ctrl_rdata_reg[8] <= TX_CHECKSUM_ENABLE;
axil_ctrl_rdata_reg[9] <= RX_CHECKSUM_ENABLE;
end
16'h0010: axil_ctrl_rdata_reg <= 1; // scheduler_count 16'h0010: axil_ctrl_rdata_reg <= 1; // scheduler_count
16'h0014: axil_ctrl_rdata_reg <= 24'h040000; // scheduler_offset 16'h0014: axil_ctrl_rdata_reg <= 24'h040000; // scheduler_offset
16'h0018: axil_ctrl_rdata_reg <= 24'h040000; // scheduler_stride 16'h0018: axil_ctrl_rdata_reg <= 24'h040000; // scheduler_stride

10
modules/mqnic/mqnic_hw.h
View File

@ -122,6 +122,11 @@ either expressed or implied, of The Regents of the University of California.
#define MQNIC_IF_REG_PORT_OFFSET 0x0044 #define MQNIC_IF_REG_PORT_OFFSET 0x0044
#define MQNIC_IF_REG_PORT_STRIDE 0x0048 #define MQNIC_IF_REG_PORT_STRIDE 0x0048
#define MQNIC_IF_FEATURE_RSS (1 << 0)
#define MQNIC_IF_FEATURE_PTP_TS (1 << 4)
#define MQNIC_IF_FEATURE_TX_CSUM (1 << 8)
#define MQNIC_IF_FEATURE_RX_CSUM (1 << 9)
// Port CSRs // Port CSRs
#define MQNIC_PORT_REG_PORT_ID 0x0000 #define MQNIC_PORT_REG_PORT_ID 0x0000
#define MQNIC_PORT_REG_PORT_FEATURES 0x0004 #define MQNIC_PORT_REG_PORT_FEATURES 0x0004
@ -150,6 +155,11 @@ either expressed or implied, of The Regents of the University of California.
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L 0x0118 #define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L 0x0118
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H 0x011C #define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H 0x011C
#define MQNIC_PORT_FEATURE_RSS (1 << 0)
#define MQNIC_PORT_FEATURE_PTP_TS (1 << 4)
#define MQNIC_PORT_FEATURE_TX_CSUM (1 << 8)
#define MQNIC_PORT_FEATURE_RX_CSUM (1 << 9)
#define MQNIC_QUEUE_STRIDE 0x00000020 #define MQNIC_QUEUE_STRIDE 0x00000020
#define MQNIC_CPL_QUEUE_STRIDE 0x00000020 #define MQNIC_CPL_QUEUE_STRIDE 0x00000020
#define MQNIC_EVENT_QUEUE_STRIDE 0x00000020 #define MQNIC_EVENT_QUEUE_STRIDE 0x00000020