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Update parameters

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This commit is contained in:
Alex Forencich 2022-02-01 00:23:52 -08:00
parent 74e4322d43
commit d9c4b173e9
6 changed files with 21 additions and 9 deletions
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10
rtl/dma_if_axi.v
View File

@ -63,8 +63,10 @@ module dma_if_axi #
parameter READ_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
// Use AXI ID signals
parameter USE_AXI_ID = 1
// Use AXI ID signals (read)
parameter READ_USE_AXI_ID = 0,
// Use AXI ID signals (write)
parameter WRITE_USE_AXI_ID = 1
)
(
input wire clk,
@ -185,7 +187,7 @@ dma_if_axi_rd #(
.LEN_WIDTH(LEN_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.USE_AXI_ID(USE_AXI_ID)
.USE_AXI_ID(READ_USE_AXI_ID)
)
dma_if_axi_rd_inst (
.clk(clk),
@ -261,7 +263,7 @@ dma_if_axi_wr #(
.LEN_WIDTH(LEN_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.USE_AXI_ID(USE_AXI_ID)
.USE_AXI_ID(WRITE_USE_AXI_ID)
)
dma_if_axi_wr_inst (
.clk(clk),

9
tb/dma_if_axi/Makefile
View File

@ -48,7 +48,8 @@ export PARAM_LEN_WIDTH ?= 16
export PARAM_TAG_WIDTH ?= 8
export PARAM_READ_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_USE_AXI_ID ?= 1
export PARAM_READ_USE_AXI_ID ?= 0
export PARAM_WRITE_USE_AXI_ID ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@ -67,7 +68,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).READ_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).USE_AXI_ID=$(PARAM_USE_AXI_ID)
COMPILE_ARGS += -P $(TOPLEVEL).READ_USE_AXI_ID=$(PARAM_READ_USE_AXI_ID)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_USE_AXI_ID=$(PARAM_WRITE_USE_AXI_ID)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -90,7 +92,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GREAD_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -GWRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GUSE_AXI_ID=$(PARAM_USE_AXI_ID)
COMPILE_ARGS += -GREAD_USE_AXI_ID=$(PARAM_READ_USE_AXI_ID)
COMPILE_ARGS += -GWRITE_USE_AXI_ID=$(PARAM_WRITE_USE_AXI_ID)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

3
tb/dma_if_axi/test_dma_if_axi.py
View File

@ -267,7 +267,8 @@ def test_dma_if_axi(request, axi_data_width):
parameters['TAG_WIDTH'] = 8
parameters['READ_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
parameters['USE_AXI_ID'] = 1
parameters['READ_USE_AXI_ID'] = 0
parameters['WRITE_USE_AXI_ID'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

3
tb/dma_if_axi_rd/Makefile
View File

@ -45,6 +45,7 @@ export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WID
export PARAM_LEN_WIDTH ?= 16
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_USE_AXI_ID ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@ -62,6 +63,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).USE_AXI_ID=$(PARAM_USE_AXI_ID)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -83,6 +85,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -GUSE_AXI_ID=$(PARAM_USE_AXI_ID)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

2
tb/dma_if_axi_rd/test_dma_if_axi_rd.py
View File

@ -202,7 +202,7 @@ def test_dma_if_axi_rd(request, axi_data_width):
parameters['LEN_WIDTH'] = 16
parameters['TAG_WIDTH'] = 8
parameters['OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
parameters['USE_AXI_ID'] = 1
parameters['USE_AXI_ID'] = 0
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

3
tb/dma_if_axi_wr/Makefile
View File

@ -45,6 +45,7 @@ export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WID
export PARAM_LEN_WIDTH ?= 16
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_USE_AXI_ID ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@ -62,6 +63,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).USE_AXI_ID=$(PARAM_USE_AXI_ID)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -83,6 +85,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -GUSE_AXI_ID=$(PARAM_USE_AXI_ID)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst