diff --git a/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl b/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
index 52106b75a..e26a1d705 100644
--- a/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
+++ b/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
@@ -8,11 +8,13 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_rb_clk_info || RE
 
     set clk [get_clocks -of_objects [get_cells "$inst/ref_strb_sync_1_reg_reg"]]
 
+    set clk_period [if {[llength $clk]} {get_property -min PERIOD $clk} {expr 1.0}]
+
     set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/ref_strb_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
 
-    set_max_delay -from [get_cells "$inst/ref_strb_reg_reg"] -to [get_cells "$inst/ref_strb_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $clk]
+    set_max_delay -from [get_cells "$inst/ref_strb_reg_reg"] -to [get_cells "$inst/ref_strb_sync_1_reg_reg"] -datapath_only $clk_period
 
     set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/channel\\\[\\d+\\\]\\.ch_flag_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
 
-    set_max_delay -from [get_cells "$inst/channel[*].ch_prescale_reg_reg[*]"] -to [get_cells "$inst/channel[*].ch_flag_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $clk]
+    set_max_delay -from [get_cells "$inst/channel[*].ch_prescale_reg_reg[*]"] -to [get_cells "$inst/channel[*].ch_flag_sync_1_reg_reg"] -datapath_only $clk_period
 }