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fpga/common: Update clock info register block timing constraints to handle clocks from OOC cores that are not defined during synthesis

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-23 00:41:21 -08:00
parent 2e8e24f446
commit d9c856b877
1 changed files with 4 additions and 2 deletions
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6
fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
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@ -8,11 +8,13 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_rb_clk_info || RE
set clk [get_clocks -of_objects [get_cells "$inst/ref_strb_sync_1_reg_reg"]]
set clk_period [if {[llength $clk]} {get_property -min PERIOD $clk} {expr 1.0}]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/ref_strb_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/ref_strb_reg_reg"] -to [get_cells "$inst/ref_strb_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $clk]
set_max_delay -from [get_cells "$inst/ref_strb_reg_reg"] -to [get_cells "$inst/ref_strb_sync_1_reg_reg"] -datapath_only $clk_period
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/channel\\\[\\d+\\\]\\.ch_flag_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/channel[*].ch_prescale_reg_reg[*]"] -to [get_cells "$inst/channel[*].ch_flag_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $clk]
set_max_delay -from [get_cells "$inst/channel[*].ch_prescale_reg_reg[*]"] -to [get_cells "$inst/channel[*].ch_flag_sync_1_reg_reg"] -datapath_only $clk_period
}