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fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-09-24 13:52:06 -07:00
parent 66b1a28159
commit d9e4b82f7a
188 changed files with 0 additions and 278 deletions
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1
fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
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@ -29,7 +29,6 @@ module mqnic_app_block #
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,

1
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -132,7 +132,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -1087,7 +1087,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

1
fpga/app/template/rtl/mqnic_app_block.v
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@ -29,7 +29,6 @@ module mqnic_app_block #
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,

1
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
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@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -883,7 +883,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

3
fpga/common/rtl/mqnic_core.v
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@ -41,7 +41,6 @@ module mqnic_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_TX_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -825,7 +824,6 @@ mqnic_ptp #(
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
.REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
@ -3616,7 +3614,6 @@ if (APP_ENABLE) begin : app
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/common/rtl/mqnic_core_axi.v
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@ -41,7 +41,6 @@ module mqnic_core_axi #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_TX_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -972,7 +971,6 @@ mqnic_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

2
fpga/common/rtl/mqnic_core_pcie.v
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@ -41,7 +41,6 @@ module mqnic_core_pcie #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_TX_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -1604,7 +1603,6 @@ mqnic_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

2
fpga/common/rtl/mqnic_core_pcie_ptile.v
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@ -41,7 +41,6 @@ module mqnic_core_pcie_ptile #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_TX_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -766,7 +765,6 @@ mqnic_core_pcie #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

2
fpga/common/rtl/mqnic_core_pcie_s10.v
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@ -41,7 +41,6 @@ module mqnic_core_pcie_s10 #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_TX_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -775,7 +774,6 @@ mqnic_core_pcie #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

2
fpga/common/rtl/mqnic_core_pcie_us.v
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@ -41,7 +41,6 @@ module mqnic_core_pcie_us #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_TX_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -895,7 +894,6 @@ mqnic_core_pcie #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

2
fpga/common/rtl/mqnic_ptp.v
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@ -18,7 +18,6 @@ module mqnic_ptp #
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
parameter REG_ADDR_WIDTH = 7+(PTP_PEROUT_ENABLE ? $clog2((PTP_PEROUT_COUNT+1)/2) + 1 : 0),
@ -131,7 +130,6 @@ mqnic_ptp_clock #(
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),

1
fpga/common/rtl/mqnic_ptp_clock.v
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@ -18,7 +18,6 @@ module mqnic_ptp_clock #
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
parameter REG_ADDR_WIDTH = 7,

1
fpga/common/tb/mqnic_core_axi/Makefile
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@ -110,7 +110,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
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@ -658,7 +658,6 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

1
fpga/common/tb/mqnic_core_pcie_ptile/Makefile
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@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
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@ -874,7 +874,6 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

1
fpga/common/tb/mqnic_core_pcie_s10/Makefile
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@ -124,7 +124,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
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@ -821,7 +821,6 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

1
fpga/common/tb/mqnic_core_pcie_us/Makefile
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@ -124,7 +124,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -895,7 +895,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

1
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
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@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
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@ -950,7 +950,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

2
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
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@ -221,7 +221,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 512;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -1258,7 +1257,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),

2
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
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@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -980,7 +979,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
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@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 0

1
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
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@ -689,7 +689,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

2
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
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@ -228,7 +228,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 512;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -1342,7 +1341,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
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@ -43,7 +43,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -1179,7 +1178,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
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@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 0
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
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@ -705,7 +705,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v
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@ -192,7 +192,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -1285,7 +1284,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v
View File

@ -43,7 +43,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
@ -953,7 +952,6 @@ mqnic_core_pcie_s10 #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile
View File

@ -134,7 +134,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 1
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -613,7 +613,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -248,7 +248,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -1618,7 +1617,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -1070,7 +1069,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 0

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -692,7 +692,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -255,7 +255,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h2;
parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
@ -1706,7 +1705,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -43,7 +43,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -1274,7 +1273,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -137,7 +137,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 0
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -708,7 +708,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -279,7 +279,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -2018,7 +2017,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),

2
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -1057,7 +1056,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 0

1
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -689,7 +689,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

2
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -286,7 +286,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -2103,7 +2102,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -43,7 +43,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -1256,7 +1255,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 0
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -705,7 +705,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -279,7 +279,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -2018,7 +2017,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -1057,7 +1056,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 0

1
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -689,7 +689,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

2
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -286,7 +286,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -2103,7 +2102,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -43,7 +43,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -1256,7 +1255,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 0
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -705,7 +705,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -235,7 +235,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -3145,7 +3144,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
@ -1000,7 +999,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 1
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 1
export PARAM_PTP_PEROUT_ENABLE := 0

1
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -681,7 +681,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 1
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 1
parameters['PTP_PEROUT_ENABLE'] = 0

2
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -242,7 +242,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -3236,7 +3235,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -43,7 +43,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -1199,7 +1198,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 1
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 1
export PARAM_PTP_PEROUT_ENABLE := 0
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -697,7 +697,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 1
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 1
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -183,7 +183,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -2596,7 +2595,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),

2
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
@ -852,7 +851,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 1
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 1
export PARAM_PTP_PEROUT_ENABLE := 0

1
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -659,7 +659,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 1
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 1
parameters['PTP_PEROUT_ENABLE'] = 0

2
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -190,7 +190,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -2645,7 +2644,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -43,7 +43,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -1041,7 +1040,6 @@ mqnic_core_pcie_us #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 1
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 1
export PARAM_PTP_PEROUT_ENABLE := 0
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -675,7 +675,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 1
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 1
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v
View File

@ -192,7 +192,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 2048;
parameter PTP_CLK_PERIOD_NS_DENOM = 825;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 8;
parameter PTP_USE_SAMPLE_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
@ -765,7 +764,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
@ -763,7 +762,6 @@ mqnic_core_pcie_ptile #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile
View File

@ -131,7 +131,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 1
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -670,7 +670,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v
View File

@ -194,7 +194,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 2048;
parameter PTP_CLK_PERIOD_NS_DENOM = 825;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 8;
parameter PTP_USE_SAMPLE_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
@ -1805,7 +1804,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(1),
.PTP_SEPARATE_RX_CLOCK(1),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

2
fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_TX_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -1293,7 +1292,6 @@ mqnic_core_pcie_ptile #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile
View File

@ -131,7 +131,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -654,7 +654,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

2
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v
View File

@ -185,7 +185,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 4096;
parameter PTP_CLK_PERIOD_NS_DENOM = 825;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 8;
parameter PTP_USE_SAMPLE_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
@ -614,7 +613,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
@ -618,7 +617,6 @@ mqnic_core_pcie_ptile #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile
View File

@ -128,7 +128,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 4096
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 1
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -654,7 +654,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v
View File

@ -187,7 +187,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 4096;
parameter PTP_CLK_PERIOD_NS_DENOM = 825;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 8;
parameter PTP_USE_SAMPLE_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
@ -1134,7 +1133,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(1),
.PTP_SEPARATE_RX_CLOCK(1),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

2
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_TX_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -872,7 +871,6 @@ mqnic_core_pcie_ptile #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile
View File

@ -128,7 +128,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 4096
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_SEPARATE_TX_CLOCK := 0
export PARAM_PTP_SEPARATE_RX_CLOCK := 0
export PARAM_PTP_PORT_CDC_PIPELINE := 0

1
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -646,7 +646,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0

2
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v
View File

@ -189,7 +189,6 @@ module fpga #
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -982,7 +981,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v
View File

@ -43,7 +43,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
@ -919,7 +918,6 @@ mqnic_core_pcie_s10 #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile
View File

@ -135,7 +135,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 1
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -616,7 +616,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1

2
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v
View File

@ -199,7 +199,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 2048;
parameter PTP_CLK_PERIOD_NS_DENOM = 825;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 8;
parameter PTP_USE_SAMPLE_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
@ -762,7 +761,6 @@ fpga_core #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

2
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v
View File

@ -40,7 +40,6 @@ module fpga_core #
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
@ -818,7 +817,6 @@ mqnic_core_pcie_ptile #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile
View File

@ -132,7 +132,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 1
export PARAM_PTP_PEROUT_COUNT := 1

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -670,7 +670,6 @@ def test_fpga_core(request):
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1

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