From d9e4b82f7aa2382cda14d779df3a35b155f21971 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 24 Sep 2023 13:52:06 -0700 Subject: [PATCH] fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter Signed-off-by: Alex Forencich --- fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v | 1 - fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile | 1 - .../dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 1 - fpga/app/template/rtl/mqnic_app_block.v | 1 - fpga/app/template/tb/mqnic_core_pcie_us/Makefile | 1 - .../template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 1 - fpga/common/rtl/mqnic_core.v | 3 --- fpga/common/rtl/mqnic_core_axi.v | 2 -- fpga/common/rtl/mqnic_core_pcie.v | 2 -- fpga/common/rtl/mqnic_core_pcie_ptile.v | 2 -- fpga/common/rtl/mqnic_core_pcie_s10.v | 2 -- fpga/common/rtl/mqnic_core_pcie_us.v | 2 -- fpga/common/rtl/mqnic_ptp.v | 2 -- fpga/common/rtl/mqnic_ptp_clock.v | 1 - fpga/common/tb/mqnic_core_axi/Makefile | 1 - fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py | 1 - fpga/common/tb/mqnic_core_pcie_ptile/Makefile | 1 - .../tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py | 1 - fpga/common/tb/mqnic_core_pcie_s10/Makefile | 1 - fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py | 1 - fpga/common/tb/mqnic_core_pcie_us/Makefile | 1 - fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 1 - fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile | 1 - .../tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py | 1 - fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile | 1 - .../ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile | 1 - .../mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU200/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU200/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU250/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU250/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU280/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU280/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU50/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/AU50/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile | 1 - .../mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile | 1 - .../DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile | 1 - .../DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile | 1 - .../DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile | 1 - .../DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile | 1 - .../DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v | 2 -- fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v | 2 -- fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile | 1 - .../DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/KR260/fpga/rtl/fpga.v | 2 -- fpga/mqnic/KR260/fpga/rtl/fpga_core.v | 2 -- fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile | 1 - fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v | 2 -- fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v | 2 -- fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 1 - fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v | 2 -- fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v | 2 -- fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile | 1 - fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ZCU102/fpga/rtl/fpga.v | 2 -- fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v | 2 -- fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile | 1 - fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v | 2 -- fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v | 2 -- fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile | 1 - fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v | 2 -- fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v | 2 -- fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile | 1 - fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v | 2 -- fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v | 2 -- fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile | 1 - fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v | 2 -- fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v | 2 -- fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile | 1 - fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py | 1 - 188 files changed, 278 deletions(-) diff --git a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v index 8cd2e4f49..01aaaf0bf 100644 --- a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v +++ b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v @@ -29,7 +29,6 @@ module mqnic_app_block # parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, parameter PTP_TS_WIDTH = 96, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index dd0d2282c..3d546fc27 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -132,7 +132,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 8365e1d84..a2c7dd7ae 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -1087,7 +1087,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v index b13dc287d..22719f46a 100644 --- a/fpga/app/template/rtl/mqnic_app_block.v +++ b/fpga/app/template/rtl/mqnic_app_block.v @@ -29,7 +29,6 @@ module mqnic_app_block # parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, parameter PTP_TS_WIDTH = 96, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index ae30eb0ba..8a813ff3d 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index c2ecc0c21..65dd7908b 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -883,7 +883,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 67bd7fbdb..a53cbac2f 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -41,7 +41,6 @@ module mqnic_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_SEPARATE_TX_CLOCK = 0, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -825,7 +824,6 @@ mqnic_ptp #( .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), .REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), @@ -3616,7 +3614,6 @@ if (APP_ENABLE) begin : app .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v index 785a01c0d..813aaeed3 100644 --- a/fpga/common/rtl/mqnic_core_axi.v +++ b/fpga/common/rtl/mqnic_core_axi.v @@ -41,7 +41,6 @@ module mqnic_core_axi # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_SEPARATE_TX_CLOCK = 0, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -972,7 +971,6 @@ mqnic_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index b8bdc4073..638265675 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -41,7 +41,6 @@ module mqnic_core_pcie # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_SEPARATE_TX_CLOCK = 0, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -1604,7 +1603,6 @@ mqnic_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/common/rtl/mqnic_core_pcie_ptile.v b/fpga/common/rtl/mqnic_core_pcie_ptile.v index fd885c7a1..1df33947b 100644 --- a/fpga/common/rtl/mqnic_core_pcie_ptile.v +++ b/fpga/common/rtl/mqnic_core_pcie_ptile.v @@ -41,7 +41,6 @@ module mqnic_core_pcie_ptile # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_SEPARATE_TX_CLOCK = 0, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -766,7 +765,6 @@ mqnic_core_pcie #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index f185719ba..0d025f8b4 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -41,7 +41,6 @@ module mqnic_core_pcie_s10 # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_SEPARATE_TX_CLOCK = 0, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -775,7 +774,6 @@ mqnic_core_pcie #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index 3b1472983..5dabfbb1a 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -41,7 +41,6 @@ module mqnic_core_pcie_us # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_SEPARATE_TX_CLOCK = 0, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -895,7 +894,6 @@ mqnic_core_pcie #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/common/rtl/mqnic_ptp.v b/fpga/common/rtl/mqnic_ptp.v index 76ded3b81..dd8d7ffb3 100644 --- a/fpga/common/rtl/mqnic_ptp.v +++ b/fpga/common/rtl/mqnic_ptp.v @@ -18,7 +18,6 @@ module mqnic_ptp # parameter PTP_CLK_PERIOD_NS_DENOM = 1, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, parameter REG_ADDR_WIDTH = 7+(PTP_PEROUT_ENABLE ? $clog2((PTP_PEROUT_COUNT+1)/2) + 1 : 0), @@ -131,7 +130,6 @@ mqnic_ptp_clock #( .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), .REG_ADDR_WIDTH(REG_ADDR_WIDTH), diff --git a/fpga/common/rtl/mqnic_ptp_clock.v b/fpga/common/rtl/mqnic_ptp_clock.v index 8e9b4f44a..ef72a896e 100644 --- a/fpga/common/rtl/mqnic_ptp_clock.v +++ b/fpga/common/rtl/mqnic_ptp_clock.v @@ -18,7 +18,6 @@ module mqnic_ptp_clock # parameter PTP_CLK_PERIOD_NS_DENOM = 1, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, parameter REG_ADDR_WIDTH = 7, diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index add7f81b8..49ec5bd01 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -110,7 +110,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index 474783e89..52efe38be 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -658,7 +658,6 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width, parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index bb614ccf2..6161dfcbb 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index bb6337941..9e884a131 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -874,7 +874,6 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index 0bc8071ce..3c9c59410 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -124,7 +124,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 72b1ba3fa..875895507 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -821,7 +821,6 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index a389a36b2..f0ad846cb 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -124,7 +124,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 9b5d8dc77..2cc13e192 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -895,7 +895,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 4ccfef3a4..0b0beefe4 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index b11a4e3a5..b3b60a0e6 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -950,7 +950,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v index bad7d7bb7..aec63f850 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v @@ -221,7 +221,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 512; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -1258,7 +1257,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index c0848225b..a6d25c160 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, @@ -980,7 +979,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index e0a17fb58..72ca73a2b 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index 463b97a66..2b4207b84 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,7 +689,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index 5fdf2c0d7..ba0facf94 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -228,7 +228,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 512; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1342,7 +1341,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v index 787ef125c..234bf33ed 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -1179,7 +1178,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index efbf27821..9305162ed 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index 47e9de27a..56f79576e 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -705,7 +705,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v index 0208f5aca..e87a6f75e 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v @@ -192,7 +192,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1285,7 +1284,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v index 09c15f22d..053be6d54 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -953,7 +952,6 @@ mqnic_core_pcie_s10 #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile index d44c27650..1e0b2137d 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile @@ -134,7 +134,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py index 0cea9b98b..c67f9eff5 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -613,7 +613,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v index 52d142b6b..77bb9f851 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v @@ -248,7 +248,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -1618,7 +1617,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index ff64b228b..6916684c3 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, @@ -1070,7 +1069,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index 234a9b657..67b6abbfd 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 2b8147214..7a9f13d00 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -692,7 +692,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 9c31ba2d3..cd26b2bec 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -255,7 +255,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h2; parameter IF_PTP_PERIOD_FNS = 16'h8F5C; @@ -1706,7 +1705,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 236d5909b..92ff9bf1e 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -1274,7 +1273,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index b0060d1eb..84a7dbc3c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -137,7 +137,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index fd781499b..a33e16d22 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -708,7 +708,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index b8cce68b7..ab4acad81 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -279,7 +279,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -2018,7 +2017,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 96317fd1b..aa98d6f89 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, @@ -1057,7 +1056,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index e8de2d7d3..6b3457a52 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index c43b5c299..87569e0dc 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,7 +689,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index 7437e3147..97017f21e 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -286,7 +286,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -2103,7 +2102,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 3e9c5021c..91b162dbd 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -1256,7 +1255,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index 78a21e1ad..a480035a9 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index ccdbd64c8..51914360e 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -705,7 +705,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v index c1b6d8a0f..a7ceb611e 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v @@ -279,7 +279,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -2018,7 +2017,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index 9b1a58769..ff0930b2a 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, @@ -1057,7 +1056,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index e8de2d7d3..6b3457a52 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index c43b5c299..87569e0dc 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,7 +689,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index 89a1a32ed..7271c2d0c 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -286,7 +286,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -2103,7 +2102,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v index 101e0c751..3a51ec6d5 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -1256,7 +1255,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile index 78a21e1ad..a480035a9 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py index ccdbd64c8..51914360e 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -705,7 +705,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v index 2191a08ac..541fa618f 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -235,7 +235,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -3145,7 +3144,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index 4399a693d..2ac4f896e 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 1, parameter PTP_PEROUT_ENABLE = 0, @@ -1000,7 +999,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index 2f8a0cc7e..0bde67d54 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 1 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 1 export PARAM_PTP_PEROUT_ENABLE := 0 diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 48d175ed2..c5dd0e429 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -681,7 +681,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 1 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 1 parameters['PTP_PEROUT_ENABLE'] = 0 diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index be42e650f..250d54676 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -242,7 +242,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -3236,7 +3235,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index 6a0adfc31..5f1e04f27 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 1, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -1199,7 +1198,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index be03d8c5d..50f7c51ea 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 1 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 1 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index cba21d76e..6f10a3ca1 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -697,7 +697,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 1 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 1 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v index 3ed345f0a..07c951deb 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v @@ -183,7 +183,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -2596,7 +2595,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index c79db94fe..183caed4d 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 1, parameter PTP_PEROUT_ENABLE = 0, @@ -852,7 +851,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index 136a99609..b55ebb732 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 1 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 1 export PARAM_PTP_PEROUT_ENABLE := 0 diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index ed7a64181..7c3e426b7 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -659,7 +659,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 1 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 1 parameters['PTP_PEROUT_ENABLE'] = 0 diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index 2689ebf1b..44a7c7004 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -190,7 +190,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -2645,7 +2644,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index e1e99803e..3a4ce9817 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 1, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -1041,7 +1040,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index 633185f56..14b9e4f45 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 1 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 1 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index 0d6c45b25..f9b1835d9 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -675,7 +675,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 1 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 1 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v index 18b240ff8..ca9c858dc 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v @@ -192,7 +192,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 2048; parameter PTP_CLK_PERIOD_NS_DENOM = 825; parameter PTP_TS_WIDTH = 96; parameter PTP_TAG_WIDTH = 8; -parameter PTP_USE_SAMPLE_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = PTP_TAG_WIDTH; @@ -765,7 +764,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v index cdd72620a..3f56b77a4 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -763,7 +762,6 @@ mqnic_core_pcie_ptile #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile index 959c3c35d..e650a2c05 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile @@ -131,7 +131,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index 980f96717..7655e7f3f 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -670,7 +670,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v index 660766825..7171c847e 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v @@ -194,7 +194,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 2048; parameter PTP_CLK_PERIOD_NS_DENOM = 825; parameter PTP_TS_WIDTH = 96; parameter PTP_TAG_WIDTH = 8; -parameter PTP_USE_SAMPLE_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = PTP_TAG_WIDTH; @@ -1805,7 +1804,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(1), .PTP_SEPARATE_RX_CLOCK(1), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v index d94e90e54..ac1c5ed66 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_TX_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -1293,7 +1292,6 @@ mqnic_core_pcie_ptile #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile index e97f4f6f8..61cd4be5c 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile @@ -131,7 +131,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py index 92c9418cc..32a85ff0e 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -654,7 +654,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v index fea7e216b..2612b0e4f 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v @@ -185,7 +185,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 4096; parameter PTP_CLK_PERIOD_NS_DENOM = 825; parameter PTP_TS_WIDTH = 96; parameter PTP_TAG_WIDTH = 8; -parameter PTP_USE_SAMPLE_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = PTP_TAG_WIDTH; @@ -614,7 +613,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v index 17d3fddf2..6118247da 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -618,7 +617,6 @@ mqnic_core_pcie_ptile #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile index 0514e94eb..bfcf723d5 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile @@ -128,7 +128,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 4096 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py index 229b2d1ab..7595b64eb 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -654,7 +654,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v index 062fa3fbf..b1537dfd2 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v @@ -187,7 +187,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 4096; parameter PTP_CLK_PERIOD_NS_DENOM = 825; parameter PTP_TS_WIDTH = 96; parameter PTP_TAG_WIDTH = 8; -parameter PTP_USE_SAMPLE_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = PTP_TAG_WIDTH; @@ -1134,7 +1133,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(1), .PTP_SEPARATE_RX_CLOCK(1), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v index 5a9136ecc..3712ceb5a 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_TX_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -872,7 +871,6 @@ mqnic_core_pcie_ptile #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile index e238a8428..69f6ba408 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile @@ -128,7 +128,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 4096 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py index 22da5624c..0eb16809c 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -646,7 +646,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v index 40e8948e2..0a240c502 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v @@ -189,7 +189,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -982,7 +981,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v index d632a1117..8a7abee1e 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -919,7 +918,6 @@ mqnic_core_pcie_s10 #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile index f7e55b764..5a237ee25 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile @@ -135,7 +135,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py index 710cc61f5..fb17b4d55 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -616,7 +616,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v index f9d76a06a..d7ad83c19 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v @@ -199,7 +199,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 2048; parameter PTP_CLK_PERIOD_NS_DENOM = 825; parameter PTP_TS_WIDTH = 96; parameter PTP_TAG_WIDTH = 8; -parameter PTP_USE_SAMPLE_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = PTP_TAG_WIDTH; @@ -762,7 +761,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v index 5bc1b2640..c75259ed4 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -818,7 +817,6 @@ mqnic_core_pcie_ptile #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile index 1423ef2ca..7f3500b1c 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile @@ -132,7 +132,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py index 1cb6af34b..e119c7a4c 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -670,7 +670,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v index 8a1a2ad0d..da4eb1377 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v @@ -201,7 +201,6 @@ parameter PTP_CLK_PERIOD_NS_NUM = 2048; parameter PTP_CLK_PERIOD_NS_DENOM = 825; parameter PTP_TS_WIDTH = 96; parameter PTP_TAG_WIDTH = 8; -parameter PTP_USE_SAMPLE_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = PTP_TAG_WIDTH; @@ -1802,7 +1801,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(1), .PTP_SEPARATE_RX_CLOCK(1), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v index 2f5b8dc34..877de12a1 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_TX_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, @@ -1324,7 +1323,6 @@ mqnic_core_pcie_ptile #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile index 2665007c9..fd610d330 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile @@ -132,7 +132,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 2048 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_TX_CLOCK := 0 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py index 2d96ec42f..21509236f 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -654,7 +654,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_TX_CLOCK'] = 0 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index e07106ec1..964151ae9 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -246,7 +246,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1548,7 +1547,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index d44cb1566..4077b52e9 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -1275,7 +1274,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index 127984b05..1bf4c8ee5 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index 6134aa680..bdeae2d79 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -665,7 +665,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga.v b/fpga/mqnic/KR260/fpga/rtl/fpga.v index 6dfe63eb3..a3adfdd9b 100644 --- a/fpga/mqnic/KR260/fpga/rtl/fpga.v +++ b/fpga/mqnic/KR260/fpga/rtl/fpga.v @@ -174,7 +174,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -662,7 +661,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga_core.v b/fpga/mqnic/KR260/fpga/rtl/fpga_core.v index 1564e0e94..f8f0a74cd 100644 --- a/fpga/mqnic/KR260/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/KR260/fpga/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -864,7 +863,6 @@ mqnic_core_axi #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile index 962a2f758..bfcde4236 100644 --- a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile @@ -120,7 +120,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py index e9f39181c..79b9bbc07 100644 --- a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py @@ -433,7 +433,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v index 2e5233107..7c52124b6 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v @@ -215,7 +215,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1298,7 +1297,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index bd491dac4..f1b60a111 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -821,7 +820,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 4661932b0..3bc0dcfed 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -134,7 +134,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index f7d1bb550..cb0daa267 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -655,7 +655,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v index c011c33ae..88e2a2745 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v @@ -207,7 +207,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1013,7 +1012,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v index 10ede33ed..8cd9a1839 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -996,7 +995,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile index 2d6b6da10..70b04c775 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py index 7bbacdf3b..f98411eb2 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py @@ -670,7 +670,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index e8b8b559b..194dd14df 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -240,7 +240,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 4; parameter PTP_CLK_PERIOD_NS_DENOM = 1; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h2; parameter IF_PTP_PERIOD_FNS = 16'h8F5C; @@ -1565,7 +1564,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index fc53b259d..9be1c3a87 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -1310,7 +1309,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index ad0525a2f..07858540c 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index 6fbf52859..4dc1e156e 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -705,7 +705,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v index 3b4dc12cd..4ab4b18da 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v @@ -209,7 +209,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 4; parameter PTP_CLK_PERIOD_NS_DENOM = 1; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h2; parameter IF_PTP_PERIOD_FNS = 16'h8F5C; @@ -1141,7 +1140,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v index be1d09fd9..282eeda08 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -1094,7 +1093,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index ae24adcbe..6f12f5773 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -137,7 +137,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index 8aa8ca4c3..8c785e102 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -698,7 +698,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index 2c95fcae3..5ad7797d1 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -255,7 +255,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1488,7 +1487,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v index 5b244fe5b..191e4af25 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -1081,7 +1080,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index cee5e0dfc..b73274d19 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index a1729a28b..1df9e424d 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -662,7 +662,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v index c9b15561d..6d4a15460 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v @@ -265,7 +265,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -1573,7 +1572,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index b19cb8eed..a86122bd4 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, @@ -1025,7 +1024,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index c10056880..c3d9b0680 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index 0b29b84bb..c53099325 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -693,7 +693,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index 0364b137f..fca61e597 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -272,7 +272,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1657,7 +1656,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index 5e9d47283..b5731f462 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -1224,7 +1223,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index 33b3c8ee4..da5012058 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index 6b80fb2bc..b11789151 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -709,7 +709,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v index e66d6a163..05db2dd82 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v @@ -276,7 +276,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -1863,7 +1862,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index 8a282db11..d0b52a2ae 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, @@ -980,7 +979,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index e8de2d7d3..6b3457a52 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index f5574158f..5940a33d8 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -687,7 +687,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index 7c54b7b31..e79630106 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -283,7 +283,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1948,7 +1947,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v index 83473995e..0822327b3 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -1179,7 +1178,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile index 78a21e1ad..a480035a9 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py index 3b69cf287..59babf55f 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -703,7 +703,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index a7537ddd5..ff66f43e8 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -328,7 +328,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 512; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -2297,7 +2296,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index cbe280aa7..77edb706e 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, @@ -1380,7 +1379,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index b4d38b6b1..334ffb4de 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index e483ab9ba..67b3e98db 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -689,7 +689,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index 122e99c31..bf20bf3b3 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -335,7 +335,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 512; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -2457,7 +2456,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index d9c7b9da2..3cbee0799 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -1599,7 +1598,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index 262467f1e..05782ff97 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 0 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index c4369982b..407acccbe 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -706,7 +706,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v index 13d9ac833..816c74167 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v @@ -341,7 +341,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 512; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -2476,7 +2475,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v index e88d5647d..c471587d4 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -1594,7 +1593,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile index bc5d0330e..f76ded620 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile @@ -136,7 +136,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py index c5685ce23..1c76e0ece 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -680,7 +680,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 0 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index c5be020c2..7183cfad3 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -219,7 +219,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -979,7 +978,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v index 3e259cd5d..c1500d7e8 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -44,7 +44,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -948,7 +947,6 @@ mqnic_core_axi #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index b9f2c0643..6e64c4b78 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -120,7 +120,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index a170ecb64..c3cc4fa2d 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -455,7 +455,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index 569e759ab..1f3f43952 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -218,7 +218,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -1030,7 +1029,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index ab86c97f4..b488ddf03 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -828,7 +827,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index ae108d0d3..2c8ac2de8 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -132,7 +132,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index 9b58a1694..0b55db2d0 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -660,7 +660,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index 3f9660e74..fb23c3c07 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -209,7 +209,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 32; parameter PTP_CLK_PERIOD_NS_DENOM = 5; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h6; parameter IF_PTP_PERIOD_FNS = 16'h6666; @@ -900,7 +899,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index 0230ae45e..744837950 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -44,7 +44,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -902,7 +901,6 @@ mqnic_core_axi #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index b9f2c0643..6e64c4b78 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -120,7 +120,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 5 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index 7aa0f532c..96320291b 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -455,7 +455,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index 4bcc6d8ce..97c26cbe6 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -294,7 +294,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -1938,7 +1937,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 6f4ba488c..61212b113 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, @@ -1082,7 +1081,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index d67d805bf..848083937 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index 9338ad143..b051cafb0 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -690,7 +690,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index d9a95c636..9182a14d3 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -302,7 +302,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h2; parameter IF_PTP_PERIOD_FNS = 16'h8F5C; @@ -2034,7 +2033,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 55c1f554a..9b633c2a8 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -1288,7 +1287,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index a086503cd..f3a73e6a5 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -137,7 +137,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 97df2ae0b..7fc68f42e 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -706,7 +706,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v index 0da4d2645..3be5e9b8a 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v @@ -311,7 +311,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration @@ -2184,7 +2183,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v index 1f07231df..e1c8e949a 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v @@ -40,7 +40,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, @@ -1347,7 +1346,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile index a14e056c2..38c2e9ce0 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile @@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_SEPARATE_RX_CLOCK := 0 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py index fa040e912..d850fa496 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -685,7 +685,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v index afc0f92cc..a76b8ead3 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v @@ -319,7 +319,6 @@ module fpga # parameter PTP_CLK_PERIOD_NS_NUM = 1024; parameter PTP_CLK_PERIOD_NS_DENOM = 165; parameter PTP_TS_WIDTH = 96; -parameter PTP_USE_SAMPLE_CLOCK = 1; parameter IF_PTP_PERIOD_NS = 6'h2; parameter IF_PTP_PERIOD_FNS = 16'h8F5C; @@ -2360,7 +2359,6 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v index f07eee4ea..d1c9f867a 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v @@ -43,7 +43,6 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_USE_SAMPLE_CLOCK = 1, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -1579,7 +1578,6 @@ mqnic_core_pcie_us #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), .PTP_SEPARATE_TX_CLOCK(0), .PTP_SEPARATE_RX_CLOCK(0), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile index 2a53e518c..4139d303c 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile @@ -137,7 +137,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 export PARAM_PTP_CLOCK_PIPELINE := 0 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_USE_SAMPLE_CLOCK := 1 export PARAM_PTP_PORT_CDC_PIPELINE := 0 export PARAM_PTP_PEROUT_ENABLE := 1 export PARAM_PTP_PEROUT_COUNT := 1 diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py index 41d278092..a48c95514 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -703,7 +703,6 @@ def test_fpga_core(request): parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_USE_SAMPLE_CLOCK'] = 1 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1