diff --git a/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v b/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
index d560cc2f9..4062cb9c7 100644
--- a/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
+++ b/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
@@ -981,10 +981,10 @@ end
 
 generate
 
-if (HAS_COMMON && !GT_GTH) begin : xcvr
+if (HAS_COMMON && !GT_GTH) begin : xcvr_gty_com
 
-    eth_xcvr_gt_full
-    eth_xcvr_gt_full_inst (
+    eth_xcvr_gty_full
+    eth_xcvr_gty_full_inst (
         // Common
         .gtpowergood_out(xcvr_gtpowergood_out),
         .loopback_in(gt_loopback_reg),
@@ -1114,10 +1114,10 @@ if (HAS_COMMON && !GT_GTH) begin : xcvr
     assign xcvr_qpll1clk_out = qpll1_clk;
     assign xcvr_qpll1refclk_out = qpll1_refclk;
 
-end else if (HAS_COMMON && GT_GTH) begin : xcvr
+end else if (HAS_COMMON && GT_GTH) begin : xcvr_gth_com
 
-    eth_xcvr_gt_full
-    eth_xcvr_gt_full_inst (
+    eth_xcvr_gth_full
+    eth_xcvr_gth_full_inst (
         // Common
         .gtpowergood_out(xcvr_gtpowergood_out),
         .loopback_in(gt_loopback_reg),
@@ -1247,10 +1247,10 @@ end else if (HAS_COMMON && GT_GTH) begin : xcvr
     assign xcvr_qpll1clk_out = qpll1_clk;
     assign xcvr_qpll1refclk_out = qpll1_refclk;
 
-end else if (!GT_GTH) begin : xcvr
+end else if (!GT_GTH) begin : xcvr_gty
 
-    eth_xcvr_gt_channel
-    eth_xcvr_gt_channel_inst (
+    eth_xcvr_gty_channel
+    eth_xcvr_gty_channel_inst (
         // Common
         .gtpowergood_out(xcvr_gtpowergood_out),
         .loopback_in(gt_loopback_reg),
@@ -1373,10 +1373,10 @@ end else if (!GT_GTH) begin : xcvr
     assign drp_do_2 = 16'd0;
     assign drp_rdy_2 = 1'b0;
 
-end else begin : xcvr
+end else begin : xcvr_gth
 
-    eth_xcvr_gt_channel
-    eth_xcvr_gt_channel_inst (
+    eth_xcvr_gth_channel
+    eth_xcvr_gth_channel_inst (
         // Common
         .gtpowergood_out(xcvr_gtpowergood_out),
         .loopback_in(gt_loopback_reg),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
index f93dce978..1c2c24743 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
@@ -128,7 +128,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile
index bd48b8162..ff8f8897d 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile
@@ -129,7 +129,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/ADM_PCIE_9V3/fpga_10g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/ADM_PCIE_9V3/fpga_10g/ip/eth_xcvr_gty.tcl
index f7f544cfe..ea679b502 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
index f93dce978..1c2c24743 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
@@ -128,7 +128,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
index bd48b8162..ff8f8897d 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
@@ -129,7 +129,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl
index cbf38c609..52254f917 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}
 
diff --git a/fpga/mqnic/AU200/fpga_10g/fpga/Makefile b/fpga/mqnic/AU200/fpga_10g/fpga/Makefile
index 2ea92a076..837ce857c 100644
--- a/fpga/mqnic/AU200/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/AU200/fpga_10g/fpga/Makefile
@@ -133,7 +133,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
 
 # Configuration
diff --git a/fpga/mqnic/AU280/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/AU280/fpga_10g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gty.tcl
index f7f544cfe..ea679b502 100644
--- a/fpga/mqnic/AU280/fpga_10g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}
 
diff --git a/fpga/mqnic/AU250/fpga_10g/fpga/Makefile b/fpga/mqnic/AU250/fpga_10g/fpga/Makefile
index 03f76703c..8bdfce4df 100644
--- a/fpga/mqnic/AU250/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/AU250/fpga_10g/fpga/Makefile
@@ -133,7 +133,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
 
 # Configuration
diff --git a/fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gty.tcl
index f7f544cfe..ea679b502 100644
--- a/fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}
 
diff --git a/fpga/mqnic/AU280/fpga_10g/fpga/Makefile b/fpga/mqnic/AU280/fpga_10g/fpga/Makefile
index 563a39503..ff3561a8a 100644
--- a/fpga/mqnic/AU280/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/AU280/fpga_10g/fpga/Makefile
@@ -131,7 +131,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
 
 # Configuration
diff --git a/fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/AU280/fpga_10g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/AU280/fpga_10g/ip/eth_xcvr_gty.tcl
index f7f544cfe..ea679b502 100644
--- a/fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/AU280/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}
 
diff --git a/fpga/mqnic/AU50/fpga_10g/fpga/Makefile b/fpga/mqnic/AU50/fpga_10g/fpga/Makefile
index b07278361..ad740ff8f 100644
--- a/fpga/mqnic/AU50/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/AU50/fpga_10g/fpga/Makefile
@@ -131,7 +131,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 IP_TCL_FILES += ip/cms.tcl
 
 # Configuration
diff --git a/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gt.tcl
deleted file mode 100644
index f7f544cfe..000000000
--- a/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gt.tcl
+++ /dev/null
@@ -1,129 +0,0 @@
-# Copyright 2022, The Regents of the University of California.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-#    1. Redistributions of source code must retain the above copyright notice,
-#       this list of conditions and the following disclaimer.
-#
-#    2. Redistributions in binary form must reproduce the above copyright notice,
-#       this list of conditions and the following disclaimer in the documentation
-#       and/or other materials provided with the distribution.
-#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
-# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
-# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-# OF SUCH DAMAGE.
-#
-# The views and conclusions contained in the software and documentation are those
-# of the authors and should not be interpreted as representing official policies,
-# either expressed or implied, of The Regents of the University of California.
-
-set base_name {eth_xcvr_gt}
-
-set preset {GTY-10GBASE-R}
-
-set freerun_freq {125}
-set line_rate {10.3125}
-set sec_line_rate {0}
-set refclk_freq {161.1328125}
-set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
-set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
-set user_data_width {64}
-set int_data_width $user_data_width
-set rx_eq_mode {DFE}
-set extra_ports [list]
-set extra_pll_ports [list]
-# DRP connections
-lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
-lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
-# PLL reset and power down
-lappend extra_pll_ports qpll0reset_in qpll1reset_in
-lappend extra_pll_ports qpll0pd_in qpll1pd_in
-# PLL clocking
-lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
-lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
-# channel reset
-lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
-lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
-# channel power down
-lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
-# channel clock selection
-lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
-# channel polarity
-lappend extra_ports txpolarity_in rxpolarity_in
-# channel TX driver
-lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
-# channel CDR
-lappend extra_ports rxcdrlock_out rxcdrhold_in
-# channel EQ
-lappend extra_ports rxlpmen_in
-# channel digital monitor
-lappend extra_ports dmonitorout_out
-# channel PRBS
-lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
-# channel eye scan
-lappend extra_ports eyescandataerror_out
-# channel loopback
-lappend extra_ports loopback_in
-
-set config [dict create]
-
-dict set config TX_LINE_RATE $line_rate
-dict set config TX_REFCLK_FREQUENCY $refclk_freq
-dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
-dict set config TX_USER_DATA_WIDTH $user_data_width
-dict set config TX_INT_DATA_WIDTH $int_data_width
-dict set config RX_LINE_RATE $line_rate
-dict set config RX_REFCLK_FREQUENCY $refclk_freq
-dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
-dict set config RX_USER_DATA_WIDTH $user_data_width
-dict set config RX_INT_DATA_WIDTH $int_data_width
-dict set config RX_EQ_MODE $rx_eq_mode
-if {$sec_line_rate != 0} {
-    dict set config SECONDARY_QPLL_ENABLE true
-    dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
-    dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
-    dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
-} else {
-    dict set config SECONDARY_QPLL_ENABLE false
-}
-dict set config ENABLE_OPTIONAL_PORTS $extra_ports
-dict set config LOCATE_COMMON {CORE}
-dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
-dict set config LOCATE_TX_USER_CLOCKING {CORE}
-dict set config LOCATE_RX_USER_CLOCKING {CORE}
-dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
-dict set config FREERUN_FREQUENCY $freerun_freq
-dict set config DISABLE_LOC_XDC {1}
-
-proc create_gtwizard_ip {name preset config} {
-    create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
-    set ip [get_ips $name]
-    set_property CONFIG.preset $preset $ip
-    set config_list {}
-    dict for {name value} $config {
-        lappend config_list "CONFIG.${name}" $value
-    }
-    set_property -dict $config_list $ip
-}
-
-# variant with channel and common
-dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
-dict set config LOCATE_COMMON {CORE}
-
-create_gtwizard_ip "${base_name}_full" $preset $config
-
-# variant with channel only
-dict set config ENABLE_OPTIONAL_PORTS $extra_ports
-dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
-
-create_gtwizard_ip "${base_name}_channel" $preset $config
diff --git a/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gty.tcl
new file mode 100644
index 000000000..ea679b502
--- /dev/null
+++ b/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -0,0 +1,129 @@
+# Copyright 2022, The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#    1. Redistributions of source code must retain the above copyright notice,
+#       this list of conditions and the following disclaimer.
+#
+#    2. Redistributions in binary form must reproduce the above copyright notice,
+#       this list of conditions and the following disclaimer in the documentation
+#       and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+# OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of The Regents of the University of California.
+
+set base_name {eth_xcvr_gty}
+
+set preset {GTY-10GBASE-R}
+
+set freerun_freq {125}
+set line_rate {10.3125}
+set sec_line_rate {0}
+set refclk_freq {161.1328125}
+set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
+set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
+set user_data_width {64}
+set int_data_width $user_data_width
+set rx_eq_mode {DFE}
+set extra_ports [list]
+set extra_pll_ports [list]
+# DRP connections
+lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
+lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
+# PLL reset and power down
+lappend extra_pll_ports qpll0reset_in qpll1reset_in
+lappend extra_pll_ports qpll0pd_in qpll1pd_in
+# PLL clocking
+lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
+lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
+# channel reset
+lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
+lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
+# channel power down
+lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
+# channel clock selection
+lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
+# channel polarity
+lappend extra_ports txpolarity_in rxpolarity_in
+# channel TX driver
+lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
+# channel CDR
+lappend extra_ports rxcdrlock_out rxcdrhold_in
+# channel EQ
+lappend extra_ports rxlpmen_in
+# channel digital monitor
+lappend extra_ports dmonitorout_out
+# channel PRBS
+lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
+# channel eye scan
+lappend extra_ports eyescandataerror_out
+# channel loopback
+lappend extra_ports loopback_in
+
+set config [dict create]
+
+dict set config TX_LINE_RATE $line_rate
+dict set config TX_REFCLK_FREQUENCY $refclk_freq
+dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
+dict set config TX_USER_DATA_WIDTH $user_data_width
+dict set config TX_INT_DATA_WIDTH $int_data_width
+dict set config RX_LINE_RATE $line_rate
+dict set config RX_REFCLK_FREQUENCY $refclk_freq
+dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
+dict set config RX_USER_DATA_WIDTH $user_data_width
+dict set config RX_INT_DATA_WIDTH $int_data_width
+dict set config RX_EQ_MODE $rx_eq_mode
+if {$sec_line_rate != 0} {
+    dict set config SECONDARY_QPLL_ENABLE true
+    dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
+    dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
+    dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
+} else {
+    dict set config SECONDARY_QPLL_ENABLE false
+}
+dict set config ENABLE_OPTIONAL_PORTS $extra_ports
+dict set config LOCATE_COMMON {CORE}
+dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
+dict set config LOCATE_TX_USER_CLOCKING {CORE}
+dict set config LOCATE_RX_USER_CLOCKING {CORE}
+dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
+dict set config FREERUN_FREQUENCY $freerun_freq
+dict set config DISABLE_LOC_XDC {1}
+
+proc create_gtwizard_ip {name preset config} {
+    create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
+    set ip [get_ips $name]
+    set_property CONFIG.preset $preset $ip
+    set config_list {}
+    dict for {name value} $config {
+        lappend config_list "CONFIG.${name}" $value
+    }
+    set_property -dict $config_list $ip
+}
+
+# variant with channel and common
+dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
+dict set config LOCATE_COMMON {CORE}
+
+create_gtwizard_ip "${base_name}_full" $preset $config
+
+# variant with channel only
+dict set config ENABLE_OPTIONAL_PORTS $extra_ports
+dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
+
+create_gtwizard_ip "${base_name}_channel" $preset $config
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
index 4e15b96b4..943baa3b1 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
+++ b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
@@ -126,7 +126,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gth.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/ip/eth_xcvr_gt.tcl b/fpga/mqnic/ExaNIC_X10/fpga/ip/eth_xcvr_gth.tcl
similarity index 99%
rename from fpga/mqnic/ExaNIC_X10/fpga/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/ExaNIC_X10/fpga/ip/eth_xcvr_gth.tcl
index da004fb1e..0294ea8d5 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/ExaNIC_X10/fpga/ip/eth_xcvr_gth.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gth}
 
 set preset {GTH-10GBASE-R}
 
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
index cc824fd8c..a9d8cfe65 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
@@ -126,7 +126,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gt.tcl
deleted file mode 100644
index f7f544cfe..000000000
--- a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gt.tcl
+++ /dev/null
@@ -1,129 +0,0 @@
-# Copyright 2022, The Regents of the University of California.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-#    1. Redistributions of source code must retain the above copyright notice,
-#       this list of conditions and the following disclaimer.
-#
-#    2. Redistributions in binary form must reproduce the above copyright notice,
-#       this list of conditions and the following disclaimer in the documentation
-#       and/or other materials provided with the distribution.
-#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
-# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
-# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-# OF SUCH DAMAGE.
-#
-# The views and conclusions contained in the software and documentation are those
-# of the authors and should not be interpreted as representing official policies,
-# either expressed or implied, of The Regents of the University of California.
-
-set base_name {eth_xcvr_gt}
-
-set preset {GTY-10GBASE-R}
-
-set freerun_freq {125}
-set line_rate {10.3125}
-set sec_line_rate {0}
-set refclk_freq {161.1328125}
-set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
-set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
-set user_data_width {64}
-set int_data_width $user_data_width
-set rx_eq_mode {DFE}
-set extra_ports [list]
-set extra_pll_ports [list]
-# DRP connections
-lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
-lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
-# PLL reset and power down
-lappend extra_pll_ports qpll0reset_in qpll1reset_in
-lappend extra_pll_ports qpll0pd_in qpll1pd_in
-# PLL clocking
-lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
-lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
-# channel reset
-lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
-lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
-# channel power down
-lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
-# channel clock selection
-lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
-# channel polarity
-lappend extra_ports txpolarity_in rxpolarity_in
-# channel TX driver
-lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
-# channel CDR
-lappend extra_ports rxcdrlock_out rxcdrhold_in
-# channel EQ
-lappend extra_ports rxlpmen_in
-# channel digital monitor
-lappend extra_ports dmonitorout_out
-# channel PRBS
-lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
-# channel eye scan
-lappend extra_ports eyescandataerror_out
-# channel loopback
-lappend extra_ports loopback_in
-
-set config [dict create]
-
-dict set config TX_LINE_RATE $line_rate
-dict set config TX_REFCLK_FREQUENCY $refclk_freq
-dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
-dict set config TX_USER_DATA_WIDTH $user_data_width
-dict set config TX_INT_DATA_WIDTH $int_data_width
-dict set config RX_LINE_RATE $line_rate
-dict set config RX_REFCLK_FREQUENCY $refclk_freq
-dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
-dict set config RX_USER_DATA_WIDTH $user_data_width
-dict set config RX_INT_DATA_WIDTH $int_data_width
-dict set config RX_EQ_MODE $rx_eq_mode
-if {$sec_line_rate != 0} {
-    dict set config SECONDARY_QPLL_ENABLE true
-    dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
-    dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
-    dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
-} else {
-    dict set config SECONDARY_QPLL_ENABLE false
-}
-dict set config ENABLE_OPTIONAL_PORTS $extra_ports
-dict set config LOCATE_COMMON {CORE}
-dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
-dict set config LOCATE_TX_USER_CLOCKING {CORE}
-dict set config LOCATE_RX_USER_CLOCKING {CORE}
-dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
-dict set config FREERUN_FREQUENCY $freerun_freq
-dict set config DISABLE_LOC_XDC {1}
-
-proc create_gtwizard_ip {name preset config} {
-    create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
-    set ip [get_ips $name]
-    set_property CONFIG.preset $preset $ip
-    set config_list {}
-    dict for {name value} $config {
-        lappend config_list "CONFIG.${name}" $value
-    }
-    set_property -dict $config_list $ip
-}
-
-# variant with channel and common
-dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
-dict set config LOCATE_COMMON {CORE}
-
-create_gtwizard_ip "${base_name}_full" $preset $config
-
-# variant with channel only
-dict set config ENABLE_OPTIONAL_PORTS $extra_ports
-dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
-
-create_gtwizard_ip "${base_name}_channel" $preset $config
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gty.tcl
new file mode 100644
index 000000000..ea679b502
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -0,0 +1,129 @@
+# Copyright 2022, The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#    1. Redistributions of source code must retain the above copyright notice,
+#       this list of conditions and the following disclaimer.
+#
+#    2. Redistributions in binary form must reproduce the above copyright notice,
+#       this list of conditions and the following disclaimer in the documentation
+#       and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+# OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of The Regents of the University of California.
+
+set base_name {eth_xcvr_gty}
+
+set preset {GTY-10GBASE-R}
+
+set freerun_freq {125}
+set line_rate {10.3125}
+set sec_line_rate {0}
+set refclk_freq {161.1328125}
+set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
+set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
+set user_data_width {64}
+set int_data_width $user_data_width
+set rx_eq_mode {DFE}
+set extra_ports [list]
+set extra_pll_ports [list]
+# DRP connections
+lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
+lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
+# PLL reset and power down
+lappend extra_pll_ports qpll0reset_in qpll1reset_in
+lappend extra_pll_ports qpll0pd_in qpll1pd_in
+# PLL clocking
+lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
+lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
+# channel reset
+lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
+lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
+# channel power down
+lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
+# channel clock selection
+lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
+# channel polarity
+lappend extra_ports txpolarity_in rxpolarity_in
+# channel TX driver
+lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
+# channel CDR
+lappend extra_ports rxcdrlock_out rxcdrhold_in
+# channel EQ
+lappend extra_ports rxlpmen_in
+# channel digital monitor
+lappend extra_ports dmonitorout_out
+# channel PRBS
+lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
+# channel eye scan
+lappend extra_ports eyescandataerror_out
+# channel loopback
+lappend extra_ports loopback_in
+
+set config [dict create]
+
+dict set config TX_LINE_RATE $line_rate
+dict set config TX_REFCLK_FREQUENCY $refclk_freq
+dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
+dict set config TX_USER_DATA_WIDTH $user_data_width
+dict set config TX_INT_DATA_WIDTH $int_data_width
+dict set config RX_LINE_RATE $line_rate
+dict set config RX_REFCLK_FREQUENCY $refclk_freq
+dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
+dict set config RX_USER_DATA_WIDTH $user_data_width
+dict set config RX_INT_DATA_WIDTH $int_data_width
+dict set config RX_EQ_MODE $rx_eq_mode
+if {$sec_line_rate != 0} {
+    dict set config SECONDARY_QPLL_ENABLE true
+    dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
+    dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
+    dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
+} else {
+    dict set config SECONDARY_QPLL_ENABLE false
+}
+dict set config ENABLE_OPTIONAL_PORTS $extra_ports
+dict set config LOCATE_COMMON {CORE}
+dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
+dict set config LOCATE_TX_USER_CLOCKING {CORE}
+dict set config LOCATE_RX_USER_CLOCKING {CORE}
+dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
+dict set config FREERUN_FREQUENCY $freerun_freq
+dict set config DISABLE_LOC_XDC {1}
+
+proc create_gtwizard_ip {name preset config} {
+    create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
+    set ip [get_ips $name]
+    set_property CONFIG.preset $preset $ip
+    set config_list {}
+    dict for {name value} $config {
+        lappend config_list "CONFIG.${name}" $value
+    }
+    set_property -dict $config_list $ip
+}
+
+# variant with channel and common
+dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
+dict set config LOCATE_COMMON {CORE}
+
+create_gtwizard_ip "${base_name}_full" $preset $config
+
+# variant with channel only
+dict set config ENABLE_OPTIONAL_PORTS $extra_ports
+dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
+
+create_gtwizard_ip "${base_name}_channel" $preset $config
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
index cc824fd8c..a9d8cfe65 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
@@ -126,7 +126,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gty.tcl
index cbf38c609..52254f917 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}
 
diff --git a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
index dfcf9ac0c..e582623c9 100644
--- a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
@@ -127,7 +127,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/VCU108/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/VCU108/fpga_10g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/VCU108/fpga_10g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/VCU108/fpga_10g/ip/eth_xcvr_gty.tcl
index c297ad17f..47d04e21c 100644
--- a/fpga/mqnic/VCU108/fpga_10g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/VCU108/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}
 
diff --git a/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile
index bde6f9009..3358d9855 100644
--- a/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile
@@ -128,7 +128,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/VCU118/fpga_10g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/VCU118/fpga_10g/ip/eth_xcvr_gty.tcl
index c297ad17f..47d04e21c 100644
--- a/fpga/mqnic/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/VCU118/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}
 
diff --git a/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile
index dc3aa9ac9..ea1e13147 100644
--- a/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile
@@ -129,7 +129,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/VCU1525/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/VCU1525/fpga_10g/ip/eth_xcvr_gt.tcl
deleted file mode 100644
index f7f544cfe..000000000
--- a/fpga/mqnic/VCU1525/fpga_10g/ip/eth_xcvr_gt.tcl
+++ /dev/null
@@ -1,129 +0,0 @@
-# Copyright 2022, The Regents of the University of California.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-#    1. Redistributions of source code must retain the above copyright notice,
-#       this list of conditions and the following disclaimer.
-#
-#    2. Redistributions in binary form must reproduce the above copyright notice,
-#       this list of conditions and the following disclaimer in the documentation
-#       and/or other materials provided with the distribution.
-#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
-# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
-# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-# OF SUCH DAMAGE.
-#
-# The views and conclusions contained in the software and documentation are those
-# of the authors and should not be interpreted as representing official policies,
-# either expressed or implied, of The Regents of the University of California.
-
-set base_name {eth_xcvr_gt}
-
-set preset {GTY-10GBASE-R}
-
-set freerun_freq {125}
-set line_rate {10.3125}
-set sec_line_rate {0}
-set refclk_freq {161.1328125}
-set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
-set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
-set user_data_width {64}
-set int_data_width $user_data_width
-set rx_eq_mode {DFE}
-set extra_ports [list]
-set extra_pll_ports [list]
-# DRP connections
-lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
-lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
-# PLL reset and power down
-lappend extra_pll_ports qpll0reset_in qpll1reset_in
-lappend extra_pll_ports qpll0pd_in qpll1pd_in
-# PLL clocking
-lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
-lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
-# channel reset
-lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
-lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
-# channel power down
-lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
-# channel clock selection
-lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
-# channel polarity
-lappend extra_ports txpolarity_in rxpolarity_in
-# channel TX driver
-lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
-# channel CDR
-lappend extra_ports rxcdrlock_out rxcdrhold_in
-# channel EQ
-lappend extra_ports rxlpmen_in
-# channel digital monitor
-lappend extra_ports dmonitorout_out
-# channel PRBS
-lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
-# channel eye scan
-lappend extra_ports eyescandataerror_out
-# channel loopback
-lappend extra_ports loopback_in
-
-set config [dict create]
-
-dict set config TX_LINE_RATE $line_rate
-dict set config TX_REFCLK_FREQUENCY $refclk_freq
-dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
-dict set config TX_USER_DATA_WIDTH $user_data_width
-dict set config TX_INT_DATA_WIDTH $int_data_width
-dict set config RX_LINE_RATE $line_rate
-dict set config RX_REFCLK_FREQUENCY $refclk_freq
-dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
-dict set config RX_USER_DATA_WIDTH $user_data_width
-dict set config RX_INT_DATA_WIDTH $int_data_width
-dict set config RX_EQ_MODE $rx_eq_mode
-if {$sec_line_rate != 0} {
-    dict set config SECONDARY_QPLL_ENABLE true
-    dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
-    dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
-    dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
-} else {
-    dict set config SECONDARY_QPLL_ENABLE false
-}
-dict set config ENABLE_OPTIONAL_PORTS $extra_ports
-dict set config LOCATE_COMMON {CORE}
-dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
-dict set config LOCATE_TX_USER_CLOCKING {CORE}
-dict set config LOCATE_RX_USER_CLOCKING {CORE}
-dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
-dict set config FREERUN_FREQUENCY $freerun_freq
-dict set config DISABLE_LOC_XDC {1}
-
-proc create_gtwizard_ip {name preset config} {
-    create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
-    set ip [get_ips $name]
-    set_property CONFIG.preset $preset $ip
-    set config_list {}
-    dict for {name value} $config {
-        lappend config_list "CONFIG.${name}" $value
-    }
-    set_property -dict $config_list $ip
-}
-
-# variant with channel and common
-dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
-dict set config LOCATE_COMMON {CORE}
-
-create_gtwizard_ip "${base_name}_full" $preset $config
-
-# variant with channel only
-dict set config ENABLE_OPTIONAL_PORTS $extra_ports
-dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
-
-create_gtwizard_ip "${base_name}_channel" $preset $config
diff --git a/fpga/mqnic/VCU1525/fpga_10g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/VCU1525/fpga_10g/ip/eth_xcvr_gty.tcl
new file mode 100644
index 000000000..ea679b502
--- /dev/null
+++ b/fpga/mqnic/VCU1525/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -0,0 +1,129 @@
+# Copyright 2022, The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#    1. Redistributions of source code must retain the above copyright notice,
+#       this list of conditions and the following disclaimer.
+#
+#    2. Redistributions in binary form must reproduce the above copyright notice,
+#       this list of conditions and the following disclaimer in the documentation
+#       and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+# OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of The Regents of the University of California.
+
+set base_name {eth_xcvr_gty}
+
+set preset {GTY-10GBASE-R}
+
+set freerun_freq {125}
+set line_rate {10.3125}
+set sec_line_rate {0}
+set refclk_freq {161.1328125}
+set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
+set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
+set user_data_width {64}
+set int_data_width $user_data_width
+set rx_eq_mode {DFE}
+set extra_ports [list]
+set extra_pll_ports [list]
+# DRP connections
+lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
+lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
+# PLL reset and power down
+lappend extra_pll_ports qpll0reset_in qpll1reset_in
+lappend extra_pll_ports qpll0pd_in qpll1pd_in
+# PLL clocking
+lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
+lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
+# channel reset
+lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
+lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
+# channel power down
+lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
+# channel clock selection
+lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
+# channel polarity
+lappend extra_ports txpolarity_in rxpolarity_in
+# channel TX driver
+lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
+# channel CDR
+lappend extra_ports rxcdrlock_out rxcdrhold_in
+# channel EQ
+lappend extra_ports rxlpmen_in
+# channel digital monitor
+lappend extra_ports dmonitorout_out
+# channel PRBS
+lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
+# channel eye scan
+lappend extra_ports eyescandataerror_out
+# channel loopback
+lappend extra_ports loopback_in
+
+set config [dict create]
+
+dict set config TX_LINE_RATE $line_rate
+dict set config TX_REFCLK_FREQUENCY $refclk_freq
+dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
+dict set config TX_USER_DATA_WIDTH $user_data_width
+dict set config TX_INT_DATA_WIDTH $int_data_width
+dict set config RX_LINE_RATE $line_rate
+dict set config RX_REFCLK_FREQUENCY $refclk_freq
+dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
+dict set config RX_USER_DATA_WIDTH $user_data_width
+dict set config RX_INT_DATA_WIDTH $int_data_width
+dict set config RX_EQ_MODE $rx_eq_mode
+if {$sec_line_rate != 0} {
+    dict set config SECONDARY_QPLL_ENABLE true
+    dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
+    dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
+    dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
+} else {
+    dict set config SECONDARY_QPLL_ENABLE false
+}
+dict set config ENABLE_OPTIONAL_PORTS $extra_ports
+dict set config LOCATE_COMMON {CORE}
+dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
+dict set config LOCATE_TX_USER_CLOCKING {CORE}
+dict set config LOCATE_RX_USER_CLOCKING {CORE}
+dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
+dict set config FREERUN_FREQUENCY $freerun_freq
+dict set config DISABLE_LOC_XDC {1}
+
+proc create_gtwizard_ip {name preset config} {
+    create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
+    set ip [get_ips $name]
+    set_property CONFIG.preset $preset $ip
+    set config_list {}
+    dict for {name value} $config {
+        lappend config_list "CONFIG.${name}" $value
+    }
+    set_property -dict $config_list $ip
+}
+
+# variant with channel and common
+dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
+dict set config LOCATE_COMMON {CORE}
+
+create_gtwizard_ip "${base_name}_full" $preset $config
+
+# variant with channel only
+dict set config ENABLE_OPTIONAL_PORTS $extra_ports
+dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
+
+create_gtwizard_ip "${base_name}_channel" $preset $config
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
index 6ad1d015c..a6447fa20 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
@@ -126,7 +126,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gth.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gt.tcl b/fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl
similarity index 99%
rename from fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl
index df37dec9c..3209d5d72 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gth}
 
 set preset {GTH-10GBASE-R}
 
diff --git a/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile
index 2ec552a93..57b881af6 100644
--- a/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile
@@ -130,7 +130,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile
index 5a19b33ae..95ced780c 100644
--- a/fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile
@@ -131,7 +131,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/fb2CG/fpga_10g/ip/eth_xcvr_gt.tcl
deleted file mode 100644
index f7f544cfe..000000000
--- a/fpga/mqnic/fb2CG/fpga_10g/ip/eth_xcvr_gt.tcl
+++ /dev/null
@@ -1,129 +0,0 @@
-# Copyright 2022, The Regents of the University of California.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-#    1. Redistributions of source code must retain the above copyright notice,
-#       this list of conditions and the following disclaimer.
-#
-#    2. Redistributions in binary form must reproduce the above copyright notice,
-#       this list of conditions and the following disclaimer in the documentation
-#       and/or other materials provided with the distribution.
-#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
-# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
-# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-# OF SUCH DAMAGE.
-#
-# The views and conclusions contained in the software and documentation are those
-# of the authors and should not be interpreted as representing official policies,
-# either expressed or implied, of The Regents of the University of California.
-
-set base_name {eth_xcvr_gt}
-
-set preset {GTY-10GBASE-R}
-
-set freerun_freq {125}
-set line_rate {10.3125}
-set sec_line_rate {0}
-set refclk_freq {161.1328125}
-set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
-set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
-set user_data_width {64}
-set int_data_width $user_data_width
-set rx_eq_mode {DFE}
-set extra_ports [list]
-set extra_pll_ports [list]
-# DRP connections
-lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
-lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
-# PLL reset and power down
-lappend extra_pll_ports qpll0reset_in qpll1reset_in
-lappend extra_pll_ports qpll0pd_in qpll1pd_in
-# PLL clocking
-lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
-lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
-# channel reset
-lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
-lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
-# channel power down
-lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
-# channel clock selection
-lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
-# channel polarity
-lappend extra_ports txpolarity_in rxpolarity_in
-# channel TX driver
-lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
-# channel CDR
-lappend extra_ports rxcdrlock_out rxcdrhold_in
-# channel EQ
-lappend extra_ports rxlpmen_in
-# channel digital monitor
-lappend extra_ports dmonitorout_out
-# channel PRBS
-lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
-# channel eye scan
-lappend extra_ports eyescandataerror_out
-# channel loopback
-lappend extra_ports loopback_in
-
-set config [dict create]
-
-dict set config TX_LINE_RATE $line_rate
-dict set config TX_REFCLK_FREQUENCY $refclk_freq
-dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
-dict set config TX_USER_DATA_WIDTH $user_data_width
-dict set config TX_INT_DATA_WIDTH $int_data_width
-dict set config RX_LINE_RATE $line_rate
-dict set config RX_REFCLK_FREQUENCY $refclk_freq
-dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
-dict set config RX_USER_DATA_WIDTH $user_data_width
-dict set config RX_INT_DATA_WIDTH $int_data_width
-dict set config RX_EQ_MODE $rx_eq_mode
-if {$sec_line_rate != 0} {
-    dict set config SECONDARY_QPLL_ENABLE true
-    dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
-    dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
-    dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
-} else {
-    dict set config SECONDARY_QPLL_ENABLE false
-}
-dict set config ENABLE_OPTIONAL_PORTS $extra_ports
-dict set config LOCATE_COMMON {CORE}
-dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
-dict set config LOCATE_TX_USER_CLOCKING {CORE}
-dict set config LOCATE_RX_USER_CLOCKING {CORE}
-dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
-dict set config FREERUN_FREQUENCY $freerun_freq
-dict set config DISABLE_LOC_XDC {1}
-
-proc create_gtwizard_ip {name preset config} {
-    create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
-    set ip [get_ips $name]
-    set_property CONFIG.preset $preset $ip
-    set config_list {}
-    dict for {name value} $config {
-        lappend config_list "CONFIG.${name}" $value
-    }
-    set_property -dict $config_list $ip
-}
-
-# variant with channel and common
-dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
-dict set config LOCATE_COMMON {CORE}
-
-create_gtwizard_ip "${base_name}_full" $preset $config
-
-# variant with channel only
-dict set config ENABLE_OPTIONAL_PORTS $extra_ports
-dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
-
-create_gtwizard_ip "${base_name}_channel" $preset $config
diff --git a/fpga/mqnic/fb2CG/fpga_10g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/fb2CG/fpga_10g/ip/eth_xcvr_gty.tcl
new file mode 100644
index 000000000..ea679b502
--- /dev/null
+++ b/fpga/mqnic/fb2CG/fpga_10g/ip/eth_xcvr_gty.tcl
@@ -0,0 +1,129 @@
+# Copyright 2022, The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#    1. Redistributions of source code must retain the above copyright notice,
+#       this list of conditions and the following disclaimer.
+#
+#    2. Redistributions in binary form must reproduce the above copyright notice,
+#       this list of conditions and the following disclaimer in the documentation
+#       and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+# OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of The Regents of the University of California.
+
+set base_name {eth_xcvr_gty}
+
+set preset {GTY-10GBASE-R}
+
+set freerun_freq {125}
+set line_rate {10.3125}
+set sec_line_rate {0}
+set refclk_freq {161.1328125}
+set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
+set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
+set user_data_width {64}
+set int_data_width $user_data_width
+set rx_eq_mode {DFE}
+set extra_ports [list]
+set extra_pll_ports [list]
+# DRP connections
+lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
+lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
+# PLL reset and power down
+lappend extra_pll_ports qpll0reset_in qpll1reset_in
+lappend extra_pll_ports qpll0pd_in qpll1pd_in
+# PLL clocking
+lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
+lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
+# channel reset
+lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
+lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
+# channel power down
+lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
+# channel clock selection
+lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
+# channel polarity
+lappend extra_ports txpolarity_in rxpolarity_in
+# channel TX driver
+lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
+# channel CDR
+lappend extra_ports rxcdrlock_out rxcdrhold_in
+# channel EQ
+lappend extra_ports rxlpmen_in
+# channel digital monitor
+lappend extra_ports dmonitorout_out
+# channel PRBS
+lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
+# channel eye scan
+lappend extra_ports eyescandataerror_out
+# channel loopback
+lappend extra_ports loopback_in
+
+set config [dict create]
+
+dict set config TX_LINE_RATE $line_rate
+dict set config TX_REFCLK_FREQUENCY $refclk_freq
+dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
+dict set config TX_USER_DATA_WIDTH $user_data_width
+dict set config TX_INT_DATA_WIDTH $int_data_width
+dict set config RX_LINE_RATE $line_rate
+dict set config RX_REFCLK_FREQUENCY $refclk_freq
+dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
+dict set config RX_USER_DATA_WIDTH $user_data_width
+dict set config RX_INT_DATA_WIDTH $int_data_width
+dict set config RX_EQ_MODE $rx_eq_mode
+if {$sec_line_rate != 0} {
+    dict set config SECONDARY_QPLL_ENABLE true
+    dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
+    dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
+    dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
+} else {
+    dict set config SECONDARY_QPLL_ENABLE false
+}
+dict set config ENABLE_OPTIONAL_PORTS $extra_ports
+dict set config LOCATE_COMMON {CORE}
+dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
+dict set config LOCATE_TX_USER_CLOCKING {CORE}
+dict set config LOCATE_RX_USER_CLOCKING {CORE}
+dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
+dict set config FREERUN_FREQUENCY $freerun_freq
+dict set config DISABLE_LOC_XDC {1}
+
+proc create_gtwizard_ip {name preset config} {
+    create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
+    set ip [get_ips $name]
+    set_property CONFIG.preset $preset $ip
+    set config_list {}
+    dict for {name value} $config {
+        lappend config_list "CONFIG.${name}" $value
+    }
+    set_property -dict $config_list $ip
+}
+
+# variant with channel and common
+dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
+dict set config LOCATE_COMMON {CORE}
+
+create_gtwizard_ip "${base_name}_full" $preset $config
+
+# variant with channel only
+dict set config ENABLE_OPTIONAL_PORTS $extra_ports
+dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
+
+create_gtwizard_ip "${base_name}_channel" $preset $config
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
index 2ec552a93..57b881af6 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
@@ -130,7 +130,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
index 5a19b33ae..95ced780c 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
@@ -131,7 +131,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
-IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gty.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl
similarity index 99%
rename from fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gt.tcl
rename to fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl
index cbf38c609..52254f917 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gt.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl
@@ -27,7 +27,7 @@
 # of the authors and should not be interpreted as representing official policies,
 # either expressed or implied, of The Regents of the University of California.
 
-set base_name {eth_xcvr_gt}
+set base_name {eth_xcvr_gty}
 
 set preset {GTY-10GBASE-R}