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Update timing parameters for async FIFO to reflect new pipeline register naming

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Alex Forencich 2020-09-07 18:54:32 -07:00
parent 71b6b9f6f2
commit da152a8546
1 changed files with 1 additions and 1 deletions
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syn/axis_async_fifo.tcl
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@ -59,7 +59,7 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo ||
set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_sync_gray_reg_reg[*]"] -to [get_cells $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]] $read_clk_period
# output register (needed for distributed RAM sync write/async read)
set output_reg_ffs [get_cells -quiet "$fifo_inst/mem_read_data_reg_reg[*]"]
set output_reg_ffs [get_cells -quiet "$fifo_inst/m_axis_pipe_reg_reg[0][*]"]
if {[llength $output_reg_ffs]} {
set_false_path -from $write_clk -to $output_reg_ffs