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merged changes in axis

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This commit is contained in:
Alex Forencich 2023-02-17 16:03:28 -08:00
commit db818b2f53
22 changed files with 266 additions and 267 deletions
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2
lib/axis/.github/workflows/regression-tests.yml vendored
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@ -5,7 +5,7 @@ on: [push, pull_request]
jobs:
build:
name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10)
runs-on: ubuntu-20.04
runs-on: ubuntu-22.04
strategy:
matrix:

25
lib/axis/tb/axis_adapter/Makefile
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@ -32,19 +32,18 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_S_DATA_WIDTH := 8
export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH := 8
export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

28
lib/axis/tb/axis_arb_mux/Makefile
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@ -38,20 +38,20 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 8
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_LAST_ENABLE ?= 1
export PARAM_UPDATE_TID ?= 1
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_S_ID_WIDTH := 8
export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_LAST_ENABLE := 1
export PARAM_UPDATE_TID := 1
export PARAM_ARB_TYPE_ROUND_ROBIN := 0
export PARAM_ARB_LSB_HIGH_PRIORITY := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

38
lib/axis/tb/axis_async_fifo/Makefile
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@ -32,25 +32,25 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_RAM_PIPELINE ?= 1
export PARAM_OUTPUT_FIFO_ENABLE ?= 0
export PARAM_FRAME_FIFO ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_DEPTH := 1024
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_ENABLE := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

44
lib/axis/tb/axis_async_fifo_adapter/Makefile
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@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../rtl/axis_adapter.v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_RAM_PIPELINE ?= 1
export PARAM_OUTPUT_FIFO_ENABLE ?= 0
export PARAM_FRAME_FIFO ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_DEPTH := 1024
export PARAM_S_DATA_WIDTH := 8
export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH := 8
export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_ENABLE := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
lib/axis/tb/axis_broadcast/Makefile
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@ -36,16 +36,16 @@ VERILOG_SOURCES += $(WRAPPER).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
lib/axis/tb/axis_cobs_decode/Makefile
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@ -32,7 +32,7 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
# export PARAM_APPEND_ZERO ?= 0
# export PARAM_NAME := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
lib/axis/tb/axis_cobs_encode/Makefile
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@ -33,7 +33,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/axis_fifo.v
# module parameters
export PARAM_APPEND_ZERO ?= 0
export PARAM_APPEND_ZERO := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
lib/axis/tb/axis_demux/Makefile
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@ -36,17 +36,17 @@ VERILOG_SOURCES += $(WRAPPER).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_M_DEST_WIDTH ?= 8
export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())")
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_TDEST_ROUTE ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_M_DEST_WIDTH := 8
export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())")
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_TDEST_ROUTE := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

38
lib/axis/tb/axis_fifo/Makefile
View File

@ -32,25 +32,25 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_RAM_PIPELINE ?= 1
export PARAM_OUTPUT_FIFO_ENABLE ?= 0
export PARAM_FRAME_FIFO ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_DEPTH := 1024
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_ENABLE := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

44
lib/axis/tb/axis_fifo_adapter/Makefile
View File

@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v
VERILOG_SOURCES += ../../rtl/axis_adapter.v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_RAM_PIPELINE ?= 1
export PARAM_OUTPUT_FIFO_ENABLE ?= 0
export PARAM_FRAME_FIFO ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_DEPTH := 1024
export PARAM_S_DATA_WIDTH := 8
export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH := 8
export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_ENABLE := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
lib/axis/tb/axis_frame_length_adjust/Makefile
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@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_LEN_WIDTH ?= 16
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_LEN_WIDTH := 16
ifeq ($(SIM), icarus)
PLUSARGS += -fst

24
lib/axis/tb/axis_frame_length_adjust_fifo/Makefile
View File

@ -34,18 +34,18 @@ VERILOG_SOURCES += ../../rtl/axis_frame_length_adjust.v
VERILOG_SOURCES += ../../rtl/axis_fifo.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_LEN_WIDTH ?= 16
export PARAM_FRAME_FIFO_DEPTH ?= 1024
export PARAM_HEADER_FIFO_DEPTH ?= 8
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_LEN_WIDTH := 16
export PARAM_FRAME_FIFO_DEPTH := 1024
export PARAM_HEADER_FIFO_DEPTH := 8
ifeq ($(SIM), icarus)
PLUSARGS += -fst

18
lib/axis/tb/axis_mux/Makefile
View File

@ -36,15 +36,15 @@ VERILOG_SOURCES += $(WRAPPER).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
lib/axis/tb/axis_pipeline_fifo/Makefile
View File

@ -32,17 +32,17 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_LENGTH ?= 2
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_LENGTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

24
lib/axis/tb/axis_pipeline_register/Makefile
View File

@ -33,18 +33,18 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/axis_register.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_REG_TYPE ?= 2
export PARAM_LENGTH ?= 2
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_REG_TYPE := 2
export PARAM_LENGTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

48
lib/axis/tb/axis_ram_switch/Makefile
View File

@ -40,30 +40,30 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_FIFO_DEPTH ?= 4096
export PARAM_CMD_FIFO_DEPTH ?= 32
export PARAM_SPEEDUP ?= 0
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 16
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
export PARAM_M_DEST_WIDTH ?= 8
export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_BAD_FRAME ?= 0
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_UPDATE_TID ?= 1
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
export PARAM_RAM_PIPELINE ?= 2
export PARAM_FIFO_DEPTH := 4096
export PARAM_CMD_FIFO_DEPTH := 32
export PARAM_SPEEDUP := 0
export PARAM_S_DATA_WIDTH := 8
export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH := 8
export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_S_ID_WIDTH := 16
export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
export PARAM_M_DEST_WIDTH := 8
export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_BAD_FRAME := 0
export PARAM_DROP_WHEN_FULL := 0
export PARAM_UPDATE_TID := 1
export PARAM_ARB_TYPE_ROUND_ROBIN := 1
export PARAM_ARB_LSB_HIGH_PRIORITY := 1
export PARAM_RAM_PIPELINE := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
lib/axis/tb/axis_rate_limit/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
lib/axis/tb/axis_register/Makefile
View File

@ -32,17 +32,17 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_REG_TYPE ?= 2
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_REG_TYPE := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
lib/axis/tb/axis_srl_fifo/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DEPTH := 1024
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
lib/axis/tb/axis_srl_register/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

30
lib/axis/tb/axis_switch/Makefile
View File

@ -40,21 +40,21 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 16
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
export PARAM_M_DEST_WIDTH ?= 8
export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_UPDATE_TID ?= 1
export PARAM_S_REG_TYPE ?= 0
export PARAM_M_REG_TYPE ?= 2
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_S_ID_WIDTH := 16
export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
export PARAM_M_DEST_WIDTH := 8
export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_UPDATE_TID := 1
export PARAM_S_REG_TYPE := 0
export PARAM_M_REG_TYPE := 2
export PARAM_ARB_TYPE_ROUND_ROBIN := 1
export PARAM_ARB_LSB_HIGH_PRIORITY := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst