mirror of
https://github.com/corundum/corundum.git
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merged changes in pcie
This commit is contained in:
commit
dc75f86980
@ -174,67 +174,66 @@ async def run_test(dut):
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await tb.init()
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mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
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mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
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mem_base = mem.get_absolute_address(0)
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dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
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dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
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dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
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dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
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tb.log.info("Test memory write to BAR 2")
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await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
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test_data = b'\x11\x22\x33\x44'
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await dev_pf0_bar2.write(0, test_data)
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await Timer(100, 'ns')
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tb.log.info("Test memory read from BAR 2")
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val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
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val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
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tb.log.info("Read data: %s", val)
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assert val == b'\x11\x22\x33\x44'
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assert val == test_data
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tb.log.info("Test DMA")
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# write packet data
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mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
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mem[0:1024] = bytearray([x % 256 for x in range(1024)])
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# enable DMA
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
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await dev_pf0_bar0.write_dword(0x000000, 1)
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# enable interrupts
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 3)
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await dev_pf0_bar0.write_dword(0x000008, 0x3)
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# write pcie read descriptor
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, (0x100) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x00010C, (0x100 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
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await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000108, 0x100)
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await dev_pf0_bar0.write_dword(0x000110, 0x400)
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await dev_pf0_bar0.write_dword(0x000114, 0xAA)
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await Timer(2000, 'ns')
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# read status
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val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
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val = await dev_pf0_bar0.read_dword(0x000118)
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tb.log.info("Status: 0x%x", val)
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assert val == 0x800000AA
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# write pcie write descriptor
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, (0x100) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x00020C, (0x100 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
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await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000208, 0x100)
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await dev_pf0_bar0.write_dword(0x000210, 0x400)
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await dev_pf0_bar0.write_dword(0x000214, 0x55)
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await Timer(2000, 'ns')
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# read status
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val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
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val = await dev_pf0_bar0.read_dword(0x000218)
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tb.log.info("Status: 0x%x", val)
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assert val == 0x80000055
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tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
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tb.log.info("%s", mem.hexdump_str(0x1000, 64))
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assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
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assert mem[0:1024] == mem[0x1000:0x1000+1024]
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@ -252,64 +252,64 @@ async def run_test(dut):
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await tb.init()
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mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
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mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
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mem_base = mem.get_absolute_address(0)
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dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
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dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
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dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
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dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
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tb.log.info("Test memory write to BAR 2")
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await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
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test_data = b'\x11\x22\x33\x44'
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await dev_pf0_bar2.write(0, test_data)
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await Timer(100, 'ns')
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tb.log.info("Test memory read from BAR 2")
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val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
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val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
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tb.log.info("Read data: %s", val)
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assert val == b'\x11\x22\x33\x44'
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assert val == test_data
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tb.log.info("Test DMA")
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# write packet data
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mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
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mem[0:1024] = bytearray([x % 256 for x in range(1024)])
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# enable DMA
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
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await dev_pf0_bar0.write_dword(0x000000, 1)
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# write pcie read descriptor
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
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await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000108, 0x100)
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await dev_pf0_bar0.write_dword(0x000110, 0x400)
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await dev_pf0_bar0.write_dword(0x000114, 0xAA)
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await Timer(2000, 'ns')
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# read status
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val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
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val = await dev_pf0_bar0.read_dword(0x000118)
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tb.log.info("Status: 0x%x", val)
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assert val == 0x800000AA
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# write pcie write descriptor
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
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await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000208, 0x100)
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await dev_pf0_bar0.write_dword(0x000210, 0x400)
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await dev_pf0_bar0.write_dword(0x000214, 0x55)
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await Timer(2000, 'ns')
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# read status
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val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
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val = await dev_pf0_bar0.read_dword(0x000218)
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tb.log.info("Status: 0x%x", val)
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assert val == 0x80000055
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tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
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tb.log.info("%s", mem.hexdump_str(0x1000, 64))
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assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
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assert mem[0:1024] == mem[0x1000:0x1000+1024]
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@ -254,64 +254,64 @@ async def run_test(dut):
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await tb.init()
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mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
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mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
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mem_base = mem.get_absolute_address(0)
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dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
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dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
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dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
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dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
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tb.log.info("Test memory write to BAR 2")
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await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
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test_data = b'\x11\x22\x33\x44'
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await dev_pf0_bar2.write(0, test_data)
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await Timer(100, 'ns')
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tb.log.info("Test memory read from BAR 2")
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val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
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val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
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tb.log.info("Read data: %s", val)
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assert val == b'\x11\x22\x33\x44'
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assert val == test_data
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tb.log.info("Test DMA")
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# write packet data
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mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
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mem[0:1024] = bytearray([x % 256 for x in range(1024)])
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# enable DMA
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
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await dev_pf0_bar0.write_dword(0x000000, 1)
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# write pcie read descriptor
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
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await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000108, 0x100)
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await dev_pf0_bar0.write_dword(0x000110, 0x400)
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await dev_pf0_bar0.write_dword(0x000114, 0xAA)
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await Timer(2000, 'ns')
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# read status
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val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
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val = await dev_pf0_bar0.read_dword(0x000118)
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tb.log.info("Status: 0x%x", val)
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assert val == 0x800000AA
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# write pcie write descriptor
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
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await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000208, 0x100)
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await dev_pf0_bar0.write_dword(0x000210, 0x400)
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await dev_pf0_bar0.write_dword(0x000214, 0x55)
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await Timer(2000, 'ns')
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# read status
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val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
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val = await dev_pf0_bar0.read_dword(0x000218)
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tb.log.info("Status: 0x%x", val)
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assert val == 0x80000055
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tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
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tb.log.info("%s", mem.hexdump_str(0x1000, 64))
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assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
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assert mem[0:1024] == mem[0x1000:0x1000+1024]
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@ -254,64 +254,64 @@ async def run_test(dut):
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await tb.init()
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mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
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mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
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mem_base = mem.get_absolute_address(0)
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dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
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dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
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dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
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dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
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tb.log.info("Test memory write to BAR 2")
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await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
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test_data = b'\x11\x22\x33\x44'
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await dev_pf0_bar2.write(0, test_data)
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await Timer(100, 'ns')
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tb.log.info("Test memory read from BAR 2")
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val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
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val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
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tb.log.info("Read data: %s", val)
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assert val == b'\x11\x22\x33\x44'
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assert val == test_data
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tb.log.info("Test DMA")
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# write packet data
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mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
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mem[0:1024] = bytearray([x % 256 for x in range(1024)])
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# enable DMA
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
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await dev_pf0_bar0.write_dword(0x000000, 1)
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# write pcie read descriptor
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
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await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
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await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
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await dev_pf0_bar0.write_dword(0x000108, 0x100)
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await dev_pf0_bar0.write_dword(0x000110, 0x400)
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await dev_pf0_bar0.write_dword(0x000114, 0xAA)
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await Timer(2000, 'ns')
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# read status
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val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -252,64 +252,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -252,64 +252,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -246,64 +246,152 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# enable interrupts
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0x3)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
tb.log.info("Test DMA block operations")
|
||||
|
||||
# write packet data
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# disable interrupts
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0)
|
||||
|
||||
# configure operation (read)
|
||||
# DMA base address
|
||||
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await dev_pf0_bar0.write_dword(0x001088, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00108c, 0)
|
||||
# DMA offset mask
|
||||
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001094, 0)
|
||||
# DMA stride
|
||||
await dev_pf0_bar0.write_dword(0x001098, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00109c, 0)
|
||||
# RAM base address
|
||||
await dev_pf0_bar0.write_dword(0x0010c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c4, 0)
|
||||
# RAM offset address
|
||||
await dev_pf0_bar0.write_dword(0x0010c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010cc, 0)
|
||||
# RAM offset mask
|
||||
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0010d4, 0)
|
||||
# RAM stride
|
||||
await dev_pf0_bar0.write_dword(0x0010d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0010dc, 0)
|
||||
# clear cycle count
|
||||
await dev_pf0_bar0.write_dword(0x001008, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00100c, 0)
|
||||
# block length
|
||||
await dev_pf0_bar0.write_dword(0x001010, 256)
|
||||
# block count
|
||||
await dev_pf0_bar0.write_dword(0x001018, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00101c, 0)
|
||||
# start
|
||||
await dev_pf0_bar0.write_dword(0x001000, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# configure operation (write)
|
||||
# DMA base address
|
||||
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await dev_pf0_bar0.write_dword(0x001188, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00118c, 0)
|
||||
# DMA offset mask
|
||||
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001194, 0)
|
||||
# DMA stride
|
||||
await dev_pf0_bar0.write_dword(0x001198, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00119c, 0)
|
||||
# RAM base address
|
||||
await dev_pf0_bar0.write_dword(0x0011c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c4, 0)
|
||||
# RAM offset address
|
||||
await dev_pf0_bar0.write_dword(0x0011c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011cc, 0)
|
||||
# RAM offset mask
|
||||
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0011d4, 0)
|
||||
# RAM stride
|
||||
await dev_pf0_bar0.write_dword(0x0011d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0011dc, 0)
|
||||
# clear cycle count
|
||||
await dev_pf0_bar0.write_dword(0x001108, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00110c, 0)
|
||||
# block length
|
||||
await dev_pf0_bar0.write_dword(0x001110, 256)
|
||||
# block count
|
||||
await dev_pf0_bar0.write_dword(0x001118, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00111c, 0)
|
||||
# start
|
||||
await dev_pf0_bar0.write_dword(0x001100, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -246,64 +246,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -252,64 +252,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -174,67 +174,66 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# enable interrupts
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 3)
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0x3)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -253,64 +253,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -259,64 +259,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -254,64 +254,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -259,64 +259,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -120,10 +120,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -137,150 +137,152 @@ async def run_test(dut):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.dut.bus_num <= tb.dev.bus_num
|
||||
tb.dut.bus_num.value = tb.dev.bus_num
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# enable interrupts
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0x3)
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0x3)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, 0x100)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, 0x100)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
tb.log.info("Test DMA block operations")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# disable interrupts
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0)
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0)
|
||||
|
||||
# configure operation (read)
|
||||
# DMA base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001080, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001088, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00108c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001088, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00108c, 0)
|
||||
# DMA offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001090, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001094, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001094, 0)
|
||||
# DMA stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001098, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00109c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001098, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00109c, 0)
|
||||
# RAM base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c0, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c4, 0)
|
||||
# RAM offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c8, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010cc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010cc, 0)
|
||||
# RAM offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d0, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0010d4, 0)
|
||||
# RAM stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d8, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010dc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0010dc, 0)
|
||||
# clear cycle count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001008, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00100c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001008, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00100c, 0)
|
||||
# block length
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001010, 256)
|
||||
await dev_pf0_bar0.write_dword(0x001010, 256)
|
||||
# block count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001018, 32)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00101c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001018, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00101c, 0)
|
||||
# start
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x001000, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# configure operation (write)
|
||||
# DMA base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001180, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001188, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00118c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001188, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00118c, 0)
|
||||
# DMA offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001190, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001194, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001194, 0)
|
||||
# DMA stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001198, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00119c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001198, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00119c, 0)
|
||||
# RAM base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c0, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c4, 0)
|
||||
# RAM offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c8, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011cc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011cc, 0)
|
||||
# RAM offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d0, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0011d4, 0)
|
||||
# RAM stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d8, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011dc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0011dc, 0)
|
||||
# clear cycle count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001108, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00110c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001108, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00110c, 0)
|
||||
# block length
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001110, 256)
|
||||
await dev_pf0_bar0.write_dword(0x001110, 256)
|
||||
# block count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001118, 32)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00111c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001118, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00111c, 0)
|
||||
# start
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001100, 1)
|
||||
await dev_pf0_bar0.write_dword(0x001100, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
|
@ -177,148 +177,150 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# enable interrupts
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0x3)
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0x3)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, 0x100)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, 0x100)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
tb.log.info("Test DMA block operations")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# disable interrupts
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0)
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0)
|
||||
|
||||
# configure operation (read)
|
||||
# DMA base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001080, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001088, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00108c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001088, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00108c, 0)
|
||||
# DMA offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001090, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001094, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001094, 0)
|
||||
# DMA stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001098, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00109c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001098, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00109c, 0)
|
||||
# RAM base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c0, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c4, 0)
|
||||
# RAM offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c8, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010cc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010cc, 0)
|
||||
# RAM offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d0, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0010d4, 0)
|
||||
# RAM stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d8, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010dc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0010dc, 0)
|
||||
# clear cycle count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001008, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00100c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001008, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00100c, 0)
|
||||
# block length
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001010, 256)
|
||||
await dev_pf0_bar0.write_dword(0x001010, 256)
|
||||
# block count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001018, 32)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00101c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001018, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00101c, 0)
|
||||
# start
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x001000, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# configure operation (write)
|
||||
# DMA base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001180, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001188, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00118c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001188, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00118c, 0)
|
||||
# DMA offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001190, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001194, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001194, 0)
|
||||
# DMA stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001198, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00119c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001198, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00119c, 0)
|
||||
# RAM base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c0, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c4, 0)
|
||||
# RAM offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c8, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011cc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011cc, 0)
|
||||
# RAM offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d0, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0011d4, 0)
|
||||
# RAM stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d8, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011dc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0011dc, 0)
|
||||
# clear cycle count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001108, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00110c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001108, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00110c, 0)
|
||||
# block length
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001110, 256)
|
||||
await dev_pf0_bar0.write_dword(0x001110, 256)
|
||||
# block count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001118, 32)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00111c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001118, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00111c, 0)
|
||||
# start
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001100, 1)
|
||||
await dev_pf0_bar0.write_dword(0x001100, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
|
@ -271,148 +271,150 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# enable interrupts
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0x3)
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0x3)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, 0x100)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, 0x100)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
tb.log.info("Test DMA block operations")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# disable interrupts
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0)
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0)
|
||||
|
||||
# configure operation (read)
|
||||
# DMA base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001080, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001088, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00108c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001088, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00108c, 0)
|
||||
# DMA offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001090, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001094, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001094, 0)
|
||||
# DMA stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001098, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00109c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001098, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00109c, 0)
|
||||
# RAM base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c0, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c4, 0)
|
||||
# RAM offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c8, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010cc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010cc, 0)
|
||||
# RAM offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d0, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0010d4, 0)
|
||||
# RAM stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d8, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010dc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0010dc, 0)
|
||||
# clear cycle count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001008, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00100c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001008, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00100c, 0)
|
||||
# block length
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001010, 256)
|
||||
await dev_pf0_bar0.write_dword(0x001010, 256)
|
||||
# block count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001018, 32)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00101c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001018, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00101c, 0)
|
||||
# start
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x001000, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# configure operation (write)
|
||||
# DMA base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001180, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001188, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00118c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001188, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00118c, 0)
|
||||
# DMA offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001190, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001194, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001194, 0)
|
||||
# DMA stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001198, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00119c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001198, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00119c, 0)
|
||||
# RAM base address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c0, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c4, 0)
|
||||
# RAM offset address
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c8, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011cc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011cc, 0)
|
||||
# RAM offset mask
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d0, 0x000003ff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d4, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0011d4, 0)
|
||||
# RAM stride
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d8, 256)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011dc, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0011dc, 0)
|
||||
# clear cycle count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001108, 0)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00110c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001108, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00110c, 0)
|
||||
# block length
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001110, 256)
|
||||
await dev_pf0_bar0.write_dword(0x001110, 256)
|
||||
# block count
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001118, 32)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00111c, 0)
|
||||
await dev_pf0_bar0.write_dword(0x001118, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00111c, 0)
|
||||
# start
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001100, 1)
|
||||
await dev_pf0_bar0.write_dword(0x001100, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
|
@ -252,64 +252,152 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# enable interrupts
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0x3)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
tb.log.info("Test DMA block operations")
|
||||
|
||||
# write packet data
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
# disable interrupts
|
||||
await dev_pf0_bar0.write_dword(0x000008, 0)
|
||||
|
||||
# configure operation (read)
|
||||
# DMA base address
|
||||
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await dev_pf0_bar0.write_dword(0x001088, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00108c, 0)
|
||||
# DMA offset mask
|
||||
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001094, 0)
|
||||
# DMA stride
|
||||
await dev_pf0_bar0.write_dword(0x001098, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00109c, 0)
|
||||
# RAM base address
|
||||
await dev_pf0_bar0.write_dword(0x0010c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010c4, 0)
|
||||
# RAM offset address
|
||||
await dev_pf0_bar0.write_dword(0x0010c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0010cc, 0)
|
||||
# RAM offset mask
|
||||
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0010d4, 0)
|
||||
# RAM stride
|
||||
await dev_pf0_bar0.write_dword(0x0010d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0010dc, 0)
|
||||
# clear cycle count
|
||||
await dev_pf0_bar0.write_dword(0x001008, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00100c, 0)
|
||||
# block length
|
||||
await dev_pf0_bar0.write_dword(0x001010, 256)
|
||||
# block count
|
||||
await dev_pf0_bar0.write_dword(0x001018, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00101c, 0)
|
||||
# start
|
||||
await dev_pf0_bar0.write_dword(0x001000, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# configure operation (write)
|
||||
# DMA base address
|
||||
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
# DMA offset address
|
||||
await dev_pf0_bar0.write_dword(0x001188, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00118c, 0)
|
||||
# DMA offset mask
|
||||
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x001194, 0)
|
||||
# DMA stride
|
||||
await dev_pf0_bar0.write_dword(0x001198, 256)
|
||||
await dev_pf0_bar0.write_dword(0x00119c, 0)
|
||||
# RAM base address
|
||||
await dev_pf0_bar0.write_dword(0x0011c0, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011c4, 0)
|
||||
# RAM offset address
|
||||
await dev_pf0_bar0.write_dword(0x0011c8, 0)
|
||||
await dev_pf0_bar0.write_dword(0x0011cc, 0)
|
||||
# RAM offset mask
|
||||
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
|
||||
await dev_pf0_bar0.write_dword(0x0011d4, 0)
|
||||
# RAM stride
|
||||
await dev_pf0_bar0.write_dword(0x0011d8, 256)
|
||||
await dev_pf0_bar0.write_dword(0x0011dc, 0)
|
||||
# clear cycle count
|
||||
await dev_pf0_bar0.write_dword(0x001108, 0)
|
||||
await dev_pf0_bar0.write_dword(0x00110c, 0)
|
||||
# block length
|
||||
await dev_pf0_bar0.write_dword(0x001110, 256)
|
||||
# block count
|
||||
await dev_pf0_bar0.write_dword(0x001118, 32)
|
||||
await dev_pf0_bar0.write_dword(0x00111c, 0)
|
||||
# start
|
||||
await dev_pf0_bar0.write_dword(0x001100, 1)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -252,64 +252,64 @@ async def run_test(dut):
|
||||
|
||||
await tb.init()
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
|
||||
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
|
||||
test_data = b'\x11\x22\x33\x44'
|
||||
await dev_pf0_bar2.write(0, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
tb.log.info("Test memory read from BAR 2")
|
||||
|
||||
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
|
||||
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
|
||||
tb.log.info("Read data: %s", val)
|
||||
assert val == b'\x11\x22\x33\x44'
|
||||
assert val == test_data
|
||||
|
||||
tb.log.info("Test DMA")
|
||||
|
||||
# write packet data
|
||||
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
# enable DMA
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
|
||||
await dev_pf0_bar0.write_dword(0x000000, 1)
|
||||
|
||||
# write pcie read descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
|
||||
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000108, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000110, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
|
||||
val = await dev_pf0_bar0.read_dword(0x000118)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x800000AA
|
||||
|
||||
# write pcie write descriptor
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
|
||||
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
|
||||
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
|
||||
await dev_pf0_bar0.write_dword(0x000208, 0x100)
|
||||
await dev_pf0_bar0.write_dword(0x000210, 0x400)
|
||||
await dev_pf0_bar0.write_dword(0x000214, 0x55)
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
# read status
|
||||
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
|
||||
val = await dev_pf0_bar0.read_dword(0x000218)
|
||||
tb.log.info("Status: 0x%x", val)
|
||||
assert val == 0x80000055
|
||||
|
||||
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
|
||||
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
|
||||
|
||||
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||
assert mem[0:1024] == mem[0x1000:0x1000+1024]
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -408,7 +408,6 @@ always @* begin
|
||||
end
|
||||
|
||||
if (s_axis_read_desc_ready && s_axis_read_desc_valid) begin
|
||||
$display("AXI DMA start read (AXI 0x%x, RAM 0x%x 0x%x, len %d, tag 0x%x)", s_axis_read_desc_axi_addr, s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr, s_axis_read_desc_len, s_axis_read_desc_tag);
|
||||
s_axis_read_desc_ready_next = 1'b0;
|
||||
req_state_next = REQ_STATE_START;
|
||||
end else begin
|
||||
|
@ -231,7 +231,7 @@ reg mask_fifo_we;
|
||||
|
||||
reg read_cmd_ready;
|
||||
|
||||
reg [AXI_ADDR_WIDTH-1:0] axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, axi_addr_next;
|
||||
reg [AXI_ADDR_WIDTH-1:0] req_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, req_axi_addr_next;
|
||||
reg [RAM_SEL_WIDTH-1:0] ram_sel_reg = {RAM_SEL_WIDTH{1'b0}}, ram_sel_next;
|
||||
reg [RAM_ADDR_WIDTH-1:0] ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, ram_addr_next;
|
||||
reg [LEN_WIDTH-1:0] op_count_reg = {LEN_WIDTH{1'b0}}, op_count_next;
|
||||
@ -253,8 +253,8 @@ reg [OFFSET_WIDTH+1-1:0] cycle_byte_count_reg = {OFFSET_WIDTH+1{1'b0}}, cycle_by
|
||||
reg [RAM_OFFSET_WIDTH-1:0] start_offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, start_offset_next;
|
||||
reg [RAM_OFFSET_WIDTH-1:0] end_offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, end_offset_next;
|
||||
|
||||
reg [AXI_ADDR_WIDTH-1:0] tlp_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, tlp_addr_next;
|
||||
reg [11:0] tlp_len_reg = 12'd0, tlp_len_next;
|
||||
reg [AXI_ADDR_WIDTH-1:0] axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, axi_addr_next;
|
||||
reg [12:0] axi_len_reg = 13'd0, axi_len_next;
|
||||
reg [RAM_OFFSET_WIDTH-1:0] offset_reg = {RAM_OFFSET_WIDTH{1'b0}}, offset_next;
|
||||
reg [AXI_STRB_WIDTH-1:0] strb_offset_mask_reg = {AXI_STRB_WIDTH{1'b1}}, strb_offset_mask_next;
|
||||
reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
|
||||
@ -266,7 +266,7 @@ reg last_cycle_reg = 1'b0, last_cycle_next;
|
||||
reg [AXI_ADDR_WIDTH-1:0] read_cmd_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, read_cmd_axi_addr_next;
|
||||
reg [RAM_SEL_WIDTH-1:0] read_cmd_ram_sel_reg = {RAM_SEL_WIDTH{1'b0}}, read_cmd_ram_sel_next;
|
||||
reg [RAM_ADDR_WIDTH-1:0] read_cmd_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, read_cmd_ram_addr_next;
|
||||
reg [11:0] read_cmd_len_reg = 12'd0, read_cmd_len_next;
|
||||
reg [12:0] read_cmd_len_reg = 13'd0, read_cmd_len_next;
|
||||
reg [CYCLE_COUNT_WIDTH-1:0] read_cmd_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, read_cmd_cycle_count_next;
|
||||
reg read_cmd_last_cycle_reg = 1'b0, read_cmd_last_cycle_next;
|
||||
reg read_cmd_valid_reg = 1'b0, read_cmd_valid_next;
|
||||
@ -378,7 +378,7 @@ always @* begin
|
||||
s_axis_write_desc_ready_next = 1'b0;
|
||||
|
||||
tag_next = tag_reg;
|
||||
axi_addr_next = axi_addr_reg;
|
||||
req_axi_addr_next = req_axi_addr_reg;
|
||||
ram_sel_next = ram_sel_reg;
|
||||
ram_addr_next = ram_addr_reg;
|
||||
op_count_next = op_count_reg;
|
||||
@ -393,10 +393,10 @@ always @* begin
|
||||
read_cmd_last_cycle_next = read_cmd_last_cycle_reg;
|
||||
read_cmd_valid_next = read_cmd_valid_reg && !read_cmd_ready;
|
||||
|
||||
op_table_start_axi_addr = axi_addr_reg;
|
||||
op_table_start_axi_addr = req_axi_addr_reg;
|
||||
op_table_start_len = 0;
|
||||
op_table_start_cycle_count = 0;
|
||||
op_table_start_offset = (axi_addr_reg & OFFSET_MASK)-ram_addr_reg[RAM_OFFSET_WIDTH-1:0];
|
||||
op_table_start_offset = (req_axi_addr_reg & OFFSET_MASK)-ram_addr_reg[RAM_OFFSET_WIDTH-1:0];
|
||||
op_table_start_tag = tag_reg;
|
||||
op_table_start_last = 0;
|
||||
op_table_start_en = 1'b0;
|
||||
@ -407,34 +407,33 @@ always @* begin
|
||||
// idle state, wait for incoming descriptor
|
||||
s_axis_write_desc_ready_next = !op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] && ($unsigned(op_table_start_ptr_reg - op_table_finish_ptr_reg) < 2**OP_TAG_WIDTH) && enable;
|
||||
|
||||
axi_addr_next = s_axis_write_desc_axi_addr;
|
||||
req_axi_addr_next = s_axis_write_desc_axi_addr;
|
||||
ram_sel_next = s_axis_write_desc_ram_sel;
|
||||
ram_addr_next = s_axis_write_desc_ram_addr;
|
||||
op_count_next = s_axis_write_desc_len;
|
||||
tag_next = s_axis_write_desc_tag;
|
||||
|
||||
if (op_count_next <= AXI_MAX_BURST_SIZE - (axi_addr_next & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
|
||||
if (op_count_next <= AXI_MAX_BURST_SIZE - (req_axi_addr_next & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
|
||||
// packet smaller than max burst size
|
||||
if (((axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
|
||||
if (((req_axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
|
||||
// crosses 4k boundary
|
||||
tr_word_count_next = 13'h1000 - axi_addr_next[11:0];
|
||||
tr_word_count_next = 13'h1000 - req_axi_addr_next[11:0];
|
||||
end else begin
|
||||
// does not cross 4k boundary
|
||||
tr_word_count_next = op_count_next;
|
||||
end
|
||||
end else begin
|
||||
// packet larger than max burst size
|
||||
if (((axi_addr_next & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
|
||||
if (((req_axi_addr_next & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
|
||||
// crosses 4k boundary
|
||||
tr_word_count_next = 13'h1000 - axi_addr_next[11:0];
|
||||
tr_word_count_next = 13'h1000 - req_axi_addr_next[11:0];
|
||||
end else begin
|
||||
// does not cross 4k boundary
|
||||
tr_word_count_next = AXI_MAX_BURST_SIZE - (axi_addr_next & OFFSET_MASK);
|
||||
tr_word_count_next = AXI_MAX_BURST_SIZE - (req_axi_addr_next & OFFSET_MASK);
|
||||
end
|
||||
end
|
||||
|
||||
if (s_axis_write_desc_ready & s_axis_write_desc_valid) begin
|
||||
$display("AXI DMA start write (AXI 0x%x, RAM 0x%x 0x%x, len %d, tag 0x%x)", s_axis_write_desc_axi_addr, s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr, s_axis_write_desc_len, s_axis_write_desc_tag);
|
||||
s_axis_write_desc_ready_next = 1'b0;
|
||||
req_state_next = REQ_STATE_START;
|
||||
end else begin
|
||||
@ -444,43 +443,43 @@ always @* begin
|
||||
REQ_STATE_START: begin
|
||||
// start state, compute length
|
||||
if (!op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] && ($unsigned(op_table_start_ptr_reg - op_table_finish_ptr_reg) < 2**OP_TAG_WIDTH) && (!ram_rd_cmd_valid_reg || ram_rd_cmd_ready) && (!read_cmd_valid_reg || read_cmd_ready)) begin
|
||||
read_cmd_axi_addr_next = axi_addr_reg;
|
||||
read_cmd_axi_addr_next = req_axi_addr_reg;
|
||||
read_cmd_ram_sel_next = ram_sel_reg;
|
||||
read_cmd_ram_addr_next = ram_addr_reg;
|
||||
read_cmd_len_next = tr_word_count_next;
|
||||
read_cmd_cycle_count_next = (tr_word_count_next + (axi_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
|
||||
read_cmd_cycle_count_next = (tr_word_count_next + (req_axi_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
|
||||
op_table_start_cycle_count = read_cmd_cycle_count_next;
|
||||
read_cmd_last_cycle_next = read_cmd_cycle_count_next == 0;
|
||||
read_cmd_valid_next = 1'b1;
|
||||
|
||||
axi_addr_next = axi_addr_reg + tr_word_count_next;
|
||||
req_axi_addr_next = req_axi_addr_reg + tr_word_count_next;
|
||||
ram_addr_next = ram_addr_reg + tr_word_count_next;
|
||||
op_count_next = op_count_reg - tr_word_count_next;
|
||||
|
||||
op_table_start_axi_addr = axi_addr_reg;
|
||||
op_table_start_axi_addr = req_axi_addr_reg;
|
||||
op_table_start_len = tr_word_count_next;
|
||||
op_table_start_offset = (axi_addr_reg & OFFSET_MASK)-ram_addr_reg[RAM_OFFSET_WIDTH-1:0];
|
||||
op_table_start_offset = (req_axi_addr_reg & OFFSET_MASK)-ram_addr_reg[RAM_OFFSET_WIDTH-1:0];
|
||||
op_table_start_tag = tag_reg;
|
||||
op_table_start_last = op_count_reg == tr_word_count_next;
|
||||
op_table_start_en = 1'b1;
|
||||
|
||||
if (op_count_next <= AXI_MAX_BURST_SIZE - (axi_addr_next & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
|
||||
if (op_count_next <= AXI_MAX_BURST_SIZE - (req_axi_addr_next & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
|
||||
// packet smaller than max burst size
|
||||
if (((axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
|
||||
if (((req_axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
|
||||
// crosses 4k boundary
|
||||
tr_word_count_next = 13'h1000 - axi_addr_next[11:0];
|
||||
tr_word_count_next = 13'h1000 - req_axi_addr_next[11:0];
|
||||
end else begin
|
||||
// does not cross 4k boundary
|
||||
tr_word_count_next = op_count_next;
|
||||
end
|
||||
end else begin
|
||||
// packet larger than max burst size
|
||||
if (((axi_addr_next & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
|
||||
if (((req_axi_addr_next & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
|
||||
// crosses 4k boundary
|
||||
tr_word_count_next = 13'h1000 - axi_addr_next[11:0];
|
||||
tr_word_count_next = 13'h1000 - req_axi_addr_next[11:0];
|
||||
end else begin
|
||||
// does not cross 4k boundary
|
||||
tr_word_count_next = AXI_MAX_BURST_SIZE - (axi_addr_next & OFFSET_MASK);
|
||||
tr_word_count_next = AXI_MAX_BURST_SIZE - (req_axi_addr_next & OFFSET_MASK);
|
||||
end
|
||||
end
|
||||
|
||||
@ -655,8 +654,8 @@ always @* begin
|
||||
|
||||
ram_rd_resp_ready_cmb = {RAM_SEG_COUNT{1'b0}};
|
||||
|
||||
tlp_addr_next = tlp_addr_reg;
|
||||
tlp_len_next = tlp_len_reg;
|
||||
axi_addr_next = axi_addr_reg;
|
||||
axi_len_next = axi_len_reg;
|
||||
offset_next = offset_reg;
|
||||
strb_offset_mask_next = strb_offset_mask_reg;
|
||||
last_cycle_offset_next = last_cycle_offset_reg;
|
||||
@ -690,17 +689,17 @@ always @* begin
|
||||
// idle state, wait for command
|
||||
ram_rd_resp_ready_cmb = {RAM_SEG_COUNT{1'b0}};
|
||||
|
||||
tlp_addr_next = op_table_axi_addr[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
tlp_len_next = op_table_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
axi_addr_next = op_table_axi_addr[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
axi_len_next = op_table_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
offset_next = op_table_offset[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
strb_offset_mask_next = {AXI_STRB_WIDTH{1'b1}} << (tlp_addr_next & OFFSET_MASK);
|
||||
last_cycle_offset_next = tlp_addr_next + (tlp_len_next & OFFSET_MASK);
|
||||
strb_offset_mask_next = {AXI_STRB_WIDTH{1'b1}} << (axi_addr_next & OFFSET_MASK);
|
||||
last_cycle_offset_next = axi_addr_next + (axi_len_next & OFFSET_MASK);
|
||||
cycle_count_next = op_table_cycle_count[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
last_cycle_next = op_table_cycle_count[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] == 0;
|
||||
|
||||
if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!m_axi_awvalid_reg || m_axi_awready)) begin
|
||||
m_axi_awid_next = op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0];
|
||||
m_axi_awaddr_next = tlp_addr_next;
|
||||
m_axi_awaddr_next = axi_addr_next;
|
||||
m_axi_awlen_next = cycle_count_next;
|
||||
m_axi_awvalid_next = 1'b1;
|
||||
op_table_tx_start_en = 1'b1;
|
||||
@ -738,17 +737,17 @@ always @* begin
|
||||
end
|
||||
|
||||
// skip idle state if possible
|
||||
tlp_addr_next = op_table_axi_addr[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
tlp_len_next = op_table_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
axi_addr_next = op_table_axi_addr[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
axi_len_next = op_table_len[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
offset_next = op_table_offset[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
strb_offset_mask_next = {AXI_STRB_WIDTH{1'b1}} << (tlp_addr_next & OFFSET_MASK);
|
||||
last_cycle_offset_next = tlp_addr_next + (tlp_len_next & OFFSET_MASK);
|
||||
strb_offset_mask_next = {AXI_STRB_WIDTH{1'b1}} << (axi_addr_next & OFFSET_MASK);
|
||||
last_cycle_offset_next = axi_addr_next + (axi_len_next & OFFSET_MASK);
|
||||
cycle_count_next = op_table_cycle_count[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
|
||||
last_cycle_next = op_table_cycle_count[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] == 0;
|
||||
|
||||
if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!m_axi_awvalid_reg || m_axi_awready)) begin
|
||||
m_axi_awid_next = op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0];
|
||||
m_axi_awaddr_next = tlp_addr_next;
|
||||
m_axi_awaddr_next = axi_addr_next;
|
||||
m_axi_awlen_next = cycle_count_next;
|
||||
m_axi_awvalid_next = 1'b1;
|
||||
op_table_tx_start_en = 1'b1;
|
||||
@ -801,7 +800,7 @@ always @(posedge clk) begin
|
||||
read_state_reg <= read_state_next;
|
||||
axi_state_reg <= axi_state_next;
|
||||
|
||||
axi_addr_reg <= axi_addr_next;
|
||||
req_axi_addr_reg <= req_axi_addr_next;
|
||||
ram_sel_reg <= ram_sel_next;
|
||||
ram_addr_reg <= ram_addr_next;
|
||||
op_count_reg <= op_count_next;
|
||||
@ -823,8 +822,8 @@ always @(posedge clk) begin
|
||||
start_offset_reg <= start_offset_next;
|
||||
end_offset_reg <= end_offset_next;
|
||||
|
||||
tlp_addr_reg <= tlp_addr_next;
|
||||
tlp_len_reg <= tlp_len_next;
|
||||
axi_addr_reg <= axi_addr_next;
|
||||
axi_len_reg <= axi_len_next;
|
||||
offset_reg <= offset_next;
|
||||
strb_offset_mask_reg <= strb_offset_mask_next;
|
||||
last_cycle_offset_reg <= last_cycle_offset_next;
|
||||
|
@ -94,10 +94,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -117,7 +117,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
dut.enable <= 1
|
||||
dut.enable.value = 1
|
||||
|
||||
for length in list(range(1, byte_lanes*3+1))+[128]:
|
||||
for offset in range(0, byte_lanes*2, step_size):
|
||||
|
@ -92,10 +92,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -115,7 +115,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
dut.enable <= 1
|
||||
dut.enable.value = 1
|
||||
|
||||
for length in list(range(1, byte_lanes*3+1))+[128]:
|
||||
for offset in range(0, byte_lanes*2, step_size):
|
||||
|
@ -100,10 +100,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -123,7 +123,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.dut.write_enable <= 1
|
||||
tb.dut.write_enable.value = 1
|
||||
|
||||
for length in list(range(1, ram_byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
# for axi_offset in axi_offsets:
|
||||
@ -175,7 +175,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.dut.read_enable <= 1
|
||||
tb.dut.read_enable.value = 1
|
||||
|
||||
for length in list(range(1, ram_byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for axi_offset in list(range(axi_byte_lanes+1))+list(range(4096-axi_byte_lanes, 4096)):
|
||||
|
@ -92,10 +92,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -115,7 +115,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.dut.enable <= 1
|
||||
tb.dut.enable.value = 1
|
||||
|
||||
for length in list(range(1, ram_byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for axi_offset in list(range(axi_byte_lanes+1))+list(range(4096-axi_byte_lanes, 4096)):
|
||||
|
@ -93,10 +93,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -116,7 +116,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.dut.enable <= 1
|
||||
tb.dut.enable.value = 1
|
||||
|
||||
for length in list(range(1, ram_byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
# for axi_offset in axi_offsets:
|
||||
|
@ -164,7 +164,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.requester_id <= tb.dev.bus_num << 8
|
||||
tb.dut.enable <= 1
|
||||
@ -177,9 +178,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
ram_addr = ram_offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
tb.dma_ram.write(ram_addr-256, b'\xaa'*(len(test_data)+512))
|
||||
|
||||
@ -218,7 +219,8 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.requester_id <= tb.dev.bus_num << 8
|
||||
tb.dut.enable <= 1
|
||||
@ -233,7 +235,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -247,7 +249,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -261,7 +263,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
|
@ -179,9 +179,10 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.write_enable <= 1
|
||||
tb.dut.write_enable.value = 1
|
||||
|
||||
for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for pcie_offset in list(range(4))+list(range(4096-4, 4096)):
|
||||
@ -192,7 +193,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.dma_ram.write(ram_addr & 0xffff80, b'\x55'*(len(test_data)+256))
|
||||
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
tb.dma_ram.write(ram_addr, test_data)
|
||||
|
||||
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM "))
|
||||
@ -209,9 +210,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 0
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -236,9 +237,10 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.read_enable <= 1
|
||||
tb.dut.read_enable.value = 1
|
||||
|
||||
for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for pcie_offset in list(range(4))+list(range(4096-4, 4096)):
|
||||
@ -248,9 +250,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
ram_addr = ram_offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
tb.dma_ram.write(ram_addr-256, b'\xaa'*(len(test_data)+512))
|
||||
|
||||
@ -290,9 +292,10 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.read_enable <= 1
|
||||
tb.dut.read_enable.value = 1
|
||||
|
||||
tb.log.info("Test bad DMA read (UR) short")
|
||||
|
||||
@ -304,7 +307,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -318,7 +321,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -332,7 +335,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
|
@ -175,9 +175,10 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.enable <= 1
|
||||
tb.dut.enable.value = 1
|
||||
|
||||
for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for pcie_offset in pcie_offsets:
|
||||
@ -187,9 +188,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
ram_addr = ram_offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
tb.dma_ram.write(ram_addr-256, b'\xaa'*(len(test_data)+512))
|
||||
|
||||
@ -229,9 +230,10 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.enable <= 1
|
||||
tb.dut.enable.value = 1
|
||||
|
||||
tb.log.info("Test bad DMA read (UR) short")
|
||||
|
||||
@ -243,7 +245,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -257,7 +259,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -271,7 +273,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
|
@ -163,9 +163,10 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.enable <= 1
|
||||
tb.dut.enable.value = 1
|
||||
|
||||
for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for pcie_offset in pcie_offsets:
|
||||
@ -176,7 +177,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.dma_ram.write(ram_addr & 0xffff80, b'\x55'*(len(test_data)+256))
|
||||
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
tb.dma_ram.write(ram_addr, test_data)
|
||||
|
||||
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM "))
|
||||
@ -192,9 +193,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 0
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
|
@ -144,7 +144,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.enable <= 1
|
||||
|
||||
@ -157,7 +158,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.dma_ram.write(ram_addr & 0xffff80, b'\x55'*(len(test_data)+256))
|
||||
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
tb.dma_ram.write(ram_addr, test_data)
|
||||
|
||||
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM "))
|
||||
@ -173,9 +174,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 0
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
|
@ -146,11 +146,13 @@ class PsdpRamWrite(Memory):
|
||||
|
||||
wr_done = 0
|
||||
|
||||
cmd_be_sample = self.bus.wr_cmd_be.value
|
||||
cmd_addr_sample = self.bus.wr_cmd_addr.value
|
||||
cmd_data_sample = self.bus.wr_cmd_data.value
|
||||
cmd_valid_sample = self.bus.wr_cmd_valid.value
|
||||
|
||||
if cmd_valid_sample:
|
||||
cmd_be_sample = self.bus.wr_cmd_be.value
|
||||
cmd_addr_sample = self.bus.wr_cmd_addr.value
|
||||
cmd_data_sample = self.bus.wr_cmd_data.value
|
||||
|
||||
if self.reset is not None and self.reset.value:
|
||||
self.bus.wr_cmd_ready.setimmediatevalue(0)
|
||||
self.bus.wr_done.setimmediatevalue(0)
|
||||
@ -185,8 +187,8 @@ class PsdpRamWrite(Memory):
|
||||
if self.pause:
|
||||
cmd_ready = 0
|
||||
|
||||
self.bus.wr_cmd_ready <= cmd_ready
|
||||
self.bus.wr_done <= wr_done
|
||||
self.bus.wr_cmd_ready.value = cmd_ready
|
||||
self.bus.wr_done.value = wr_done
|
||||
|
||||
async def _run_pause(self):
|
||||
for val in self._pause_generator:
|
||||
@ -258,9 +260,11 @@ class PsdpRamRead(Memory):
|
||||
while True:
|
||||
await RisingEdge(self.clock)
|
||||
|
||||
cmd_addr_sample = self.bus.rd_cmd_addr.value
|
||||
cmd_valid_sample = self.bus.rd_cmd_valid.value
|
||||
|
||||
if cmd_valid_sample:
|
||||
cmd_addr_sample = self.bus.rd_cmd_addr.value
|
||||
|
||||
resp_ready_sample = self.bus.rd_resp_ready.value
|
||||
|
||||
if self.reset is not None and self.reset.value:
|
||||
@ -309,10 +313,10 @@ class PsdpRamRead(Memory):
|
||||
if self.pause:
|
||||
cmd_ready = 0
|
||||
|
||||
self.bus.rd_cmd_ready <= cmd_ready
|
||||
self.bus.rd_cmd_ready.value = cmd_ready
|
||||
|
||||
self.bus.rd_resp_data <= resp_data
|
||||
self.bus.rd_resp_valid <= resp_valid
|
||||
self.bus.rd_resp_data.value = resp_data
|
||||
self.bus.rd_resp_valid.value = resp_valid
|
||||
|
||||
async def _run_pause(self):
|
||||
for val in self._pause_generator:
|
||||
|
@ -133,10 +133,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -154,9 +154,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
for length in list(range(0, byte_lanes*2))+[1024]:
|
||||
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
|
||||
@ -166,7 +166,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(length*4+150, 'ns')
|
||||
|
||||
@ -194,9 +194,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
for length in list(range(0, byte_lanes*2))+[1024]:
|
||||
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
|
||||
@ -209,7 +209,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("read data: %s", val)
|
||||
|
||||
@ -233,10 +233,10 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
tb.log.info("Test IO write")
|
||||
|
||||
@ -247,7 +247,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -273,7 +273,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_cor_asserted
|
||||
assert not tb.status_error_uncor_asserted
|
||||
|
@ -133,10 +133,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -154,9 +154,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
for length in list(range(0, byte_lanes*2))+[1024]:
|
||||
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
|
||||
@ -169,7 +169,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("read data: %s", val)
|
||||
|
||||
@ -193,10 +193,10 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
tb.log.info("Test write")
|
||||
|
||||
@ -206,7 +206,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -229,7 +229,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -255,7 +255,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_cor_asserted
|
||||
assert not tb.status_error_uncor_asserted
|
||||
|
@ -119,10 +119,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -140,7 +140,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
for length in list(range(0, byte_lanes*2))+[1024]:
|
||||
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
|
||||
@ -150,7 +150,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(length*4+150, 'ns')
|
||||
|
||||
@ -175,8 +175,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.log.info("Test read")
|
||||
|
||||
@ -190,7 +190,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Timeout"):
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_uncor_asserted
|
||||
|
||||
@ -205,7 +205,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
with assert_raises(Exception, "Timeout"):
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -229,7 +229,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Timeout"):
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_uncor_asserted
|
||||
|
||||
|
@ -134,10 +134,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -156,9 +156,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
for length in list(range(0, pcie_byte_lanes*2))+[1024]:
|
||||
for pcie_offset in list(range(axil_byte_lanes))+list(range(4096-axil_byte_lanes, 4096)):
|
||||
@ -168,10 +168,10 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
# wait for write to complete
|
||||
val = await tb.rc.mem_read(dev_bar0, 4, 10000, 'ns')
|
||||
val = await dev_bar0.read(0, 4, timeout=10000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
@ -198,9 +198,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
for length in list(range(0, pcie_byte_lanes*2))+[1024]:
|
||||
for pcie_offset in list(range(axil_byte_lanes))+list(range(4096-axil_byte_lanes, 4096)):
|
||||
@ -213,7 +213,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 10000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=10000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("read data: %s", val)
|
||||
|
||||
@ -237,10 +237,10 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
tb.log.info("Test IO write")
|
||||
|
||||
@ -251,7 +251,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=10000, timeout_unit='ns')
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -277,7 +277,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=10000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_cor_asserted
|
||||
assert not tb.status_error_uncor_asserted
|
||||
|
@ -134,10 +134,10 @@ class TB(object):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
@ -153,9 +153,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
for length in range(0, 5):
|
||||
for pcie_offset in range(4-length+1):
|
||||
@ -165,10 +165,10 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
# wait for write to complete
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
@ -192,9 +192,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
for length in range(0, 5):
|
||||
for pcie_offset in range(4-length+1):
|
||||
@ -207,7 +207,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("read data: %s", val)
|
||||
|
||||
@ -231,10 +231,10 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.dut.completer_id <= int(tb.dev.functions[0].pcie_id)
|
||||
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
|
||||
|
||||
tb.log.info("Test IO write")
|
||||
|
||||
@ -245,7 +245,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -271,7 +271,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_cor_asserted
|
||||
assert not tb.status_error_uncor_asserted
|
||||
@ -287,7 +287,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -313,7 +313,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_cor_asserted
|
||||
assert not tb.status_error_uncor_asserted
|
||||
|
@ -457,7 +457,7 @@ class PcieIfSource(PcieIfBase):
|
||||
|
||||
if self.reset is not None and self.reset.value:
|
||||
self.active = False
|
||||
self.bus.valid <= 0
|
||||
self.bus.valid.value = 0
|
||||
continue
|
||||
|
||||
if ready_sample or not valid_sample:
|
||||
@ -467,7 +467,7 @@ class PcieIfSource(PcieIfBase):
|
||||
self.drive_sync.set()
|
||||
self.active = True
|
||||
else:
|
||||
self.bus.valid <= 0
|
||||
self.bus.valid.value = 0
|
||||
self.active = bool(self.drive_obj)
|
||||
if not self.drive_obj:
|
||||
self.idle_event.set()
|
||||
@ -608,7 +608,7 @@ class PcieIfSink(PcieIfBase):
|
||||
valid_sample = self.bus.valid.value
|
||||
|
||||
if self.reset is not None and self.reset.value:
|
||||
self.bus.ready <= 0
|
||||
self.bus.ready.value = 0
|
||||
continue
|
||||
|
||||
if ready_sample and valid_sample:
|
||||
@ -616,7 +616,7 @@ class PcieIfSink(PcieIfBase):
|
||||
self.bus.sample(self.sample_obj)
|
||||
self.sample_sync.set()
|
||||
|
||||
self.bus.ready <= (not self.full() and not self.pause)
|
||||
self.bus.ready.value = (not self.full() and not self.pause)
|
||||
|
||||
async def _run(self):
|
||||
self.active = False
|
||||
@ -873,13 +873,13 @@ class PcieIfDevice(Device):
|
||||
|
||||
tlp.release_fc()
|
||||
|
||||
self.log.info("Function not found: failed to route config type 0 TLP")
|
||||
self.log.info("Function not found: failed to route config type 0 TLP: %r", tlp)
|
||||
elif tlp.fmt_type in {TlpType.CFG_READ_1, TlpType.CFG_WRITE_1}:
|
||||
# config type 1
|
||||
|
||||
tlp.release_fc()
|
||||
|
||||
self.log.warning("Malformed TLP: endpoint received config type 1 TLP")
|
||||
self.log.warning("Malformed TLP: endpoint received config type 1 TLP: %r", tlp)
|
||||
elif tlp.fmt_type in {TlpType.CPL, TlpType.CPL_DATA, TlpType.CPL_LOCKED, TlpType.CPL_LOCKED_DATA}:
|
||||
# Completion
|
||||
|
||||
@ -898,18 +898,18 @@ class PcieIfDevice(Device):
|
||||
|
||||
tlp.release_fc()
|
||||
|
||||
self.log.warning("Unexpected completion: failed to route completion to function")
|
||||
self.log.warning("Unexpected completion: failed to route completion to function: %r", tlp)
|
||||
return # no UR response for completion
|
||||
elif tlp.fmt_type in {TlpType.IO_READ, TlpType.IO_WRITE}:
|
||||
# IO read/write
|
||||
|
||||
for f in self.functions:
|
||||
bar = f.match_bar(tlp.address, True)
|
||||
if len(bar) == 1:
|
||||
if bar:
|
||||
|
||||
frame = PcieIfFrame.from_tlp(tlp, self.force_64bit_addr)
|
||||
|
||||
frame.bar_id = bar[0][0]
|
||||
frame.bar_id = bar[0]
|
||||
frame.func_num = tlp.requester_id.function
|
||||
|
||||
await self.rx_req_queue.put(frame)
|
||||
@ -920,17 +920,17 @@ class PcieIfDevice(Device):
|
||||
|
||||
tlp.release_fc()
|
||||
|
||||
self.log.warning("No BAR match: IO request did not match any BARs")
|
||||
self.log.warning("No BAR match: IO request did not match any BARs: %r", tlp)
|
||||
elif tlp.fmt_type in {TlpType.MEM_READ, TlpType.MEM_READ_64, TlpType.MEM_WRITE, TlpType.MEM_WRITE_64}:
|
||||
# Memory read/write
|
||||
|
||||
for f in self.functions:
|
||||
bar = f.match_bar(tlp.address)
|
||||
if len(bar) == 1:
|
||||
if bar:
|
||||
|
||||
frame = PcieIfFrame.from_tlp(tlp, self.force_64bit_addr)
|
||||
|
||||
frame.bar_id = bar[0][0]
|
||||
frame.bar_id = bar[0]
|
||||
frame.func_num = tlp.requester_id.function
|
||||
|
||||
await self.rx_req_queue.put(frame)
|
||||
@ -942,10 +942,10 @@ class PcieIfDevice(Device):
|
||||
tlp.release_fc()
|
||||
|
||||
if tlp.fmt_type in {TlpType.MEM_WRITE, TlpType.MEM_WRITE_64}:
|
||||
self.log.warning("No BAR match: memory write request did not match any BARs")
|
||||
self.log.warning("No BAR match: memory write request did not match any BARs: %r", tlp)
|
||||
return # no UR response for write request
|
||||
else:
|
||||
self.log.warning("No BAR match: memory read request did not match any BARs")
|
||||
self.log.warning("No BAR match: memory read request did not match any BARs: %r", tlp)
|
||||
else:
|
||||
raise Exception("TODO")
|
||||
|
||||
@ -991,8 +991,8 @@ class PcieIfDevice(Device):
|
||||
if not self.rd_req_tx_seq_num_queue.empty():
|
||||
data |= self.rd_req_tx_seq_num_queue.get_nowait() << (width*k)
|
||||
valid |= 1 << k
|
||||
self.rd_req_tx_seq_num <= data
|
||||
self.rd_req_tx_seq_num_valid <= valid
|
||||
self.rd_req_tx_seq_num.value = data
|
||||
self.rd_req_tx_seq_num_valid.value = valid
|
||||
elif not self.rd_req_tx_seq_num_queue.empty():
|
||||
self.rd_req_tx_seq_num_queue.get_nowait()
|
||||
|
||||
@ -1017,8 +1017,8 @@ class PcieIfDevice(Device):
|
||||
if not self.wr_req_tx_seq_num_queue.empty():
|
||||
data |= self.wr_req_tx_seq_num_queue.get_nowait() << (width*k)
|
||||
valid |= 1 << k
|
||||
self.wr_req_tx_seq_num <= data
|
||||
self.wr_req_tx_seq_num_valid <= valid
|
||||
self.wr_req_tx_seq_num.value = data
|
||||
self.wr_req_tx_seq_num_valid.value = valid
|
||||
elif not self.wr_req_tx_seq_num_queue.empty():
|
||||
self.wr_req_tx_seq_num_queue.get_nowait()
|
||||
|
||||
@ -1027,54 +1027,54 @@ class PcieIfDevice(Device):
|
||||
await RisingEdge(self.clk)
|
||||
|
||||
if self.cfg_max_payload is not None:
|
||||
self.cfg_max_payload <= self.functions[0].pcie_cap.max_payload_size
|
||||
self.cfg_max_payload.value = self.functions[0].pcie_cap.max_payload_size
|
||||
if self.cfg_max_read_req is not None:
|
||||
self.cfg_max_read_req <= self.functions[0].pcie_cap.max_read_request_size
|
||||
self.cfg_max_read_req.value = self.functions[0].pcie_cap.max_read_request_size
|
||||
if self.cfg_ext_tag_enable is not None:
|
||||
self.cfg_ext_tag_enable <= self.functions[0].pcie_cap.extended_tag_field_enable
|
||||
self.cfg_ext_tag_enable.value = self.functions[0].pcie_cap.extended_tag_field_enable
|
||||
|
||||
async def _run_fc_logic(self):
|
||||
while True:
|
||||
await RisingEdge(self.clk)
|
||||
|
||||
if self.tx_fc_ph_av is not None:
|
||||
self.tx_fc_ph_av <= self.upstream_port.fc_state[0].ph.tx_credits_available
|
||||
self.tx_fc_ph_av.value = self.upstream_port.fc_state[0].ph.tx_credits_available
|
||||
if self.tx_fc_pd_av is not None:
|
||||
self.tx_fc_pd_av <= self.upstream_port.fc_state[0].pd.tx_credits_available
|
||||
self.tx_fc_pd_av.value = self.upstream_port.fc_state[0].pd.tx_credits_available
|
||||
if self.tx_fc_nph_av is not None:
|
||||
self.tx_fc_nph_av <= self.upstream_port.fc_state[0].nph.tx_credits_available
|
||||
self.tx_fc_nph_av.value = self.upstream_port.fc_state[0].nph.tx_credits_available
|
||||
if self.tx_fc_npd_av is not None:
|
||||
self.tx_fc_npd_av <= self.upstream_port.fc_state[0].npd.tx_credits_available
|
||||
self.tx_fc_npd_av.value = self.upstream_port.fc_state[0].npd.tx_credits_available
|
||||
if self.tx_fc_cplh_av is not None:
|
||||
self.tx_fc_cplh_av <= self.upstream_port.fc_state[0].cplh.tx_credits_available
|
||||
self.tx_fc_cplh_av.value = self.upstream_port.fc_state[0].cplh.tx_credits_available
|
||||
if self.tx_fc_cpld_av is not None:
|
||||
self.tx_fc_cpld_av <= self.upstream_port.fc_state[0].cpld.tx_credits_available
|
||||
self.tx_fc_cpld_av.value = self.upstream_port.fc_state[0].cpld.tx_credits_available
|
||||
|
||||
if self.tx_fc_ph_lim is not None:
|
||||
self.tx_fc_ph_lim <= self.upstream_port.fc_state[0].ph.tx_credit_limit
|
||||
self.tx_fc_ph_lim.value = self.upstream_port.fc_state[0].ph.tx_credit_limit
|
||||
if self.tx_fc_pd_lim is not None:
|
||||
self.tx_fc_pd_lim <= self.upstream_port.fc_state[0].pd.tx_credit_limit
|
||||
self.tx_fc_pd_lim.value = self.upstream_port.fc_state[0].pd.tx_credit_limit
|
||||
if self.tx_fc_nph_lim is not None:
|
||||
self.tx_fc_nph_lim <= self.upstream_port.fc_state[0].nph.tx_credit_limit
|
||||
self.tx_fc_nph_lim.value = self.upstream_port.fc_state[0].nph.tx_credit_limit
|
||||
if self.tx_fc_npd_lim is not None:
|
||||
self.tx_fc_npd_lim <= self.upstream_port.fc_state[0].npd.tx_credit_limit
|
||||
self.tx_fc_npd_lim.value = self.upstream_port.fc_state[0].npd.tx_credit_limit
|
||||
if self.tx_fc_cplh_lim is not None:
|
||||
self.tx_fc_cplh_lim <= self.upstream_port.fc_state[0].cplh.tx_credit_limit
|
||||
self.tx_fc_cplh_lim.value = self.upstream_port.fc_state[0].cplh.tx_credit_limit
|
||||
if self.tx_fc_cpld_lim is not None:
|
||||
self.tx_fc_cpld_lim <= self.upstream_port.fc_state[0].cpld.tx_credit_limit
|
||||
self.tx_fc_cpld_lim.value = self.upstream_port.fc_state[0].cpld.tx_credit_limit
|
||||
|
||||
if self.tx_fc_ph_cons is not None:
|
||||
self.tx_fc_ph_cons <= self.upstream_port.fc_state[0].ph.tx_credits_consumed
|
||||
self.tx_fc_ph_cons.value = self.upstream_port.fc_state[0].ph.tx_credits_consumed
|
||||
if self.tx_fc_pd_cons is not None:
|
||||
self.tx_fc_pd_cons <= self.upstream_port.fc_state[0].pd.tx_credits_consumed
|
||||
self.tx_fc_pd_cons.value = self.upstream_port.fc_state[0].pd.tx_credits_consumed
|
||||
if self.tx_fc_nph_cons is not None:
|
||||
self.tx_fc_nph_cons <= self.upstream_port.fc_state[0].nph.tx_credits_consumed
|
||||
self.tx_fc_nph_cons.value = self.upstream_port.fc_state[0].nph.tx_credits_consumed
|
||||
if self.tx_fc_npd_cons is not None:
|
||||
self.tx_fc_npd_cons <= self.upstream_port.fc_state[0].npd.tx_credits_consumed
|
||||
self.tx_fc_npd_cons.value = self.upstream_port.fc_state[0].npd.tx_credits_consumed
|
||||
if self.tx_fc_cplh_cons is not None:
|
||||
self.tx_fc_cplh_cons <= self.upstream_port.fc_state[0].cplh.tx_credits_consumed
|
||||
self.tx_fc_cplh_cons.value = self.upstream_port.fc_state[0].cplh.tx_credits_consumed
|
||||
if self.tx_fc_cpld_cons is not None:
|
||||
self.tx_fc_cpld_cons <= self.upstream_port.fc_state[0].cpld.tx_credits_consumed
|
||||
self.tx_fc_cpld_cons.value = self.upstream_port.fc_state[0].cpld.tx_credits_consumed
|
||||
|
||||
|
||||
class PcieIfTestDevice:
|
||||
@ -1433,7 +1433,7 @@ class PcieIfTestDevice:
|
||||
elif tlp.fmt_type == TlpType.IO_READ:
|
||||
self.log.info("IO read")
|
||||
|
||||
cpl = Tlp.create_completion_data_for_tlp(tlp, PcieId(0, 0, 0))
|
||||
cpl = Tlp.create_completion_data_for_tlp(tlp, PcieId(self.dev_bus_num, self.dev_device_num, 0))
|
||||
|
||||
region = frame.bar_id
|
||||
addr = tlp.address % self.regions[region][0]
|
||||
@ -1468,7 +1468,7 @@ class PcieIfTestDevice:
|
||||
elif tlp.fmt_type == TlpType.IO_WRITE:
|
||||
self.log.info("IO write")
|
||||
|
||||
cpl = Tlp.create_completion_for_tlp(tlp, PcieId(0, 0, 0))
|
||||
cpl = Tlp.create_completion_for_tlp(tlp, PcieId(self.dev_bus_num, self.dev_device_num, 0))
|
||||
|
||||
region = frame.bar_id
|
||||
addr = tlp.address % self.regions[region][0]
|
||||
@ -1516,7 +1516,7 @@ class PcieIfTestDevice:
|
||||
byte_length = tlp.get_be_byte_count()
|
||||
|
||||
while m < dw_length:
|
||||
cpl = Tlp.create_completion_data_for_tlp(tlp, PcieId(0, 0, 0))
|
||||
cpl = Tlp.create_completion_data_for_tlp(tlp, PcieId(self.dev_bus_num, self.dev_device_num, 0))
|
||||
|
||||
cpl_dw_length = dw_length - m
|
||||
cpl_byte_length = byte_length - n
|
||||
|
@ -64,7 +64,6 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).L_TILE=$(PARAM_L_TILE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
|
||||
@ -88,7 +87,6 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
|
||||
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
|
||||
COMPILE_ARGS += -GTX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
|
||||
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -GL_TILE=$(PARAM_L_TILE)
|
||||
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)
|
||||
|
@ -229,46 +229,43 @@ async def run_test_mem(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
|
||||
tb.test_dev.dev_bus_num = tb.dev.bus_num
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar3 = tb.rc.tree[0][0].bar_addr[3]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
dev_bar3 = tb.rc.tree[0][0].bar_window[3]
|
||||
|
||||
for length in list(range(0, 8)):
|
||||
for offset in list(range(8)):
|
||||
tb.log.info("IO operation length: %d offset: %d", length, offset)
|
||||
addr = dev_bar3+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.rc.io_write(addr, test_data, 5000)
|
||||
await dev_bar3.write(offset, test_data, timeout=5000)
|
||||
assert tb.test_dev.regions[3][1][offset:offset+length] == test_data
|
||||
|
||||
assert await tb.rc.io_read(addr, length, 5000) == test_data
|
||||
assert await dev_bar3.read(offset, length, timeout=5000) == test_data
|
||||
|
||||
for length in list(range(0, 32))+[1024]:
|
||||
for offset in list(range(8))+list(range(4096-8, 4096)):
|
||||
tb.log.info("Memory operation (32-bit BAR) length: %d offset: %d", length, offset)
|
||||
addr = dev_bar0+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.rc.mem_write(addr, test_data, 100)
|
||||
await dev_bar0.write(offset, test_data, timeout=100)
|
||||
# wait for write to complete
|
||||
await tb.rc.mem_read(addr, 1, 5000)
|
||||
await dev_bar0.read(offset, 1, timeout=5000)
|
||||
assert tb.test_dev.regions[0][1][offset:offset+length] == test_data
|
||||
|
||||
assert await tb.rc.mem_read(addr, length, 5000) == test_data
|
||||
assert await dev_bar0.read(offset, length, timeout=5000) == test_data
|
||||
|
||||
for length in list(range(0, 32))+[1024]:
|
||||
for offset in list(range(8))+list(range(4096-8, 4096)):
|
||||
tb.log.info("Memory operation (64-bit BAR) length: %d offset: %d", length, offset)
|
||||
addr = dev_bar1+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.rc.mem_write(addr, test_data, 100)
|
||||
await dev_bar1.write(offset, test_data, timeout=100)
|
||||
# wait for write to complete
|
||||
await tb.rc.mem_read(addr, 1, 5000)
|
||||
await dev_bar1.read(offset, 1, timeout=5000)
|
||||
assert tb.test_dev.regions[1][1][offset:offset+length] == test_data
|
||||
|
||||
assert await tb.rc.mem_read(addr, length, 5000) == test_data
|
||||
assert await dev_bar1.read(offset, length, timeout=5000) == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
@ -278,8 +275,11 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(1024*1024)
|
||||
io_base, io_data = tb.rc.alloc_io_region(1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
io = tb.rc.io_pool.alloc_region(1024)
|
||||
io_base = io.get_absolute_address(0)
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
@ -299,14 +299,14 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
addr = mem_base+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.test_dev.dma_mem_write(addr, test_data, 5000, 'ns')
|
||||
await tb.test_dev.dma_mem_write(addr, test_data, timeout=5000, timeout_unit='ns')
|
||||
# wait for write to complete
|
||||
while not tb.test_dev.tx_wr_req_tlp_source.empty() or tb.test_dev.tx_wr_req_tlp_source.active:
|
||||
await RisingEdge(dut.clk)
|
||||
await tb.test_dev.dma_mem_read(addr, length, 5000, 'ns')
|
||||
assert mem_data[offset:offset+length] == test_data
|
||||
await tb.test_dev.dma_mem_read(addr, length, timeout=5000, timeout_unit='ns')
|
||||
assert mem[offset:offset+length] == test_data
|
||||
|
||||
assert await tb.test_dev.dma_mem_read(addr, length, 5000, 'ns') == test_data
|
||||
assert await tb.test_dev.dma_mem_read(addr, length, timeout=5000, timeout_unit='ns') == test_data
|
||||
|
||||
for length in list(range(0, 8)):
|
||||
for offset in list(range(8)):
|
||||
@ -314,10 +314,10 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
addr = io_base+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.test_dev.dma_io_write(addr, test_data, 5000, 'ns')
|
||||
assert io_data[offset:offset+length] == test_data
|
||||
await tb.test_dev.dma_io_write(addr, test_data, timeout=5000, timeout_unit='ns')
|
||||
assert io[offset:offset+length] == test_data
|
||||
|
||||
assert await tb.test_dev.dma_io_read(addr, length, 5000, 'ns') == test_data
|
||||
assert await tb.test_dev.dma_io_read(addr, length, timeout=5000, timeout_unit='ns') == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
@ -335,7 +335,8 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.test_dev.dev_max_payload = tb.dev.functions[0].pcie_cap.max_payload_size
|
||||
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
|
||||
@ -344,7 +345,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
|
||||
tb.log.info("Memory operation (DMA) bad read (UR) short")
|
||||
|
||||
try:
|
||||
await tb.test_dev.dma_mem_read(mem_base - 1024, 8, 5000, 'ns')
|
||||
await tb.test_dev.dma_mem_read(mem_base - 1024, 8, timeout=5000, timeout_unit='ns')
|
||||
except Exception:
|
||||
pass
|
||||
else:
|
||||
@ -353,7 +354,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
|
||||
tb.log.info("Memory operation (DMA) bad read (UR) first")
|
||||
|
||||
try:
|
||||
await tb.test_dev.dma_mem_read(mem_base - 512, 1024, 5000, 'ns')
|
||||
await tb.test_dev.dma_mem_read(mem_base - 512, 1024, timeout=5000, timeout_unit='ns')
|
||||
except Exception:
|
||||
pass
|
||||
else:
|
||||
@ -362,7 +363,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
|
||||
tb.log.info("Memory operation (DMA) bad read (UR) last")
|
||||
|
||||
try:
|
||||
await tb.test_dev.dma_mem_read(mem_base + 1024*1024 - 512, 1024, 5000, 'ns')
|
||||
await tb.test_dev.dma_mem_read(mem_base + mem.size - 512, 1024, timeout=5000, timeout_unit='ns')
|
||||
except Exception:
|
||||
pass
|
||||
else:
|
||||
@ -388,9 +389,9 @@ async def run_test_msi(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.info("Send MSI %d", k)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
tb.dut.msi_irq <= 1 << k
|
||||
tb.dut.msi_irq.value = 1 << k
|
||||
await RisingEdge(dut.clk)
|
||||
tb.dut.msi_irq <= 0
|
||||
tb.dut.msi_irq.value = 0
|
||||
|
||||
event = tb.rc.msi_get_event(tb.dev.functions[0].pcie_id, k)
|
||||
event.clear()
|
||||
@ -416,17 +417,15 @@ async def run_test_fifos(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
|
||||
tb.test_dev.dev_bus_num = tb.dev.bus_num
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
test_data = bytearray([x for x in range(256)])
|
||||
|
||||
for k in range(64):
|
||||
addr = dev_bar0+k*256
|
||||
await tb.rc.mem_write(addr, test_data, 100)
|
||||
await dev_bar0.write(k*256, test_data, timeout=100)
|
||||
|
||||
for k in range(64):
|
||||
addr = dev_bar0+k*256
|
||||
assert await tb.rc.mem_read(addr, len(test_data), 50000) == test_data
|
||||
assert await dev_bar0.read(k*256, len(test_data), timeout=50000) == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
@ -171,9 +171,10 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.write_enable <= 1
|
||||
tb.dut.write_enable.value = 1
|
||||
|
||||
for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for pcie_offset in list(range(4))+list(range(4096-4, 4096)):
|
||||
@ -184,7 +185,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axi_ram.write(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256))
|
||||
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
tb.axi_ram.write(axi_addr, test_data)
|
||||
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((axi_addr & ~0xf)-16, (((axi_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
@ -200,9 +201,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 0
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -227,9 +228,10 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.read_enable <= 1
|
||||
tb.dut.read_enable.value = 1
|
||||
|
||||
for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for pcie_offset in list(range(4))+list(range(4096-4, 4096)):
|
||||
@ -239,9 +241,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
axi_addr = axi_offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
tb.axi_ram.write(axi_addr-256, b'\xaa'*(len(test_data)+512))
|
||||
|
||||
@ -281,9 +283,10 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.read_enable <= 1
|
||||
tb.dut.read_enable.value = 1
|
||||
|
||||
tb.log.info("Test bad DMA read (UR) short")
|
||||
|
||||
@ -295,7 +298,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -309,7 +312,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -323,7 +326,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
|
@ -166,9 +166,10 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.enable <= 1
|
||||
tb.dut.enable.value = 1
|
||||
|
||||
for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for pcie_offset in pcie_offsets:
|
||||
@ -178,9 +179,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
axi_addr = axi_offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
tb.axi_ram.write(axi_addr-256, b'\xaa'*(len(test_data)+512))
|
||||
|
||||
@ -220,9 +221,10 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.enable <= 1
|
||||
tb.dut.enable.value = 1
|
||||
|
||||
tb.log.info("Test bad DMA read (UR) short")
|
||||
|
||||
@ -234,7 +236,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -248,7 +250,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
@ -262,7 +264,7 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
|
||||
tb.log.info("status: %s", status)
|
||||
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 10
|
||||
assert int(status.error) in {10, 11}
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
|
@ -152,9 +152,10 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.dut.enable <= 1
|
||||
tb.dut.enable.value = 1
|
||||
|
||||
for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
|
||||
for pcie_offset in pcie_offsets:
|
||||
@ -165,7 +166,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axi_ram.write(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256))
|
||||
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
||||
tb.axi_ram.write(axi_addr, test_data)
|
||||
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((axi_addr & ~0xf)-16, (((axi_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
@ -181,9 +182,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
assert int(status.tag) == cur_tag
|
||||
assert int(status.error) == 0
|
||||
|
||||
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
|
||||
|
||||
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
cur_tag = (cur_tag + 1) % tag_count
|
||||
|
||||
|
@ -155,7 +155,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
for length in list(range(0, byte_lanes*2))+[1024]:
|
||||
for pcie_offset in range(byte_lanes):
|
||||
@ -165,7 +165,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(length*4+150, 'ns')
|
||||
|
||||
@ -194,7 +194,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
for length in list(range(0, byte_lanes*2))+[1024]:
|
||||
for pcie_offset in range(byte_lanes):
|
||||
@ -207,7 +207,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("read data: %s", val)
|
||||
|
||||
@ -232,8 +232,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.log.info("Test IO write")
|
||||
|
||||
@ -244,7 +244,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -270,7 +270,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_cor_asserted
|
||||
assert not tb.status_error_uncor_asserted
|
||||
|
@ -152,7 +152,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
for length in list(range(0, byte_lanes*2))+[1024]:
|
||||
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
|
||||
@ -165,7 +165,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("read data: %s", val)
|
||||
|
||||
@ -190,8 +190,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.log.info("Test write")
|
||||
|
||||
@ -201,7 +201,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -224,7 +224,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -250,7 +250,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_cor_asserted
|
||||
assert not tb.status_error_uncor_asserted
|
||||
|
@ -137,7 +137,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
|
||||
for length in list(range(0, byte_lanes*2))+[1024]:
|
||||
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
|
||||
@ -147,7 +147,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(length*4+150, 'ns')
|
||||
|
||||
@ -173,8 +173,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.log.info("Test read")
|
||||
|
||||
@ -188,7 +188,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Timeout"):
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_uncor_asserted
|
||||
|
||||
@ -203,7 +203,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
with assert_raises(Exception, "Timeout"):
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -227,7 +227,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Timeout"):
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_uncor_asserted
|
||||
|
||||
|
@ -151,8 +151,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
for length in range(0, 5):
|
||||
for pcie_offset in range(4-length+1):
|
||||
@ -162,7 +162,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -189,8 +189,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
for length in range(0, 5):
|
||||
for pcie_offset in range(4-length+1):
|
||||
@ -203,7 +203,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("read data: %s", val)
|
||||
|
||||
@ -228,8 +228,8 @@ async def run_test_io_write(dut, idle_inserter=None, backpressure_inserter=None)
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
for length in range(1, 5):
|
||||
for pcie_offset in range(4-length+1):
|
||||
@ -239,7 +239,7 @@ async def run_test_io_write(dut, idle_inserter=None, backpressure_inserter=None)
|
||||
|
||||
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
|
||||
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
@ -264,8 +264,8 @@ async def run_test_io_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
for length in range(1, 5):
|
||||
for pcie_offset in range(4-length+1):
|
||||
@ -278,7 +278,7 @@ async def run_test_io_read(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
tb.log.debug("read data: %s", val)
|
||||
|
||||
@ -303,8 +303,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
await tb.rc.enumerate()
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
|
||||
tb.log.info("Test bad write")
|
||||
|
||||
@ -314,7 +314,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
|
||||
|
||||
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
|
||||
await dev_bar0.write(pcie_addr, test_data)
|
||||
|
||||
await Timer(100, 'ns')
|
||||
|
||||
@ -340,7 +340,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
|
||||
|
||||
with assert_raises(Exception, "Unsuccessful completion"):
|
||||
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
|
||||
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
|
||||
|
||||
assert tb.status_error_cor_asserted
|
||||
assert not tb.status_error_uncor_asserted
|
||||
|
@ -309,46 +309,43 @@ async def run_test_mem(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
|
||||
tb.test_dev.dev_bus_num = tb.dev.bus_num
|
||||
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
|
||||
dev_bar3 = tb.rc.tree[0][0].bar_addr[3]
|
||||
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
|
||||
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
|
||||
dev_bar3 = tb.rc.tree[0][0].bar_window[3]
|
||||
|
||||
for length in list(range(0, 8)):
|
||||
for offset in list(range(8)):
|
||||
tb.log.info("IO operation length: %d offset: %d", length, offset)
|
||||
addr = dev_bar3+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.rc.io_write(addr, test_data, 5000)
|
||||
await dev_bar3.write(offset, test_data, timeout=5000)
|
||||
assert tb.test_dev.regions[3][1][offset:offset+length] == test_data
|
||||
|
||||
assert await tb.rc.io_read(addr, length, 5000) == test_data
|
||||
assert await dev_bar3.read(offset, length, timeout=5000) == test_data
|
||||
|
||||
for length in list(range(0, 32))+[1024]:
|
||||
for offset in list(range(8))+list(range(4096-8, 4096)):
|
||||
tb.log.info("Memory operation (32-bit BAR) length: %d offset: %d", length, offset)
|
||||
addr = dev_bar0+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.rc.mem_write(addr, test_data, 100)
|
||||
await dev_bar0.write(offset, test_data, timeout=100)
|
||||
# wait for write to complete
|
||||
await tb.rc.mem_read(addr, 1, 5000)
|
||||
await dev_bar0.read(offset, 1, timeout=5000)
|
||||
assert tb.test_dev.regions[0][1][offset:offset+length] == test_data
|
||||
|
||||
assert await tb.rc.mem_read(addr, length, 5000) == test_data
|
||||
assert await dev_bar0.read(offset, length, timeout=5000) == test_data
|
||||
|
||||
for length in list(range(0, 32))+[1024]:
|
||||
for offset in list(range(8))+list(range(4096-8, 4096)):
|
||||
tb.log.info("Memory operation (64-bit BAR) length: %d offset: %d", length, offset)
|
||||
addr = dev_bar1+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.rc.mem_write(addr, test_data, 100)
|
||||
await dev_bar1.write(offset, test_data, timeout=100)
|
||||
# wait for write to complete
|
||||
await tb.rc.mem_read(addr, 1, 5000)
|
||||
await dev_bar1.read(offset, 1, timeout=5000)
|
||||
assert tb.test_dev.regions[1][1][offset:offset+length] == test_data
|
||||
|
||||
assert await tb.rc.mem_read(addr, length, 5000) == test_data
|
||||
assert await dev_bar1.read(offset, length, timeout=5000) == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
@ -358,8 +355,11 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(1024*1024)
|
||||
io_base, io_data = tb.rc.alloc_io_region(1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
io = tb.rc.io_pool.alloc_region(1024)
|
||||
io_base = io.get_absolute_address(0)
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
@ -379,14 +379,14 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
addr = mem_base+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.test_dev.dma_mem_write(addr, test_data, 5000, 'ns')
|
||||
await tb.test_dev.dma_mem_write(addr, test_data, timeout=5000, timeout_unit='ns')
|
||||
# wait for write to complete
|
||||
while not tb.test_dev.tx_wr_req_tlp_source.empty() or tb.test_dev.tx_wr_req_tlp_source.active:
|
||||
await RisingEdge(dut.clk)
|
||||
await tb.test_dev.dma_mem_read(addr, 1, 5000, 'ns')
|
||||
assert mem_data[offset:offset+length] == test_data
|
||||
await tb.test_dev.dma_mem_read(addr, 1, timeout=5000, timeout_unit='ns')
|
||||
assert mem[offset:offset+length] == test_data
|
||||
|
||||
assert await tb.test_dev.dma_mem_read(addr, length, 5000, 'ns') == test_data
|
||||
assert await tb.test_dev.dma_mem_read(addr, length, timeout=5000, timeout_unit='ns') == test_data
|
||||
|
||||
for length in list(range(0, 8)):
|
||||
for offset in list(range(8)):
|
||||
@ -394,10 +394,10 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
addr = io_base+offset
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.test_dev.dma_io_write(addr, test_data, 5000, 'ns')
|
||||
assert io_data[offset:offset+length] == test_data
|
||||
await tb.test_dev.dma_io_write(addr, test_data, timeout=5000, timeout_unit='ns')
|
||||
assert io[offset:offset+length] == test_data
|
||||
|
||||
assert await tb.test_dev.dma_io_read(addr, length, 5000, 'ns') == test_data
|
||||
assert await tb.test_dev.dma_io_read(addr, length, timeout=5000, timeout_unit='ns') == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
@ -415,7 +415,8 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
|
||||
|
||||
await tb.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
|
||||
mem_base, mem_data = tb.rc.alloc_region(1024*1024)
|
||||
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
|
||||
mem_base = mem.get_absolute_address(0)
|
||||
|
||||
tb.test_dev.dev_max_payload = tb.dev.functions[0].pcie_cap.max_payload_size
|
||||
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
|
||||
@ -424,7 +425,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
|
||||
tb.log.info("Memory operation (DMA) bad read (UR) short")
|
||||
|
||||
try:
|
||||
await tb.test_dev.dma_mem_read(mem_base - 1024, 8, 5000, 'ns')
|
||||
await tb.test_dev.dma_mem_read(mem_base - 1024, 8, timeout=5000, timeout_unit='ns')
|
||||
except Exception:
|
||||
pass
|
||||
else:
|
||||
@ -433,7 +434,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
|
||||
tb.log.info("Memory operation (DMA) bad read (UR) first")
|
||||
|
||||
try:
|
||||
await tb.test_dev.dma_mem_read(mem_base - 512, 1024, 5000, 'ns')
|
||||
await tb.test_dev.dma_mem_read(mem_base - 512, 1024, timeout=5000, timeout_unit='ns')
|
||||
except Exception:
|
||||
pass
|
||||
else:
|
||||
@ -442,7 +443,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
|
||||
tb.log.info("Memory operation (DMA) bad read (UR) last")
|
||||
|
||||
try:
|
||||
await tb.test_dev.dma_mem_read(mem_base + 1024*1024 - 512, 1024, 5000, 'ns')
|
||||
await tb.test_dev.dma_mem_read(mem_base + mem.size - 512, 1024, timeout=5000, timeout_unit='ns')
|
||||
except Exception:
|
||||
pass
|
||||
else:
|
||||
@ -468,9 +469,9 @@ async def run_test_msi(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
tb.log.info("Send MSI %d", k)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
tb.dut.msi_irq <= 1 << k
|
||||
tb.dut.msi_irq.value = 1 << k
|
||||
await RisingEdge(dut.clk)
|
||||
tb.dut.msi_irq <= 0
|
||||
tb.dut.msi_irq.value = 0
|
||||
|
||||
event = tb.rc.msi_get_event(tb.dev.functions[0].pcie_id, k)
|
||||
event.clear()
|
||||
|
Loading…
x
Reference in New Issue
Block a user