Initial commit

.gitignore

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+*~
+*.lxt
+*.pyc
+*.vvp
+*.kate-swp
+

AUTHORS

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+Alex Forencich <alex@alexforencich.com>

COPYING

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+Copyright 2019, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+   1. Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimer in the documentation
+      and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.

README

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+README.md

README.md

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+# Corundum Readme
+
+GitHub repository: https://github.com/ucsdsysnet/corundum
+
+## Introduction
+
+Corundum is an open source, high performance FPGA based NIC.
+
+## Documentation
+
+### Modules
+
+### Common signals
+
+### Common parameters
+
+### Source Files
+
+    arbiter.v               : Parametrizable arbiter
+
+## Testing
+
+Running the included testbenches requires MyHDL and Icarus Verilog.  Make sure
+that myhdl.vpi is installed properly for cosimulation to work correctly.  The
+testbenches can be run with a Python test runner like nose or py.test, or the
+individual test scripts can be run with python directly.
+
+### Testbench Files
+
+    tb/axis_ep.py        : MyHDL AXI Stream endpoints
+    tb/pcie.py           : MyHDL PCI Express BFM
+    tb/pcie_us.py        : MyHDL Xilinx Ultrascale PCIe core model