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https://github.com/corundum/corundum.git
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Update testbenches for latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
ae55dcc432
commit
dd2853bf40
@ -85,7 +85,8 @@ class TB(object):
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cq_cc_straddle=False,
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rq_rc_straddle=False,
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rc_4tlp_straddle=False,
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enable_pf1=False,
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pf_count=1,
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max_payload_size=1024,
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enable_client_tag=True,
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enable_extended_tag=True,
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enable_parity=False,
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@ -93,8 +94,38 @@ class TB(object):
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enable_sriov=False,
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enable_extended_configuration=False,
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enable_pf0_msi=True,
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enable_pf1_msi=False,
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pf0_msi_enable=True,
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pf0_msi_count=32,
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pf1_msi_enable=False,
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pf1_msi_count=1,
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pf2_msi_enable=False,
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pf2_msi_count=1,
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pf3_msi_enable=False,
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pf3_msi_count=1,
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pf0_msix_enable=False,
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pf0_msix_table_size=0,
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pf0_msix_table_bir=0,
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pf0_msix_table_offset=0x00000000,
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pf0_msix_pba_bir=0,
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pf0_msix_pba_offset=0x00000000,
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pf1_msix_enable=False,
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pf1_msix_table_size=0,
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pf1_msix_table_bir=0,
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pf1_msix_table_offset=0x00000000,
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pf1_msix_pba_bir=0,
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pf1_msix_pba_offset=0x00000000,
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pf2_msix_enable=False,
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pf2_msix_table_size=0,
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pf2_msix_table_bir=0,
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pf2_msix_table_offset=0x00000000,
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pf2_msix_pba_bir=0,
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pf2_msix_pba_offset=0x00000000,
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pf3_msix_enable=False,
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pf3_msix_table_size=0,
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pf3_msix_table_bir=0,
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pf3_msix_table_offset=0x00000000,
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pf3_msix_pba_bir=0,
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pf3_msix_pba_offset=0x00000000,
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# signals
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# Clock and Reset Interface
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@ -240,6 +271,8 @@ class TB(object):
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# cfg_interrupt_msix_int
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# cfg_interrupt_msix_vec_pending
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# cfg_interrupt_msix_vec_pending_status
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# cfg_interrupt_msix_sent
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# cfg_interrupt_msix_fail
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cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
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cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
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cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
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@ -263,8 +296,6 @@ class TB(object):
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self.driver = mqnic.Driver()
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self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
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self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
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if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
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self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
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@ -363,7 +394,7 @@ class TB(object):
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self.dut.ptp_rst.setimmediatevalue(0)
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await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
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await self.rc.enumerate()
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async def _run_loopback(self):
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while True:
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@ -383,7 +414,7 @@ async def run_test_nic(dut):
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await tb.init()
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tb.log.info("Init driver")
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await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
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await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
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for interface in tb.driver.interfaces:
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await interface.open()
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@ -85,7 +85,8 @@ class TB(object):
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cq_cc_straddle=False,
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rq_rc_straddle=False,
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rc_4tlp_straddle=False,
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enable_pf1=False,
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pf_count=1,
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max_payload_size=1024,
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enable_client_tag=True,
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enable_extended_tag=True,
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enable_parity=False,
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@ -93,8 +94,38 @@ class TB(object):
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enable_sriov=False,
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enable_extended_configuration=False,
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enable_pf0_msi=True,
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enable_pf1_msi=False,
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pf0_msi_enable=True,
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pf0_msi_count=32,
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pf1_msi_enable=False,
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pf1_msi_count=1,
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pf2_msi_enable=False,
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pf2_msi_count=1,
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pf3_msi_enable=False,
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pf3_msi_count=1,
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pf0_msix_enable=False,
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pf0_msix_table_size=0,
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pf0_msix_table_bir=0,
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pf0_msix_table_offset=0x00000000,
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pf0_msix_pba_bir=0,
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pf0_msix_pba_offset=0x00000000,
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pf1_msix_enable=False,
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pf1_msix_table_size=0,
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pf1_msix_table_bir=0,
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pf1_msix_table_offset=0x00000000,
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pf1_msix_pba_bir=0,
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pf1_msix_pba_offset=0x00000000,
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pf2_msix_enable=False,
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pf2_msix_table_size=0,
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pf2_msix_table_bir=0,
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pf2_msix_table_offset=0x00000000,
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pf2_msix_pba_bir=0,
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pf2_msix_pba_offset=0x00000000,
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pf3_msix_enable=False,
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pf3_msix_table_size=0,
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pf3_msix_table_bir=0,
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pf3_msix_table_offset=0x00000000,
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pf3_msix_pba_bir=0,
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pf3_msix_pba_offset=0x00000000,
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# signals
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# Clock and Reset Interface
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@ -240,6 +271,8 @@ class TB(object):
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# cfg_interrupt_msix_int
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# cfg_interrupt_msix_vec_pending
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# cfg_interrupt_msix_vec_pending_status
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# cfg_interrupt_msix_sent
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# cfg_interrupt_msix_fail
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cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
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cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
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cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
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@ -263,8 +296,6 @@ class TB(object):
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self.driver = mqnic.Driver()
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self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
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self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
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if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
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self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
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@ -363,7 +394,7 @@ class TB(object):
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self.dut.ptp_rst.setimmediatevalue(0)
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await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
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await self.rc.enumerate()
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async def _run_loopback(self):
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while True:
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@ -383,7 +414,7 @@ async def run_test_nic(dut):
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await tb.init()
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tb.log.info("Init driver")
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await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
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await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
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for interface in tb.driver.interfaces:
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await interface.open()
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@ -377,7 +377,6 @@ class EqRing:
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self.interface = interface
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self.log = interface.log
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self.driver = interface.driver
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self.rc = interface.driver.rc
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self.log_size = size.bit_length() - 1
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self.size = 2**self.log_size
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self.size_mask = self.size-1
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@ -479,7 +478,6 @@ class CqRing:
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self.interface = interface
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self.log = interface.log
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self.driver = interface.driver
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self.rc = interface.driver.rc
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self.log_size = size.bit_length() - 1
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self.size = 2**self.log_size
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self.size_mask = self.size-1
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@ -547,7 +545,6 @@ class TxRing:
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self.interface = interface
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self.log = interface.log
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self.driver = interface.driver
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self.rc = interface.driver.rc
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self.log_queue_size = size.bit_length() - 1
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self.log_desc_block_size = int(stride/MQNIC_DESC_SIZE).bit_length() - 1
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self.desc_block_size = 2**self.log_desc_block_size
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@ -632,7 +629,6 @@ class RxRing:
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self.interface = interface
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self.log = interface.log
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self.driver = interface.driver
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self.rc = interface.driver.rc
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self.log_queue_size = size.bit_length() - 1
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self.log_desc_block_size = int(stride/MQNIC_DESC_SIZE).bit_length() - 1
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self.desc_block_size = 2**self.log_desc_block_size
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@ -1367,10 +1363,7 @@ class Driver:
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def __init__(self):
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self.log = SimLog("cocotb.mqnic")
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self.rc = None
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self.dev_id = None
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self.rc_tree_ent = None
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self.dev = None
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self.pool = None
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self.hw_regs = None
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@ -1412,24 +1405,26 @@ class Driver:
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self.allocated_packets = []
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self.free_packets = deque()
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async def init_pcie_dev(self, rc, dev_id):
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async def init_pcie_dev(self, dev):
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assert not self.initialized
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self.initialized = True
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self.rc = rc
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self.dev_id = dev_id
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self.rc_tree_ent = self.rc.tree.find_child_dev(dev_id)
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self.dev = dev
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self.pool = self.rc.mem_pool
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self.pool = self.dev.rc.mem_pool
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self.hw_regs = self.rc_tree_ent.bar_window[0]
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self.app_hw_regs = self.rc_tree_ent.bar_window[2]
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self.ram_hw_regs = self.rc_tree_ent.bar_window[4]
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await self.dev.enable_device()
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await self.dev.set_master()
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await self.dev.alloc_irq_vectors(1, MQNIC_MAX_EVENT_RINGS)
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self.hw_regs = self.dev.bar_window[0]
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self.app_hw_regs = self.dev.bar_window[2]
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self.ram_hw_regs = self.dev.bar_window[4]
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# set up MSI
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for index in range(32):
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irq = Interrupt(index, self.interrupt_handler)
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self.rc.msi_register_callback(self.dev_id, irq.interrupt, index)
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self.dev.request_irq(index, irq.interrupt)
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self.irq_list.append(irq)
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await self.init_common()
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@ -82,6 +82,42 @@ class TB(object):
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# pcie_link_width=2,
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# pld_clk_frequency=250e6,
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l_tile=False,
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pf_count=1,
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max_payload_size=1024,
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enable_extended_tag=True,
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pf0_msi_enable=True,
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pf0_msi_count=32,
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pf1_msi_enable=False,
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pf1_msi_count=1,
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pf2_msi_enable=False,
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pf2_msi_count=1,
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pf3_msi_enable=False,
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pf3_msi_count=1,
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pf0_msix_enable=False,
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pf0_msix_table_size=0,
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pf0_msix_table_bir=0,
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pf0_msix_table_offset=0x00000000,
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pf0_msix_pba_bir=0,
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pf0_msix_pba_offset=0x00000000,
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pf1_msix_enable=False,
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pf1_msix_table_size=0,
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pf1_msix_table_bir=0,
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pf1_msix_table_offset=0x00000000,
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pf1_msix_pba_bir=0,
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pf1_msix_pba_offset=0x00000000,
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pf2_msix_enable=False,
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pf2_msix_table_size=0,
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pf2_msix_table_bir=0,
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pf2_msix_table_offset=0x00000000,
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pf2_msix_pba_bir=0,
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pf2_msix_pba_offset=0x00000000,
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pf3_msix_enable=False,
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pf3_msix_table_size=0,
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pf3_msix_table_bir=0,
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pf3_msix_table_offset=0x00000000,
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pf3_msix_pba_bir=0,
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pf3_msix_pba_offset=0x00000000,
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# signals
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# Clock and reset
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@ -188,8 +224,6 @@ class TB(object):
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self.driver = mqnic.Driver()
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self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
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self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
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if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
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self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
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@ -288,7 +322,7 @@ class TB(object):
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self.dut.ptp_rst.setimmediatevalue(0)
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await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
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await self.rc.enumerate()
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async def _run_loopback(self):
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while True:
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@ -308,7 +342,7 @@ async def run_test_nic(dut):
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await tb.init()
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tb.log.info("Init driver")
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await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
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await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
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for interface in tb.driver.interfaces:
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await interface.open()
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@ -85,7 +85,8 @@ class TB(object):
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cq_cc_straddle=False,
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rq_rc_straddle=False,
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rc_4tlp_straddle=False,
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enable_pf1=False,
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pf_count=1,
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max_payload_size=1024,
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enable_client_tag=True,
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enable_extended_tag=True,
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enable_parity=False,
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@ -93,8 +94,38 @@ class TB(object):
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enable_sriov=False,
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enable_extended_configuration=False,
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enable_pf0_msi=True,
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enable_pf1_msi=False,
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pf0_msi_enable=True,
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pf0_msi_count=32,
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pf1_msi_enable=False,
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pf1_msi_count=1,
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pf2_msi_enable=False,
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pf2_msi_count=1,
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pf3_msi_enable=False,
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pf3_msi_count=1,
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pf0_msix_enable=False,
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pf0_msix_table_size=0,
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pf0_msix_table_bir=0,
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pf0_msix_table_offset=0x00000000,
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pf0_msix_pba_bir=0,
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pf0_msix_pba_offset=0x00000000,
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pf1_msix_enable=False,
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pf1_msix_table_size=0,
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pf1_msix_table_bir=0,
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pf1_msix_table_offset=0x00000000,
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pf1_msix_pba_bir=0,
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pf1_msix_pba_offset=0x00000000,
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pf2_msix_enable=False,
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pf2_msix_table_size=0,
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pf2_msix_table_bir=0,
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pf2_msix_table_offset=0x00000000,
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pf2_msix_pba_bir=0,
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pf2_msix_pba_offset=0x00000000,
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pf3_msix_enable=False,
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pf3_msix_table_size=0,
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pf3_msix_table_bir=0,
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pf3_msix_table_offset=0x00000000,
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pf3_msix_pba_bir=0,
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pf3_msix_pba_offset=0x00000000,
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# signals
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# Clock and Reset Interface
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@ -240,6 +271,8 @@ class TB(object):
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# cfg_interrupt_msix_int
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# cfg_interrupt_msix_vec_pending
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# cfg_interrupt_msix_vec_pending_status
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# cfg_interrupt_msix_sent
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# cfg_interrupt_msix_fail
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cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
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cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
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cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
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@ -263,8 +296,6 @@ class TB(object):
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self.driver = mqnic.Driver()
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self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
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self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
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if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
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self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
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@ -363,7 +394,7 @@ class TB(object):
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|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -383,7 +414,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
for interface in tb.driver.interfaces:
|
||||
await interface.open()
|
||||
|
||||
|
||||
@ -85,7 +85,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -93,8 +94,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -240,6 +271,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -263,8 +296,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -363,7 +394,7 @@ class TB(object):
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -383,7 +414,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
for interface in tb.driver.interfaces:
|
||||
await interface.open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -359,7 +390,7 @@ class TB(object):
|
||||
self.dut.qsfp_1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp_1_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -380,7 +411,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -426,7 +457,7 @@ class TB(object):
|
||||
self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -459,7 +490,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -359,7 +390,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -380,7 +411,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -426,7 +457,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -459,7 +490,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -359,7 +390,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -380,7 +411,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -426,7 +457,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -459,7 +490,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -348,7 +379,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -369,7 +400,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -415,7 +446,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -448,7 +479,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -323,7 +354,7 @@ class TB(object):
|
||||
self.dut.qsfp_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -342,7 +373,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
|
||||
# enable queues
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -356,7 +387,7 @@ class TB(object):
|
||||
self.dut.qsfp_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -381,7 +412,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
|
||||
# enable queues
|
||||
|
||||
@ -82,7 +82,8 @@ class TB(object):
|
||||
user_clk_frequency=250e6,
|
||||
alignment="dword",
|
||||
straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -90,8 +91,22 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -231,8 +246,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -256,8 +271,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -422,7 +435,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -455,7 +468,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -82,7 +82,8 @@ class TB(object):
|
||||
user_clk_frequency=250e6,
|
||||
alignment="dword",
|
||||
straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -90,8 +91,22 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -231,8 +246,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -256,8 +271,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -341,7 +354,7 @@ class TB(object):
|
||||
self.dut.sfp_4_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp_4_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -366,7 +379,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -82,7 +82,8 @@ class TB(object):
|
||||
user_clk_frequency=250e6,
|
||||
alignment="dword",
|
||||
straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -90,8 +91,22 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -231,8 +246,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -256,8 +271,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -333,7 +346,7 @@ class TB(object):
|
||||
self.dut.sfp_2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp_2_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -354,7 +367,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -430,7 +461,7 @@ class TB(object):
|
||||
self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -463,7 +494,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -342,7 +373,7 @@ class TB(object):
|
||||
self.dut.sfp_2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp_2_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -363,7 +394,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -80,6 +80,42 @@ class TB(object):
|
||||
# pcie_link_width=8,
|
||||
# pld_clk_frequency=250e6,
|
||||
l_tile=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_extended_tag=True,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and reset
|
||||
@ -184,8 +220,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -335,7 +369,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -368,7 +402,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -82,7 +82,8 @@ class TB(object):
|
||||
user_clk_frequency=250e6,
|
||||
alignment="dword",
|
||||
straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -90,8 +91,22 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -231,8 +246,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -256,8 +271,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -363,7 +376,7 @@ class TB(object):
|
||||
self.dut.qsfp_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -388,7 +401,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
|
||||
# enable queues
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -363,7 +394,7 @@ class TB(object):
|
||||
self.dut.qsfp2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -384,7 +415,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -430,7 +461,7 @@ class TB(object):
|
||||
self.dut.qsfp2_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp2_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -463,7 +494,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -357,7 +388,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -378,7 +409,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -424,7 +455,7 @@ class TB(object):
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -457,7 +488,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -423,7 +454,7 @@ class TB(object):
|
||||
self.dut.qsfp3_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp3_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -448,7 +479,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -558,7 +589,7 @@ class TB(object):
|
||||
self.dut.qsfp3_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp3_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -607,7 +638,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -336,7 +367,7 @@ class TB(object):
|
||||
self.dut.sfp1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp1_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -357,7 +388,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -361,7 +394,7 @@ class TB(object):
|
||||
self.dut.qsfp_1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp_1_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -382,7 +415,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
@ -84,7 +84,8 @@ class TB(object):
|
||||
cq_cc_straddle=False,
|
||||
rq_rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
enable_pf1=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
@ -92,8 +93,38 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
enable_pf0_msi=True,
|
||||
enable_pf1_msi=False,
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
@ -239,6 +270,8 @@ class TB(object):
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
@ -262,8 +295,6 @@ class TB(object):
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
@ -428,7 +459,7 @@ class TB(object):
|
||||
self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
@ -461,7 +492,7 @@ async def run_test_nic(dut):
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user