FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Update testbenches for latest version of cocotbext-pcie

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-05-30 13:10:39 -07:00
parent ae55dcc432
commit dd2853bf40
33 changed files with 1127 additions and 235 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -85,7 +85,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -93,8 +94,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -240,6 +271,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -263,8 +296,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -363,7 +394,7 @@ class TB(object):
self.dut.ptp_rst.setimmediatevalue(0) self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -383,7 +414,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
for interface in tb.driver.interfaces: for interface in tb.driver.interfaces:
await interface.open() await interface.open()

45
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -85,7 +85,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -93,8 +94,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -240,6 +271,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -263,8 +296,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -363,7 +394,7 @@ class TB(object):
self.dut.ptp_rst.setimmediatevalue(0) self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -383,7 +414,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
for interface in tb.driver.interfaces: for interface in tb.driver.interfaces:
await interface.open() await interface.open()

29
fpga/common/tb/mqnic.py
View File

@ -377,7 +377,6 @@ class EqRing:
self.interface = interface self.interface = interface
self.log = interface.log self.log = interface.log
self.driver = interface.driver self.driver = interface.driver
self.rc = interface.driver.rc
self.log_size = size.bit_length() - 1 self.log_size = size.bit_length() - 1
self.size = 2**self.log_size self.size = 2**self.log_size
self.size_mask = self.size-1 self.size_mask = self.size-1
@ -479,7 +478,6 @@ class CqRing:
self.interface = interface self.interface = interface
self.log = interface.log self.log = interface.log
self.driver = interface.driver self.driver = interface.driver
self.rc = interface.driver.rc
self.log_size = size.bit_length() - 1 self.log_size = size.bit_length() - 1
self.size = 2**self.log_size self.size = 2**self.log_size
self.size_mask = self.size-1 self.size_mask = self.size-1
@ -547,7 +545,6 @@ class TxRing:
self.interface = interface self.interface = interface
self.log = interface.log self.log = interface.log
self.driver = interface.driver self.driver = interface.driver
self.rc = interface.driver.rc
self.log_queue_size = size.bit_length() - 1 self.log_queue_size = size.bit_length() - 1
self.log_desc_block_size = int(stride/MQNIC_DESC_SIZE).bit_length() - 1 self.log_desc_block_size = int(stride/MQNIC_DESC_SIZE).bit_length() - 1
self.desc_block_size = 2**self.log_desc_block_size self.desc_block_size = 2**self.log_desc_block_size
@ -632,7 +629,6 @@ class RxRing:
self.interface = interface self.interface = interface
self.log = interface.log self.log = interface.log
self.driver = interface.driver self.driver = interface.driver
self.rc = interface.driver.rc
self.log_queue_size = size.bit_length() - 1 self.log_queue_size = size.bit_length() - 1
self.log_desc_block_size = int(stride/MQNIC_DESC_SIZE).bit_length() - 1 self.log_desc_block_size = int(stride/MQNIC_DESC_SIZE).bit_length() - 1
self.desc_block_size = 2**self.log_desc_block_size self.desc_block_size = 2**self.log_desc_block_size
@ -1367,10 +1363,7 @@ class Driver:
def __init__(self): def __init__(self):
self.log = SimLog("cocotb.mqnic") self.log = SimLog("cocotb.mqnic")
self.rc = None self.dev = None
self.dev_id = None
self.rc_tree_ent = None
self.pool = None self.pool = None
self.hw_regs = None self.hw_regs = None
@ -1412,24 +1405,26 @@ class Driver:
self.allocated_packets = [] self.allocated_packets = []
self.free_packets = deque() self.free_packets = deque()
async def init_pcie_dev(self, rc, dev_id): async def init_pcie_dev(self, dev):
assert not self.initialized assert not self.initialized
self.initialized = True self.initialized = True
self.rc = rc self.dev = dev
self.dev_id = dev_id
self.rc_tree_ent = self.rc.tree.find_child_dev(dev_id)
self.pool = self.rc.mem_pool self.pool = self.dev.rc.mem_pool
self.hw_regs = self.rc_tree_ent.bar_window[0] await self.dev.enable_device()
self.app_hw_regs = self.rc_tree_ent.bar_window[2] await self.dev.set_master()
self.ram_hw_regs = self.rc_tree_ent.bar_window[4] await self.dev.alloc_irq_vectors(1, MQNIC_MAX_EVENT_RINGS)
self.hw_regs = self.dev.bar_window[0]
self.app_hw_regs = self.dev.bar_window[2]
self.ram_hw_regs = self.dev.bar_window[4]
# set up MSI # set up MSI
for index in range(32): for index in range(32):
irq = Interrupt(index, self.interrupt_handler) irq = Interrupt(index, self.interrupt_handler)
self.rc.msi_register_callback(self.dev_id, irq.interrupt, index) self.dev.request_irq(index, irq.interrupt)
self.irq_list.append(irq) self.irq_list.append(irq)
await self.init_common() await self.init_common()

42
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -82,6 +82,42 @@ class TB(object):
# pcie_link_width=2, # pcie_link_width=2,
# pld_clk_frequency=250e6, # pld_clk_frequency=250e6,
l_tile=False, l_tile=False,
pf_count=1,
max_payload_size=1024,
enable_extended_tag=True,
pf0_msi_enable=True,
pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and reset # Clock and reset
@ -188,8 +224,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -288,7 +322,7 @@ class TB(object):
self.dut.ptp_rst.setimmediatevalue(0) self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -308,7 +342,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
for interface in tb.driver.interfaces: for interface in tb.driver.interfaces:
await interface.open() await interface.open()

45
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -85,7 +85,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -93,8 +94,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -240,6 +271,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -263,8 +296,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -363,7 +394,7 @@ class TB(object):
self.dut.ptp_rst.setimmediatevalue(0) self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -383,7 +414,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
for interface in tb.driver.interfaces: for interface in tb.driver.interfaces:
await interface.open() await interface.open()

45
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -85,7 +85,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -93,8 +94,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -240,6 +271,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -263,8 +296,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -363,7 +394,7 @@ class TB(object):
self.dut.ptp_rst.setimmediatevalue(0) self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -383,7 +414,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
for interface in tb.driver.interfaces: for interface in tb.driver.interfaces:
await interface.open() await interface.open()

45
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -359,7 +390,7 @@ class TB(object):
self.dut.qsfp_1_rx_rst.setimmediatevalue(0) self.dut.qsfp_1_rx_rst.setimmediatevalue(0)
self.dut.qsfp_1_tx_rst.setimmediatevalue(0) self.dut.qsfp_1_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -380,7 +411,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -426,7 +457,7 @@ class TB(object):
self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -459,7 +490,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -359,7 +390,7 @@ class TB(object):
self.dut.qsfp1_rx_rst.setimmediatevalue(0) self.dut.qsfp1_rx_rst.setimmediatevalue(0)
self.dut.qsfp1_tx_rst.setimmediatevalue(0) self.dut.qsfp1_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -380,7 +411,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -426,7 +457,7 @@ class TB(object):
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -459,7 +490,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -359,7 +390,7 @@ class TB(object):
self.dut.qsfp1_rx_rst.setimmediatevalue(0) self.dut.qsfp1_rx_rst.setimmediatevalue(0)
self.dut.qsfp1_tx_rst.setimmediatevalue(0) self.dut.qsfp1_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -380,7 +411,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -426,7 +457,7 @@ class TB(object):
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -459,7 +490,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -348,7 +379,7 @@ class TB(object):
self.dut.qsfp1_rx_rst.setimmediatevalue(0) self.dut.qsfp1_rx_rst.setimmediatevalue(0)
self.dut.qsfp1_tx_rst.setimmediatevalue(0) self.dut.qsfp1_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -369,7 +400,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -415,7 +446,7 @@ class TB(object):
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -448,7 +479,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -323,7 +354,7 @@ class TB(object):
self.dut.qsfp_rx_rst.setimmediatevalue(0) self.dut.qsfp_rx_rst.setimmediatevalue(0)
self.dut.qsfp_tx_rst.setimmediatevalue(0) self.dut.qsfp_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -342,7 +373,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# enable queues # enable queues

45
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -356,7 +387,7 @@ class TB(object):
self.dut.qsfp_rx_rst_4.setimmediatevalue(0) self.dut.qsfp_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp_tx_rst_4.setimmediatevalue(0) self.dut.qsfp_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -381,7 +412,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# enable queues # enable queues

31
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -82,7 +82,8 @@ class TB(object):
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
straddle=False, straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -90,8 +91,22 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -231,8 +246,8 @@ class TB(object):
# cfg_interrupt_msix_address # cfg_interrupt_msix_address
# cfg_interrupt_msix_data # cfg_interrupt_msix_data
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_sent
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -256,8 +271,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -422,7 +435,7 @@ class TB(object):
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -455,7 +468,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

31
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -82,7 +82,8 @@ class TB(object):
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
straddle=False, straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -90,8 +91,22 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -231,8 +246,8 @@ class TB(object):
# cfg_interrupt_msix_address # cfg_interrupt_msix_address
# cfg_interrupt_msix_data # cfg_interrupt_msix_data
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_sent
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -256,8 +271,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -341,7 +354,7 @@ class TB(object):
self.dut.sfp_4_rx_rst.setimmediatevalue(0) self.dut.sfp_4_rx_rst.setimmediatevalue(0)
self.dut.sfp_4_tx_rst.setimmediatevalue(0) self.dut.sfp_4_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -366,7 +379,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

31
fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -82,7 +82,8 @@ class TB(object):
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
straddle=False, straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -90,8 +91,22 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -231,8 +246,8 @@ class TB(object):
# cfg_interrupt_msix_address # cfg_interrupt_msix_address
# cfg_interrupt_msix_data # cfg_interrupt_msix_data
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_sent
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -256,8 +271,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -333,7 +346,7 @@ class TB(object):
self.dut.sfp_2_rx_rst.setimmediatevalue(0) self.dut.sfp_2_rx_rst.setimmediatevalue(0)
self.dut.sfp_2_tx_rst.setimmediatevalue(0) self.dut.sfp_2_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -354,7 +367,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -430,7 +461,7 @@ class TB(object):
self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -463,7 +494,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -342,7 +373,7 @@ class TB(object):
self.dut.sfp_2_rx_rst.setimmediatevalue(0) self.dut.sfp_2_rx_rst.setimmediatevalue(0)
self.dut.sfp_2_tx_rst.setimmediatevalue(0) self.dut.sfp_2_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -363,7 +394,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

42
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -80,6 +80,42 @@ class TB(object):
# pcie_link_width=8, # pcie_link_width=8,
# pld_clk_frequency=250e6, # pld_clk_frequency=250e6,
l_tile=False, l_tile=False,
pf_count=1,
max_payload_size=1024,
enable_extended_tag=True,
pf0_msi_enable=True,
pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and reset # Clock and reset
@ -184,8 +220,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -335,7 +369,7 @@ class TB(object):
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -368,7 +402,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

31
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -82,7 +82,8 @@ class TB(object):
user_clk_frequency=250e6, user_clk_frequency=250e6,
alignment="dword", alignment="dword",
straddle=False, straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -90,8 +91,22 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -231,8 +246,8 @@ class TB(object):
# cfg_interrupt_msix_address # cfg_interrupt_msix_address
# cfg_interrupt_msix_data # cfg_interrupt_msix_data
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_sent
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -256,8 +271,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -363,7 +376,7 @@ class TB(object):
self.dut.qsfp_rx_rst_4.setimmediatevalue(0) self.dut.qsfp_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp_tx_rst_4.setimmediatevalue(0) self.dut.qsfp_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -388,7 +401,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# enable queues # enable queues

45
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -363,7 +394,7 @@ class TB(object):
self.dut.qsfp2_rx_rst.setimmediatevalue(0) self.dut.qsfp2_rx_rst.setimmediatevalue(0)
self.dut.qsfp2_tx_rst.setimmediatevalue(0) self.dut.qsfp2_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -384,7 +415,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -430,7 +461,7 @@ class TB(object):
self.dut.qsfp2_rx_rst_4.setimmediatevalue(0) self.dut.qsfp2_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_4.setimmediatevalue(0) self.dut.qsfp2_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -463,7 +494,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -357,7 +388,7 @@ class TB(object):
self.dut.qsfp1_rx_rst.setimmediatevalue(0) self.dut.qsfp1_rx_rst.setimmediatevalue(0)
self.dut.qsfp1_tx_rst.setimmediatevalue(0) self.dut.qsfp1_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -378,7 +409,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -424,7 +455,7 @@ class TB(object):
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -457,7 +488,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -423,7 +454,7 @@ class TB(object):
self.dut.qsfp3_rx_rst.setimmediatevalue(0) self.dut.qsfp3_rx_rst.setimmediatevalue(0)
self.dut.qsfp3_tx_rst.setimmediatevalue(0) self.dut.qsfp3_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -448,7 +479,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -558,7 +589,7 @@ class TB(object):
self.dut.qsfp3_rx_rst_4.setimmediatevalue(0) self.dut.qsfp3_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_4.setimmediatevalue(0) self.dut.qsfp3_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -607,7 +638,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -336,7 +367,7 @@ class TB(object):
self.dut.sfp1_rx_rst.setimmediatevalue(0) self.dut.sfp1_rx_rst.setimmediatevalue(0)
self.dut.sfp1_tx_rst.setimmediatevalue(0) self.dut.sfp1_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -357,7 +388,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

43
fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -361,7 +394,7 @@ class TB(object):
self.dut.qsfp_1_rx_rst.setimmediatevalue(0) self.dut.qsfp_1_rx_rst.setimmediatevalue(0)
self.dut.qsfp_1_tx_rst.setimmediatevalue(0) self.dut.qsfp_1_tx_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -382,7 +415,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

45
fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -84,7 +84,8 @@ class TB(object):
cq_cc_straddle=False, cq_cc_straddle=False,
rq_rc_straddle=False, rq_rc_straddle=False,
rc_4tlp_straddle=False, rc_4tlp_straddle=False,
enable_pf1=False, pf_count=1,
max_payload_size=1024,
enable_client_tag=True, enable_client_tag=True,
enable_extended_tag=True, enable_extended_tag=True,
enable_parity=False, enable_parity=False,
@ -92,8 +93,38 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
enable_pf0_msi=True, pf0_msi_enable=True,
enable_pf1_msi=False, pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals # signals
# Clock and Reset Interface # Clock and Reset Interface
@ -239,6 +270,8 @@ class TB(object):
# cfg_interrupt_msix_int # cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_vec_pending_status
# cfg_interrupt_msix_sent
# cfg_interrupt_msix_fail
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
@ -262,8 +295,6 @@ class TB(object):
self.driver = mqnic.Driver() self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
@ -428,7 +459,7 @@ class TB(object):
self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) await self.rc.enumerate()
async def _run_loopback(self): async def _run_loopback(self):
while True: while True:
@ -461,7 +492,7 @@ async def run_test_nic(dut):
await tb.init() await tb.init()
tb.log.info("Init driver") tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open() await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open() # await tb.driver.interfaces[1].open()

2
tox.ini
View File

@ -18,7 +18,7 @@ deps =
cocotb-test == 0.2.1 cocotb-test == 0.2.1
cocotbext-axi == 0.1.18 cocotbext-axi == 0.1.18
cocotbext-eth == 0.1.18 cocotbext-eth == 0.1.18
cocotbext-pcie == 0.1.22 cocotbext-pcie == 0.2.0
scapy == 2.4.5 scapy == 2.4.5
commands = commands =