From 90c65dfed7b47fac73c863e540f8cc3aa49323e3 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 22 Jul 2022 22:33:38 -0700 Subject: [PATCH 1/4] Fix PBA offsets Signed-off-by: Alex Forencich --- example/DE10_Agilex/fpga/ip/pcie.tcl | 2 +- example/S10DX_DK/fpga/ip/pcie.tcl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/example/DE10_Agilex/fpga/ip/pcie.tcl b/example/DE10_Agilex/fpga/ip/pcie.tcl index 27e137ead..c59267f7c 100644 --- a/example/DE10_Agilex/fpga/ip/pcie.tcl +++ b/example/DE10_Agilex/fpga/ip/pcie.tcl @@ -165,7 +165,7 @@ proc do_create_pcie {} { set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msi_multiple_msg_cap_hwtcl} {1} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_bir_hwtcl} {4} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_offset_hwtcl} {8192.0} + set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_offset_hwtcl} {4096.0} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_offset_hwtcl} {0.0} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_size_hwtcl} {31} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} diff --git a/example/S10DX_DK/fpga/ip/pcie.tcl b/example/S10DX_DK/fpga/ip/pcie.tcl index 882206a2f..db0f775a0 100644 --- a/example/S10DX_DK/fpga/ip/pcie.tcl +++ b/example/S10DX_DK/fpga/ip/pcie.tcl @@ -165,7 +165,7 @@ proc do_create_pcie {} { set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msi_multiple_msg_cap_hwtcl} {1} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_bir_hwtcl} {4} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_offset_hwtcl} {8192.0} + set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_offset_hwtcl} {4096.0} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_offset_hwtcl} {0.0} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_size_hwtcl} {31} set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} From a53509de68cc373473bf06454309a23c5c564d17 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 22 Jul 2022 22:34:04 -0700 Subject: [PATCH 2/4] Add instance names Signed-off-by: Alex Forencich --- example/DE10_Agilex/fpga/rtl/fpga.v | 2 +- example/S10DX_DK/fpga/rtl/fpga.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/example/DE10_Agilex/fpga/rtl/fpga.v b/example/DE10_Agilex/fpga/rtl/fpga.v index b9029876e..187e7b970 100644 --- a/example/DE10_Agilex/fpga/rtl/fpga.v +++ b/example/DE10_Agilex/fpga/rtl/fpga.v @@ -161,7 +161,7 @@ wire [15:0] tl_cfg_ctl; wire [4:0] tl_cfg_add; wire [2:0] tl_cfg_func; -pcie ( +pcie pcie_hip_inst ( .p0_rx_st_ready_i(rx_st_ready), .p0_rx_st_sop_o(rx_st_sop), .p0_rx_st_eop_o(rx_st_eop), diff --git a/example/S10DX_DK/fpga/rtl/fpga.v b/example/S10DX_DK/fpga/rtl/fpga.v index 6ca4ac03a..26f88c213 100644 --- a/example/S10DX_DK/fpga/rtl/fpga.v +++ b/example/S10DX_DK/fpga/rtl/fpga.v @@ -147,7 +147,7 @@ wire [15:0] tl_cfg_ctl; wire [4:0] tl_cfg_add; wire [2:0] tl_cfg_func; -pcie ( +pcie pcie_hip_inst ( .p0_rx_st_ready_i(rx_st_ready), .p0_rx_st_sop_o(rx_st_sop), .p0_rx_st_eop_o(rx_st_eop), From a5fe40cd4217acde57939ac24e5c007ebdc7ea78 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 22 Jul 2022 22:34:26 -0700 Subject: [PATCH 3/4] Fix JTAG index Signed-off-by: Alex Forencich --- example/S10DX_DK/fpga/fpga/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/example/S10DX_DK/fpga/fpga/Makefile b/example/S10DX_DK/fpga/fpga/Makefile index 941412c6d..a1a189e71 100644 --- a/example/S10DX_DK/fpga/fpga/Makefile +++ b/example/S10DX_DK/fpga/fpga/Makefile @@ -48,4 +48,4 @@ SDC_FILES = fpga.sdc include ../common/quartus_pro.mk program: fpga - quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" + quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@2" From 0d9b1d0fb0603776ef720e72fceaca81df57ec0e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 26 Jul 2022 14:01:00 -0700 Subject: [PATCH 4/4] Implement flow control in UltraScale shim Signed-off-by: Alex Forencich --- example/common/rtl/example_core_pcie_us.v | 70 ++++++++++++----------- rtl/pcie_us_if.v | 47 ++++++++++----- rtl/pcie_us_if_rq.v | 33 +++++++++-- tb/pcie_us_if/test_pcie_us_if.py | 4 +- tb/pcie_us_if_rq/test_pcie_us_if_rq.py | 6 ++ 5 files changed, 108 insertions(+), 52 deletions(-) diff --git a/example/common/rtl/example_core_pcie_us.v b/example/common/rtl/example_core_pcie_us.v index d3afe936c..f03b2d292 100644 --- a/example/common/rtl/example_core_pcie_us.v +++ b/example/common/rtl/example_core_pcie_us.v @@ -135,18 +135,7 @@ module example_core_pcie_us # input wire s_axis_rq_seq_num_valid_1, /* - * Flow control - */ - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - /* - * Configuration interface + * Configuration management interface */ output wire [9:0] cfg_mgmt_addr, output wire [7:0] cfg_mgmt_function_number, @@ -158,7 +147,24 @@ module example_core_pcie_us # input wire cfg_mgmt_read_write_done, /* - * Interrupt interface + * Configuration status interface + */ + input wire [2:0] cfg_max_read_req, + input wire [2:0] cfg_max_payload, + + /* + * Configuration flow control interface + */ + input wire [7:0] cfg_fc_ph, + input wire [11:0] cfg_fc_pd, + input wire [7:0] cfg_fc_nph, + input wire [11:0] cfg_fc_npd, + input wire [7:0] cfg_fc_cplh, + input wire [11:0] cfg_fc_cpld, + output wire [2:0] cfg_fc_sel, + + /* + * Configuration interrupt interface */ input wire [3:0] cfg_interrupt_msix_enable, input wire [3:0] cfg_interrupt_msix_mask, @@ -173,12 +179,6 @@ module example_core_pcie_us # input wire cfg_interrupt_msix_fail, output wire [7:0] cfg_interrupt_msi_function_number, - /* - * Configuration - */ - input wire [2:0] cfg_max_read_req, - input wire [2:0] cfg_max_payload, - /* * Status */ @@ -342,18 +342,7 @@ pcie_us_if_inst ( .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration interface + * Configuration management interface */ .cfg_mgmt_addr(cfg_mgmt_addr), .cfg_mgmt_function_number(cfg_mgmt_function_number), @@ -365,7 +354,24 @@ pcie_us_if_inst ( .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), /* - * Interrupt interface + * Configuration status interface + */ + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + + /* + * Configuration flow control interface + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + /* + * Configuration interrupt interface */ .cfg_interrupt_msi_enable(), .cfg_interrupt_msi_vf_enable(), diff --git a/rtl/pcie_us_if.v b/rtl/pcie_us_if.v index 62c429ef8..54b0943da 100644 --- a/rtl/pcie_us_if.v +++ b/rtl/pcie_us_if.v @@ -139,18 +139,7 @@ module pcie_us_if # input wire s_axis_rq_seq_num_valid_1, /* - * Flow control - */ - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - /* - * Configuration interface + * Configuration management interface */ output wire [9:0] cfg_mgmt_addr, output wire [7:0] cfg_mgmt_function_number, @@ -162,7 +151,24 @@ module pcie_us_if # input wire cfg_mgmt_read_write_done, /* - * Interrupt interface + * Configuration status interface + */ + output wire [2:0] cfg_max_payload, + output wire [2:0] cfg_max_read_req, + + /* + * Configuration flow control interface + */ + input wire [7:0] cfg_fc_ph, + input wire [11:0] cfg_fc_pd, + input wire [7:0] cfg_fc_nph, + input wire [11:0] cfg_fc_npd, + input wire [7:0] cfg_fc_cplh, + input wire [11:0] cfg_fc_cpld, + output wire [2:0] cfg_fc_sel, + + /* + * Configuration interrupt interface */ input wire [3:0] cfg_interrupt_msi_enable, input wire [7:0] cfg_interrupt_msi_vf_enable, @@ -405,7 +411,20 @@ pcie_us_if_rq_inst * Transmit sequence number output (DMA write request) */ .m_axis_wr_req_tx_seq_num(m_axis_wr_req_tx_seq_num), - .m_axis_wr_req_tx_seq_num_valid(m_axis_wr_req_tx_seq_num_valid) + .m_axis_wr_req_tx_seq_num_valid(m_axis_wr_req_tx_seq_num_valid), + + /* + * Flow control + */ + .tx_fc_ph_av(tx_fc_ph_av), + .tx_fc_pd_av(tx_fc_pd_av), + .tx_fc_nph_av(tx_fc_nph_av), + .tx_fc_npd_av(tx_fc_npd_av), + + /* + * Configuration + */ + .max_payload_size(cfg_max_payload) ); pcie_us_if_cq #( diff --git a/rtl/pcie_us_if_rq.v b/rtl/pcie_us_if_rq.v index 406e61c06..a0284c338 100644 --- a/rtl/pcie_us_if_rq.v +++ b/rtl/pcie_us_if_rq.v @@ -110,7 +110,20 @@ module pcie_us_if_rq # * Transmit sequence number output (DMA write request) */ output wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num, - output wire [TX_SEQ_NUM_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid + output wire [TX_SEQ_NUM_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid, + + /* + * Flow control + */ + input wire [7:0] tx_fc_ph_av, + input wire [11:0] tx_fc_pd_av, + input wire [7:0] tx_fc_nph_av, + input wire [11:0] tx_fc_npd_av, + + /* + * Configuration + */ + input wire [2:0] max_payload_size ); parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8; @@ -207,6 +220,10 @@ localparam [3:0] REQ_MSG_VENDOR = 4'b1101, REQ_MSG_ATS = 4'b1110; +reg [8:0] max_payload_size_fc_reg = 9'd0; +reg have_p_credit_reg = 1'b0; +reg have_np_credit_reg = 1'b0; + reg frame_reg = 1'b0, frame_next, frame_cyc; reg tlp_hdr1_reg = 1'b0, tlp_hdr1_next, tlp_hdr1_cyc; reg tlp_hdr2_reg = 1'b0, tlp_hdr2_next, tlp_hdr2_cyc; @@ -291,6 +308,8 @@ reg [SEG_SEL_WIDTH+1-1:0] fifo_read_seg_count[0:PORTS-1]; reg [INT_TLP_SEG_COUNT-1:0] fifo_tlp_extra[0:PORTS-1]; +wire [PORTS-1:0] port_have_credit; + // read requests pcie_tlp_fifo_raw #( .DEPTH((1024/4)*2), @@ -359,6 +378,8 @@ rd_req_fifo_inst ( assign fifo_tlp_data[0] = 0; assign fifo_tlp_strb[0] = 0; +assign port_have_credit[0] = have_np_credit_reg; + // write requests pcie_tlp_fifo_raw #( .DEPTH((1024/4)*2), @@ -424,6 +445,8 @@ wr_req_fifo_inst ( .watermark() ); +assign port_have_credit[1] = have_p_credit_reg; + integer port, cur_port, seg, cur_seg, lane; always @* begin @@ -504,7 +527,7 @@ always @* begin tlp_split1_cyc = 1'b0; tlp_split2_cyc = 1'b0; for (port = 0; port < PORTS; port = port + 1) begin - if (port_seg_valid[cur_port][0] && !frame_cyc) begin + if (port_seg_valid[cur_port][0] && port_have_credit[cur_port] && !frame_cyc) begin // select port, set frame frame_cyc = 1'b1; port_cyc = cur_port; @@ -844,9 +867,11 @@ always @* begin end end -integer i; - always @(posedge clk) begin + max_payload_size_fc_reg <= 9'd8 << (max_payload_size > 5 ? 5 : max_payload_size); + have_p_credit_reg <= (tx_fc_ph_av > 4) && (tx_fc_pd_av > (max_payload_size_fc_reg << 1)); + have_np_credit_reg <= tx_fc_nph_av > 4; + frame_reg <= frame_next; tlp_hdr1_reg <= tlp_hdr1_next; tlp_hdr2_reg <= tlp_hdr2_next; diff --git a/tb/pcie_us_if/test_pcie_us_if.py b/tb/pcie_us_if/test_pcie_us_if.py index 1a9c588ea..bea546fc3 100644 --- a/tb/pcie_us_if/test_pcie_us_if.py +++ b/tb/pcie_us_if/test_pcie_us_if.py @@ -166,8 +166,8 @@ class TB(object): # cfg_phy_link_status # cfg_negotiated_width # cfg_current_speed - # cfg_max_payload - # cfg_max_read_req + cfg_max_payload=dut.cfg_max_payload, + cfg_max_read_req=dut.cfg_max_read_req, # cfg_function_status # cfg_vf_status # cfg_function_power_state diff --git a/tb/pcie_us_if_rq/test_pcie_us_if_rq.py b/tb/pcie_us_if_rq/test_pcie_us_if_rq.py index b83226978..5f9bbd80e 100644 --- a/tb/pcie_us_if_rq/test_pcie_us_if_rq.py +++ b/tb/pcie_us_if_rq/test_pcie_us_if_rq.py @@ -71,6 +71,12 @@ class TB(object): dut.s_axis_rq_seq_num_1.setimmediatevalue(0) dut.s_axis_rq_seq_num_valid_1.setimmediatevalue(0) + dut.tx_fc_ph_av.setimmediatevalue(0x80) + dut.tx_fc_pd_av.setimmediatevalue(0x800) + dut.tx_fc_nph_av.setimmediatevalue(0x80) + dut.tx_fc_npd_av.setimmediatevalue(0x800) + dut.max_payload_size.setimmediatevalue(0) + def set_idle_generator(self, generator=None): if generator: self.rd_req_source.set_pause_generator(generator())